MAXIM MAX11646EUA+

19-5134; Rev 0; 1/10
KIT
ATION
EVALU
E
L
B
AVAILA
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
The MAX11646/MAX11647 low-power, 10-bit, 1-/2channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, a clock, and
an I 2 C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11647) or 4.5V to 5.5V (MAX11646) and require
only 670µA at the maximum sampling rate of 94.4ksps.
Supply current falls below 230µA for sampling rates
under 40ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current
to less than 1µA at low throughput rates. The
MAX11646/MAX11647 each measure two single-ended
or one differential input. The fully differential analog
inputs are software configurable for unipolar or bipolar
and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11647 features a 2.048V internal reference and the MAX11646
features a 4.096V internal reference.
The MAX11646/MAX11647 are available in an 8-pin
µMAX® package and are guaranteed over the extended temperature range (-40°C to +85°C). For pin-compatible 12-bit parts, refer to the MAX11644/MAX11645
data sheet.
Features
♦ High-Speed I2C-Compatible Serial Interface
♦
♦
♦
♦
♦
♦
♦
♦
♦
400kHz Fast Mode
1.7MHz High-Speed Mode
Single Supply
2.7V to 3.6V (MAX11647)
4.5V to 5.5V (MAX11646)
Internal Reference
2.048V (MAX11647)
4.096V (MAX11646)
External Reference: 1V to VDD
Internal Clock
2-Channel Single-Ended or 1-Channel Fully
Differential
Internal FIFO with Channel-Scan Mode
Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
Software-Configurable Unipolar/Bipolar
Small, 8-Pin µMAX Package
Ordering Information
Applications
Handheld Portable Applications
PART
TEMP RANGE
PINI2C SLAVE
PACKAGE ADDRESS
MAX11646EUA+
-40°C to +85°C
8 µMAX
0110110
MAX11647EUA+
-40°C to +85°C
8 µMAX
0110110
Medical Instruments
Battery-Powered Test Equipment
Power-Supply Monitoring
Solar-Powered Remote Systems
+Denotes a lead(Pb)-free/RoHs-compliant package.
Received-Signal-Strength Indicators
System Supervision
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX11646/MAX11647
General Description
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
AIN0, AIN1,
REF to GND ...........-0.3V to the lower of (VDD + 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C) ............362mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Bits
Relative Accuracy
INL
(Note 2)
±1
LSB
Differential Nonlinearity
DNL
No missing codes over temperature
±1
LSB
±1
LSB
Offset Error
Offset-Error Temperature
Coefficient
Relative to FSR
Gain Error
(Note 3)
Gain-Temperature Coefficient
Relative to FSR
0.3
ppm/°C
±1
LSB
0.3
ppm/°C
Channel-to-Channel Offset
Matching
±0.1
LSB
Channel-to-Channel Gain
Matching
±0.1
LSB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)
Signal-to-Noise and Distortion
SINAD
60
dB
Up to the fifth harmonic
-70
dB
70
dB
Full-Power Bandwidth
SINAD > 57dB
3.0
MHz
Full-Linear Bandwidth
-3dB point
5.0
MHz
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
CONVERSION RATE
Conversion Time (Note 4)
Throughput Rate
Track/Hold Acquisition Time
2
tCONV
fSAMPLE
Internal clock
External clock
6.8
10.6
Internal clock, SCAN[1:0] = 01
53
External clock
μs
ksps
94.4
800
_______________________________________________________________________________________
ns
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Internal Clock Frequency
Aperture Delay (Note 5)
TYP
MAX
2.8
tAD
External clock, fast mode
60
External clock, high-speed mode
30
UNITS
MHz
ns
ANALOG INPUT (AIN0/AIN1)
Input Voltage Range, SingleEnded and Differential (Note 6)
Input Multiplexer Leakage Current
Input Capacitance
Unipolar
0
VREF
Bipolar
0
±VREF/2
On/off-leakage current, VAIN_ = 0V or VDD
±0.01
CIN
±1
22
V
μA
pF
INTERNAL REFERENCE (Note 7)
Reference Voltage
VREF
Reference-Voltage Temperature
Coefficient
TA = +25°C
MAX11647
1.968
2.048
2.128
MAX11646
3.939
4.096
4.256
25
TCVREF
REF Short-Circuit Current
ppm/°C
2
REF Source Impedance
V
1.5
mA
k
EXTERNAL REFERENCE
REF Input Voltage Range
VREF
(Note 8)
REF Input Current
IREF
fSAMPLE = 94.4ksps
1
VDD
V
40
μA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage
0.7 x VDD
VIH
Input Low Voltage
V
0.3 x VDD
VIL
Input Hysteresis
0.1 x VDD
VHYST
Input Current
IIN
Input Capacitance
CIN
Output Low Voltage
VOL
V
V
±10
VIN = 0V to VDD
15
ISINK = 3mA
μA
pF
0.4
V
POWER REQUIREMENTS
Supply Voltage
VDD
MAX11647
2.7
3.6
MAX11646
4.5
5.5
fSAMPLE = 94.4ksps
external clock
fSAMPLE = 40ksps
internal clock
Supply Current
IDD
fSAMPLE = 10ksps
internal clock
fSAMPLE =1ksps
internal clock
Internal reference
900
1150
External reference
670
900
Internal reference
530
External reference
230
Internal reference
380
External reference
60
Internal reference
330
External reference
6
Shutdown (internal reference off)
0.5
V
μA
10
_______________________________________________________________________________________
3
MAX11646/MAX11647
ELECTRICAL CHARACTERISTICS (continued)
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.01
±0.5
LSB/V
POWER REQUIREMENTS
Power-Supply Rejection Ratio
PSRR
Full-scale input (Note 9)
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF
1.3
μs
Hold Time for a START (S)
Condition
tHD:STA
0.6
μs
Low Period of the SCL Clock
tLOW
1.3
μs
High Period of the SCL Clock
tHIGH
0.6
μs
Setup Time for a REPEATED
START Condition (Sr)
tSU:STA
0.6
μs
Data Hold Time
tHD:DAT
Data Setup Time
tSU:DAT
(Note 10)
0
900
100
ns
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
Measured from 0.3VDD to 0.7VDD
20 +
0.1CB
300
ns
Fall Time of SDA Transmitting
tF
Measured from 0.3VDD to 0.7VDD (Note 11)
20 +
0.1CB
300
ns
Setup Time for a STOP (P)
Condition
0.6
tSU:STO
μs
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
1.7
MHz
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)
Serial-Clock Frequency
Hold Time, REPEATED START
Condition (Sr)
fSCLH
(Note 13)
tHD:STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a REPEATED
START Condition (Sr)
tSU:STA
160
ns
Data Hold Time
tHD:DAT
Data Setup Time
tSU:DAT
4
(Note 10)
0
10
_______________________________________________________________________________________
150
ns
ns
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
Measured from 0.3VDD to 0.7VDD
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
Measured from 0.3VDD to 0.7VDD
20
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD to 0.7VDD
20
80
ns
Rise Time of SDA Signal
tRDA
Measured from 0.3VDD to 0.7VDD
20
160
ns
Fall Time of SDA Signal
tFDA
Measured from 0.3VDD to 0.7VDD (Note 11)
20
160
ns
Setup Time for a STOP (P)
Condition
tSU:STO
Capacitive Load for Each Bus
Line
CB
Pulse Width of Spike Suppressed
tSP
160
(Notes 10 and 13)
0
ns
400
pF
10
ns
Note 1: For DC accuracy, the MAX11646 is tested at VDD = 5V and the MAX11647 is tested at VDD = 3V, with an external reference
for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to VDD.
Note 7: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a 0.1µF capacitor
and a 2kΩ series resistor (see the Typical Operating Circuit).
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 9: Measured as follows for the MAX11647:
⎡
2N ⎤
⎢ ⎡⎣ VFS (3 . 6V) − VFS (2 . 7V) ⎤⎦ ×
⎥
VREF ⎥⎦
⎢⎣
(3 . 6V − 2 . 7V)
and for the MAX11646, where N is the number of bits:
⎡
2N ⎤
⎢ ⎡⎣ VFS (5 . 5V) − VFS (4 . 5V) ⎤⎦ ×
⎥
VREF ⎥⎦
⎢⎣
(5 . 5V − 4 . 5V)
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 11: The minimum value is specified at TA = +25°C.
Note 12: CB = total capacitance of one bus line in pF.
Note 13: fSCL must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________
5
MAX11646/MAX11647
TIMING CHARACTERISTICS (Figure 1) (continued)
Typical Operating Characteristics
(VDD = 3.3V (MAX11647), VDD = 5V (MAX11646), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar,
TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.4
0.3
-0.1
AMPLITUDE (dBc)
INL (LSB)
0.1
0
-0.1
-0.2
-140
200
400
600
800
400
600
800
0
1000
20k
30k
40k
FREQUENCY (Hz)
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11647
EXTERNAL REFERENCE
MAX11646
0.5
IDD (μA)
0.4
0.3
0.2
450
EXTERNAL REFERENCE
0.50
0.45
0.35
0.30
0.25
0.20
MAX11647
0.15
0.10
0.1
MAX11647
MAX11646
0.40
SUPPLY CURRENT (μA)
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
INTERNAL REFERENCE
SDA = SCL = VDD
50k
MAX11646 toc06
MAX11646 toc04
MAX11646
INTERNAL REFERENCE
0.6
350
0.05
0
300
-40 -25 -10
5
20
35
50
65
80
0
3.2
2.7
3.7
TEMPERATURE (°C)
4.2
4.7
5.2
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
700
B
600
500
400
1.0008
35
NORMALIZED TO REFERENCE VALUE
TA = +25°C
1.0006
MAX11646
1.0004
1.0002
1.0000
0.9998
300
0.9996
200
0.9994
100
0.9992
0
20
1.0010
VREF NORMALIZED
AVERAGE IDD (μA)
800
A
5
MAX11647
0.9990
0
20
40
60
CONVERSION RATE (ksps)
80
100
50
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11646 toc07
1000
900
-40 -25 -10
SUPPLY VOLTAGE (V)
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
6
10k
DIGITAL OUTPUT CODE
700
400
200
DIGITAL OUTPUT CODE
800
500
0
1000
MAX11646 toc05
0
550
-160
-0.5
-0.3
600
-100
-120
-0.4
650
-80
-0.3
-0.2
750
-60
MAX11646 toc08
DNL (LSB)
0
fSAMPLE = 94.4ksps
fIN = 10kHz
-20
-40
0.2
0.1
0
MAX11646 toc02
0.2
FFT PLOT
0.5
MAX11646 toc01
0.3
MAX11646 toc03
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SUPPLY CURRENT (μA)
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
-40 -25
-10
5
20
35
50
65
TEMPERATURE (°C)
_______________________________________________________________________________________
80
65
80
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.00004
-0.1
-0.2
1.00000
0.99998
0.99996
0.99994
0.99992
MAX11646 toc10
MAX11646,
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
1.00002
MAX11647,
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
0.99990
-40 -25 -10
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
5
20
35
50
65
80
TEMPERATURE (°C)
VDD (V)
OFFSET ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
-0.1
-0.2
MAX11646 toc12
1.0
MAX11646 toc11
0
0.9
0.8
GAIN ERROR (LSB)
-0.3
-0.4
-0.5
-0.6
0.7
0.6
0.5
0.4
-0.7
0.3
-0.8
0.2
-0.9
0.1
-1.0
0
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
-40 -25 -10
VDD (V)
5
20
35
50
65
80
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11646 toc13
1.0
0.9
0.8
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
VREF NORMALIZED
1.00006
OFFSET ERROR (LSB)
1.00008
OFFSET ERROR vs. TEMPERATURE
0
MAX11646 toc09
1.00010
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.7
3.2
3.7
4.2
4.7
5.2
VDD (V)
_______________________________________________________________________________________
7
MAX11646/MAX11647
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX11647), VDD = 5V (MAX11646), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar,
TA = +25°C, unless otherwise noted.)
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
MAX11646/MAX11647
Pin Configuration
TOP VIEW
+
AIN0 1
AIN1 2
N.C.
3
MAX11646
MAX11647
REF 4
8
VDD
7
GND
6
SDA
5
SCL
μMAX
Pin Description
PIN
NAME
FUNCTION
1, 2
AIN0, AIN1
3
N.C.
Analog Inputs
No Connection. Not internally connected.
4
REF
Reference Input/Output. Selected in the setup register (see Tables 1 and 6).
5
SCL
Clock Input
6
SDA
Data Input/Output
7
GND
Ground
8
VDD
Positive Supply. Bypass to GND with a 0.1µF capacitor.
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
tR
tF
t
SDA
tSU:DAT
tHD:DAT
tLOW
tHD:STA
tBUF
tSU:STA
tSU:STO
SCL
tHD:STA
tHIGH
tR
tF
S
A
Sr
P
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
S
tRDA
tFDA
SDA
tSU:DAT
tHD:DAT
tLOW
tBUF
tHD:STA
tSU:STO
tSU:STA
SCL
tHD:STA
tHIGH
tRCL
tFCL
tRCL1
S
Sr
A
P
HS MODE
Figure 1. 2-Wire Serial-Interface Timing
8
_______________________________________________________________________________________
S
F/S MODE
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
MAX11646/MAX11647
SDA
SCL
INPUT SHIFT REGISTER
VDD
CONTROL
LOGIC
SETUP REGISTER
GND
INTERNAL
OSCILLATOR
CONFIGURATION REGISTER
AIN0
AIN1
10-BIT
ADC
T/H
ANALOG
INPUT
MUX
REF
OUTPUT SHIFT
REGISTER
AND RAM
REF
REFERENCE
4.096V (MAX11646)
2.048V (MAX11647)
MAX11646
MAX11647
Figure 2. Functional Diagram
Power Supply
VDD
IOL
VOUT
SDA
400pF
IOH
Figure 3. Load Circuit
Detailed Description
The MAX11646/MAX11647 ADCs use successiveapproximation conversion techniques and fully differential input T/H circuitry to capture and convert an analog
signal to a serial 10-bit digital output. The
MAX11646/MAX11647 measure either two singleended inputs or one differential input. These devices
feature a high-speed, 2-wire serial interface supporting
data rates up to 1.7MHz. Figure 2 shows the simplified
internal structure for the MAX11646/MAX11647.
The MAX11646/MAX11647 operate from a single supply
and consume 670µA (typ) at sampling rates up to
94.4ksps. The MAX11647 features a 2.048V internal reference and the MAX11646 features a 4.096V internal reference. These devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/Hold
The MAX11646/MAX11647 analog input architecture
contains an analog input multiplexer (mux), a fully differential T/H capacitor, T/H switches, a comparator,
and a fully differential switched capacitive digital-toanalog converter (DAC) (Figure 4).
In single-ended mode, the analog-input multiplexer connects CT/H between the analog input selected by CS0
(see the Configuration/Setup Bytes (Write Cycle) section) and GND (Table 3). In differential mode, the analog
input multiplexer connects CT/H to the + and - analog
inputs selected by CS0 (Table 4).
During the acquisition interval, the T/H switches are in
the track position and CT/H charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/H as a stable sample of the input signal.
_______________________________________________________________________________________
9
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕ (VIN+ - VIN-) from
CT/H to the binary-weighted capacitive DAC, forming a
digital representation of the analog input signal.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capacitance. If the analog input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the Slave Address section). The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion or a series of conversions is then
internally clocked and the MAX11646/MAX11647 hold
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W = 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 10
clock cycles.
tACQ ≥ 9 ✕ (RSOURCE + RIN) ✕ CIN
where RSOURCE is the analog input source impedance,
RIN = 2.5kΩ, and CIN = 22pF. tACQ is 1.5/fSCL for internal
clock mode and tACQ = 2/fSCL for external clock mode.
Analog Input Bandwidth
The MAX11646/MAX11647 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
VDD and GND. These diodes allow the analog inputs to
swing from (VGND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above VDD.
HOLD
ANALOG INPUT MUX
REF
CT/H
AIN0
HOLD
GND
TRACK
VDD/2
HOLD
AIN1
CAPACITIVE
DAC
TRACK
HOLD
TRACK
TRACK
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
TRACK
CAPACITIVE
DAC
CT/H
HOLD
REF
MAX11646
MAX11647
Figure 4. Equivalent Input Circuit
10
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is binary in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11646/MAX11647
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX11646/MAX11647 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communication between the MAX11646/MAX11647 and the master
at rates up to 1.7MHz. The MAX11646/MAX11647 are
slaves that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional.
They protect the input architecture of the MAX11646/
MAX11647 from high voltage spikes on the bus lines,
minimize crosstalk, and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11646/
MAX11647. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in
SDA while SCL is stable are considered control signals
(see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see the HS Mode section).
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11646/MAX11647 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Sr
S
P
SDA
SCL
Figure 5. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
SCL
1
2
8
9
Figure 6. Acknowledge Bits
______________________________________________________________________________________
11
MAX11646/MAX11647
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11646/MAX11647 analog input circuitry for singleended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS0 and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the difference between the + and the - analog inputs selected
by CS0 (Table 4).
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
DEVICE
SLAVE ADDRESS
MAX11646/MAX11647
0110110
SLAVE ADDRESS
S
0
1
1
0
1
1
0
R/W
A
SDA
1
SCL
2
3
4
5
6
7
8
9
Figure 7. Slave Address Byte
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX11646/MAX11647 continuously wait for a START condition followed by their slave
address. When the MAX11646/MAX11647 recognize their
slave address, they are ready to accept or send data.
The slave address has been factory programmed and is
always 0110110 for the MAX11646/MAX11647 (Figure 7).
The least significant bit (LSB) of the address byte (R/W)
determines whether the master is writing to or reading
from the MAX11646/MAX11647 (R/W = 0 selects a write
condition, R/W = 1 selects a read condition). After receiving the address, the MAX11646/MAX11647 (slave) issue
an acknowledge by pulling SDA low for one clock cycle.
high-speed mode (HS mode) to achieve conversion
rates up to 94.4ksps. Figure 1 shows the bus timing for
the MAX11646/MAX11647’s 2-wire interface.
HS Mode
At power-up, the MAX11646/MAX11647 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the
MAX11646/MAX11647 issue a not-acknowledge, allowing SDA to be pulled high for one clock cycle
(Figure 8). After the not-acknowledge, the MAX11646/
MAX11647 are in HS mode. The bus master must then
send a repeated START followed by a slave address to
initiate HS-mode communication. If the master generates a STOP condition the MAX11646/MAX11647 return
to F/S mode.
Bus Timing
At power-up, the MAX11646/MAX11647 bus timing is set
for fast mode (F/S mode), allowing conversion rates up to
22.2ksps. The MAX11646/MAX11647 must operate in
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
12
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
ration byte (Table 2). The master can write either 1 or 2
bytes to the slave in any order (setup byte then configuration byte, configuration byte then setup byte, setup
byte or configuration byte only; see Figure 9). If the
slave receives a byte successfully, it issues an acknowledge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the bus
into F/S mode (see the HS Mode section).
MASTER TO SLAVE
SLAVE TO MASTER
A. 1-BYTE WRITE CYCLE
1
7
1 1
S
SLAVE ADDRESS
W A
1
8
1
NUMBER OF BITS
SETUP OR
A P or Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. 2-BYTE WRITE CYCLE
7
1
S
1 1
1
8
SETUP OR
W A
CONFIGURATION BYTE
SLAVE ADDRESS
A
8
1
1
NUMBER OF BITS
SETUP OR
A P or Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
NAME
7
REG
6
SEL2
5
SEL1
4
SEL0
3
CLK
2
BIP/UNI
1
RST
0
X
DESCRIPTION
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
Three bits select the reference voltage (Table 6). Default to 000 at power-up.
1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
______________________________________________________________________________________
13
MAX11646/MAX11647
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 7)
and a write bit (R/W = 0). If the address byte is successfully received, the MAX11646/MAX11647 (slave) issue
an acknowledge. The master then writes to the slave.
The slave recognizes the received byte as the setup
byte (Table 1) if the most significant bit (MSB) is 1. If the
MSB is 0, the slave recognizes that byte as the configu-
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Table 2. Configuration Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SCAN1
SCAN0
X
X
X
CS0
SGL/DIF
BIT
NAME
7
REG
6
SCAN1
5
SCAN0
4
X
3
X
2
X
1
CS0
0
SGL/DIF
DESCRIPTION
Register bit. 1= setup byte (see Table 1), 0 = configuration byte.
Scan-select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.
Channel-select bit. CS0 selects which analog input channels are to be used for conversion
(Tables 3 and 4). Defaults to 0000 at power-up.
1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the SingleEnded/Differential Input section.
X = Don’t care.
Table 3. Channel Selection in SingleEnded Mode (SGL/DIF = 1)
CS0
AIN0
0
+
1
AIN1
+
Table 4. Channel Selection in Differential
Mode (SGL/DIF = 0)
GND
CS0
AIN0
AIN1
-
0
+
-
1
-
+
-
X = Don’t care.
X = Don’t care.
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11646/MAX11647 (slave) issue an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 6 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s),
it can issue an acknowledge if it wants to continue
reading or a not-acknowledge if it no longer wishes to
read. If the MAX11646/MAX11647 receive a not-
acknowledge, they release SDA, allowing the master to
generate a STOP or a repeated START condition. See
the Clock Modes and Scan Mode sections for detailed
information on how data is obtained and converted.
14
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the setup byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11646/MAX11647 are defaulted
to internal clock mode (CLK = 0).
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
order the scan conversion has been done at a clock
rate of up to 1.7MHz. SCL is stretched for a maximum
of 7.6µs per channel (see Figure 10).
The device memory contains all of the conversion results
when the MAX11646/MAX11647 release SCL. The converted results are read back in a first-in/first-out (FIFO)
sequence. The memory contents can be read continuously. If reading continues past the result stored in
memory, the pointer wraps around and point to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during conversion. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
CLOCK STRETCH
RESULT 2 MSBs
8
A
RESULT 8 LSBs
1
1
NUMBER OF BITS
A P or Sr
tACQ
tCONV
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
CLOCK STRETCH
tACQ1
tCONV1
tACQ2
tCONV2
CLOCK STRETCH
1
8
1
RESULT 1 ( 2MSBs) A RESULT 1 (8 LSBs) A
8
1
8
1
1
NUMBER OF BITS
RESULT N (8MSBs) A RESULT N (8LSBs) A P or Sr
tACQN
tCONVN
Figure 10. Internal Clock Mode Read Cycles
______________________________________________________________________________________
15
MAX11646/MAX11647
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11646/MAX11647 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11646/MAX11647 begin tracking the analog input
after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11646/
MAX11647 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conversions, they all happen in succession with each additional result stored in memory. The MAX11646/
MAX11647 contain two 10-bit blocks of memory. Once
all conversions are complete, the MAX11646/MAX11647
release SCL, allowing it to be pulled high. The master can
now clock the results out of the memory in the same
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
External Clock
When configured for external clock mode (CLK = 1),
the MAX11646/MAX11647 use the SCL as the conversion clock. In external clock mode, the MAX11646/
MAX11647 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
converted data is available immediately after the first
four empty high bits. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to re-address the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX11646/MAX11647 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps internal clock mode is recommended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to memory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission, the first byte
begins with six empty bits during which SDA is left
high. Each byte has to be acknowledged by the master
or the memory transmission is terminated. It is not possible to read the memory independently of conversion.
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1 1
8
1
8
1
1
S
SLAVE ADDRESS
R A
RESULT (2 MSBs)
A
RESULT (8 LSBs)
A
P OR Sr
NUMBER OF BITS
tACQ
tCONV
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
RESULT 1 (2 MSBs)
1
8
1
8
1
8
A
RESULT 2 (8 LSBs)
A
RESULT N (2 MSBs)
A
RESULT N (8 LSBs)
tACQ2
tACQN
tACQ1
tCONV1
1
1
NUMBER OF BITS
A P OR Sr
tCONVN
Figure 11. External Clock Mode Read Cycle
Table 5. Scanning Configuration
SCAN1
SCAN0
0
0
Scans up from AIN0 to the input selected by CS0.
SCANNING CONFIGURATION
0
1
Converts the input selected by CS0 eight times (see Tables 3 and 4).*
1
0
Reserved. Do not use.
1
1
Converts input selected by CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not acknowledge occurs.
16
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference. The memory contents are unknown after power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11646/MAX11647 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, notacknowledge, or repeated START condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not necessary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all conversion results are written to memory (Figure 10). When
using an external reference or VDD as a reference, all
analog circuitry is inactive in shutdown and supply current is less than 0.5µA (typ). The digital conversion
results obtained in internal clock mode are maintained
in memory during shutdown and are available for
access through the serial interface at any time prior to a
STOP or a repeated START condition.
When idle, the MAX11646/MAX11647 continuously wait
for a START condition followed by their slave address
(see the Slave Address section). Upon reading a valid
address byte the MAX11646/MAX11647 power up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up
10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
or VDD as the reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11647 is 60µA (typ)
and drops to 6µA (typ) at 1ksps. At 0.1ksps the average supply current is just 1µA, or a minuscule 3µW of
power consumption (see Average Supply Current vs.
Conversion Rate (External Clock) in the Typical Operating
Characteristics).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference
and the REF configuration (Table 6).
Internal Reference
The internal reference is 4.096V for the MAX11646 and
2.048V for the MAX11647. When REF is configured to be
an internal reference output (SEL[2:1] = 11), decouple
REF to GND with a 0.1µF capacitor and a 2kΩ series
resistor (see the Typical Operating Circuit). Once powered
up, the reference always remains on until reconfigured.
The internal reference requires 10ms to wake up and is
accessed using SEL0 (Table 6). When in shutdown, the
internal reference output is in a high-impedance state. The
reference should not be used to supply current for external circuitry. The internal reference does not require an
external bypass capacitor and works best when left
unconnected (SEL1 = 0).
External Reference
The external reference can range from 1V to VDD. For
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output impedance of 500Ω or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close
as possible to REF with a 0.1µF capacitor.
Table 6. Reference Voltage and REF Format
SEL2
SEL1
SEL0
REFERENCE VOLTAGE
REF
INTERNAL REFERENCE STATE
0
0
X
0
1
X
VDD
Not connected
Always off
External reference
Reference input
1
0
0
Internal reference
Always off
Not connected*
Always off
1
0
1
1
1
0
Internal reference
Not connected*
Always on
Internal reference
Reference output
1
1
1
Always off
Internal reference
Reference output
Always on
X = Don’t care.
*Preferred configuration for internal reference.
______________________________________________________________________________________
17
MAX11646/MAX11647
Applications Information
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Transfer Functions
Layout, Grounding, and Bypassing
Output data coding for the MAX11646/MAX11647 is
binary in unipolar mode and two’s complement in bipolar mode with 1 LSB = (VREF/2N) where N is the number
of bits (10). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13
show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively.
Only use PCBs. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog
and digital lines parallel to each other, and do not lay
out digital signal paths underneath the ADC package.
Use separate analog and digital PCB ground sections
with only one star point (Figure 14) connecting the two
ground systems (analog and digital). For lowest noise
operation, ensure the ground return to the star ground’s
power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog
and reference inputs.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
MAX11646
MAX11647
11 . . . 110
11 . . . 101
FS = VREF
ZS = GND
V
1 LSB = REF
1024
00 . . . 011
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX11646/MAX11647 powersupply pin. Minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5Ω)
in series with the power supply if it is extremely noisy.
Definitions
00 . . . 010
00 . . . 001
Integral Nonlinearity
00 . . . 000
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once offset
and gain errors have been nullified. The MAX11646/
MAX11647’s INL is measured using the endpoint.
0
1
2
3
FS
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 12. Unipolar Transfer Function
OUTPUT CODE
011 . . . 111
V
FS = REF
2
011 . . . 110
ZS = 0
000 . . . 010
000 . . . 001
MAX11646
MAX11647
SUPPLIES
3V OR 5V
-VREF
2
V
1 LSB = REF
1024
VLOGIC = 3V/5V
GND
-FS =
000 . . . 000
4.7μF
R* = 5Ω
111 . . . 111
111 . . . 110
0.1μF
111 . . . 101
VDD
GND
3V/5V
DGND
100 . . . 001
100 . . . 000
0
- FS
MAX11646
MAX11647
+FS - 1 LSB
INPUT VOLTAGE (LSB)
*VCOM ≥ VREF/2
*VIN = (AIN+) - (AIN-)
Figure 13. Bipolar Transfer Function
18
*OPTIONAL
Figure 14. Power-Supply Grounding Connection
______________________________________________________________________________________
DIGITAL
CIRCUITRY
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNRMAX[dB] = 6.02dB ✕ N + 1.76dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
⎡
⎤
SignalRMS
SINAD(dB) = 20 × log ⎢
⎥
⎣ NoiseRMS + THDRMS ⎦
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as:
⎛
THD = 20 × log ⎜⎜
⎜
⎝
⎛ V 2 +V 2 +V 2 +V 2 ⎞ ⎞
3
4
5 ⎟⎟
⎜ 2
⎜
⎟⎟
V
1
⎝
⎠⎟
⎠
where V1 is the fundamental amplitude, and V2 through V5
are the amplitudes of the 2nd through 5th order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion
component.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 ✕ log (SignalRMS/NoiseRMS)
______________________________________________________________________________________
19
MAX11646/MAX11647
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
MAX11646/MAX11647
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Typical Operating Circuit
Selector Guide
3.3V or 5V
PART
0.1μF
INTERNAL
SUPPLY
INPUT
INL
REFERENCE VOLTAGE
CHANNELS
(LSB)
(V)
(V)
VDD
RS*
ANALOG
INPUTS
AIN0
AIN1
MAX11646
2 SingleEnded/1
Differential
4.096
4.5 to 5.5
±1
MAX11647
2 SingleEnded/1
Differential
2.048
2.7 to 3.6
±1
SDA
MAX11646
MAX11647
SCL
RS*
RC NETWORK* 2kΩ
CREF
0.1μF
REF
GND
Chip Information
5V
RP
SDA
SCL
*OPTIONAL
PROCESS: BiCMOS
Package Information
5V
μC
RP
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 µMAX
U8CN+1
21-0036
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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