19-4794; Rev 0; 11/98 KIT ATION EVALU E L B A AVAIL +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC ♦ Monolithic, 14-Bit, 1Msps ADC ♦ +5V Single Supply ♦ SNR of 80dB for fIN = 500kHz ♦ SFDR of 87dB for fIN = 500kHz ♦ Low Power Dissipation: 257mW ♦ On-Demand Self-Calibration ♦ Differential Nonlinearity Error: ±0.3LSB ♦ Integral Nonlinearity Error: ±1.2LSB ♦ Three-State, Two’s Complement Output Data Ordering Information PART TEMP. RANGE MAX1205CMH 0°C to +70°C 44 MQFP PIN-PACKAGE MAX1205EMH -40°C to +85°C 44 MQFP TEST0 34 35 RFPS RFPF CM 36 37 38 INP RFNS RFNF 39 40 41 INN N.C. N.C. 42 Applications END_CAL TOP VIEW 43 Pin Configuration 44 The MAX1205 is a 14-bit, monolithic, analog-to-digital converter (ADC) capable of conversion rates up to 1Msps. This integrated circuit, built on a CMOS process, uses a fully differential, pipelined architecture with digital error correction and a short self-calibration procedure that corrects for capacitor and gain mismatches and ensures 14-bit linearity at full sample rates. An on-chip track/hold (T/H) maintains superb dynamic performance up to the Nyquist frequency. The MAX1205 operates from a single +5V supply. The fully differential inputs allow an input swing of ±VREF. The reference is also differential, with the positive reference (RFPF) typically connected to +4.096V and the negative reference (RFNF) connected to analog ground. Additional sensing pins (RFPS, RFNS) are provided to compensate for any resistive-divider action that may occur due to finite internal and external resistances in the reference traces and the on-chip resistance of the reference pins. A single-ended input is also possible using two operational amplifiers. The power dissipation is typically 257mW at +5V, at a sampling rate of 1Msps. The device employs a CMOScompatible, 14-bit parallel, two’s complement output data format. For higher sampling rates, the MAX1201 is a 2.2Msps pin-compatible upgrade to the MAX1205. The MAX1205 is available in an MQFP package, and operates over the commercial (0°C to +70°C) and the extended (-40°C to +85°C) temperature ranges. Features Imaging 32 3 31 AGND AGND AVDD DOR D13 D12 D11 D10 4 30 5 29 6 28 MAX1205 21 22 20 D1 DGND D5 D9 D8 19 23 18 24 11 D4 D3 D2 25 10 17 26 9 16 27 8 15 7 12 Data Acquisition 33 2 14 Scanners 1 D7 D6 DRVDD Medical ST_CAL AGND AVDD 13 Communications OE DAV CLK DVDD DGND DGND DVDD TEST1 TEST2 TEST3 D0 MQFP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1205 General Description MAX1205 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC ABSOLUTE MAXIMUM RATINGS AVDD to AGND, DGND ..........................................................+7V DVDD to DGND, AGND..........................................................+7V DRVDD to DGND, AGND .......................................................+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM.................................(AGND - 0.3V) to (AVDD + 0.3V) Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V) Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V) Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C)........889mW Operating Temperature Ranges (TA) MAX1205CMH .....................................................0°C to +70°C MAX1205EMH ..................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK= 2.048MHz, digital output load ≤ 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Input Voltage Range (Notes 2, 3) VIN Input Resistance (Note 4) RI Input Capacitance (Note 3) CI Single-ended Differential Per side in track mode 4.096 4.5 ±4.096 ±4.5 V 55 kΩ 21 pF REFERENCE/EXTERNAL Reference Voltage (Note 3) 4.096 VREF 700 Reference Input Resistance 4.5 V Ω 1000 TRANSFER CHARACTERISTICS Resolution (no missing codes) (Note 5) RES Integral Nonlinearity INL Differential Nonlinearity DNL After calibration, guaranteed 14 Bits ±1.2 LSB -1 ±0.3 +1 LSB Offset Error -0.2 ±0.003 +0.2 %FSR Gain Error -5 -3.0 +5 Input-Referred Noise %FSR 75 µVRMS 4 fSAMPLE Cycles 100 ns ns DYNAMIC SPECIFICATIONS (Note 6) Maximum Sampling Rate fSAMPLE fSAMPLE = fCLK / 2 Conversion Time (Pipeline Delay/Latency) Msps Acquisition Time tACQ Overvoltage Recovery Time tOVR 410 Aperture Delay tAD 3 ns Full-Power Bandwidth 3.3 MHz Small-Signal Bandwidth 78 MHz 2 To full-scale step (0.006%) 1.024 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK= 2.048MHz, digital output load ≤ 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Signal-to-Noise Ratio (Note 5) Spurious-Free Dynamic Range (Note 5) Total Harmonic Distortion (Note 5) Signal-to-Noise Ratio plus Distortion (Note 5) SYMBOL CONDITIONS fIN = 99.5kHz SNR THD 83 81.5 fIN = 504.5kHz 80 84 88 fIN = 504.5kHz 87 fIN = 99.5kHz -86 fIN = 300.5kHz -85 fIN = 504.5kHz -84 77 MAX UNITS dB 91 fIN = 300.5kHz fIN = 99.5kHz SINAD TYP 78 fIN = 300.5kHz fIN = 99.5kHz SFDR MIN dB -80 dB 82 fIN = 300.5kHz 79 fIN = 504.5kHz 78 dB POWER REQUIREMENTS Analog Supply Voltage AVDD Analog Supply Current I(AVDD) Digital Supply Voltage DVDD Digital Supply Current I(DVDD) Output Drive Supply Voltage DRVDD Output Drive Supply Current I(DRVDD) Power Dissipation 4.75 5 5.25 V 51 70 mA 5.25 V 1.2 mA 3 0.4 3 10pF loads on D0–D13 and DAV PDSS Warm-Up Time DVDD V 0.1 0.6 mA 257 377 mW 0.1 Power-Supply Rejection Ratio PSRR Offset 55 Gain 55 sec dB _______________________________________________________________________________________ 3 MAX1205 ELECTRICAL CHARACTERISTICS (continued) MAX1205 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC TIMING CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Conversion Time tCONV 4 / fSAMPLE ns Clock Period tCLK 488 ns Clock High Time tCH 187 244 301 ns Clock Low Time tCL 187 244 301 ns Acquisition Time tACQ tCLK / 2 Output Delay tOD 70 DAV Pulse Width tDAV 1 / fCLK tS 65 145 ns 16 75 ns 16 75 CLK-to-DAV Rising Edge Data Access Time tAC Bus Relinquish Time tREL Calibration Time tCAL CL = 20pF ST_CAL = 1, Figure 8 ns 150 ns ns ns fCLK cycles 17,400 DIGITAL INPUTS AND OUTPUTS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Input Low Voltage VIL Input High Voltage VIH CONDITIONS MIN CLK Input Capacitance CCLK Digital Input Current IIN_ Clock Input Current ICLK Output Low Voltage VOL Three-State Output Capacitance V V CLKVIL CLKVIH Three-State Leakage Current UNITS 0.8 4 CLK Input High Voltage Output High Voltage MAX DVDD - 0.8 Input Capacitance CLK Input Low Voltage TYP VOH pF 0.8 AVDD - 0.8 V 9 VIN_ = 0 or DVDD pF ±0.1 ±10 µA -10 ±1 +10 µA 70 400 mV DVDD - 0.4 DVDD - 0.03 ISINK = 1.6mA ISOURCE = 200µA V ILEAKAGE ±0.1 COUT 3.5 V ±10 µA pF Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation. Note 2: For unipolar mode, the analog input voltage VINP must be within 0V and VREF, VINN = VREF / 2; where VREF = VRFPS - VRFNS. For differential mode, the analog inputs INP and INN must be within 0V and VREF; where VREF = VRFPS - VRFNS. The common mode of the inputs INP and INN is VREF / 2. Note 3: Minimum and maximum parameters are not tested. Guaranteed by design. Note 4: RI varies inversely with sample rate. Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Note 6: All AC specifications are shown for the differential mode. 4 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC 1.00 0.75 SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 99.5kHz) 120 MAX1205-02 1.0 MAX1205-01 1.25 DIFFERENTIAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE 100 0.5 0 -0.25 SFDR (dB) 90 0.25 DNL (LSB) 0 80 70 60 -0.50 -0.5 -0.75 50 -1.00 40 -1.25 -8192 -6144 -4096 -2048 0 -80 -70 -60 -50 -40 -30 -20 INPUT AMPLITUDE (dBFS) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY AIN = -20dBFS -78 72 AIN = -6dBFS -82 -84 70 AIN = -0.5dBFS 80 SNR (dB) THD (dB) 74 0 85 AIN = -6dBFS -80 AIN = -6dBFS -10 MAX1205-06 MAX1205-04 -76 80 78 30 2048 4096 6144 8192 TWO’S COMPLEMENT OUTPUT CODE AIN = -0.5dBFS 76 dBc TWO’S COMPLEMENT OUTPUT CODE 84 82 -1.0 -8192 -6144 -4096 -2048 0 2048 4096 6144 8192 MAX1205-05 75 70 -86 68 65 AIN = -0.5dBFS -88 66 AIN = -20dBFS -90 64 1 10 AIN = -20dBFS 100 1000 60 1 10 100 1000 10 AIN = -0.5dBFS 1000 TYPICAL FFT (fIN = 99.5kHz, 2048 VALUE RECORD) MAX1205-07 85 100 INPUT FREQUENCY (kHz) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. SAMPLING RATE (fIN = 99.5kHz) -15 -30 AMPLITUDE (dBFS) 84 SINAD (dB) 1 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) MAX1205-08 INL (LSB) dBFS 110 0.50 SINAD (dB) MAX1205-03 INTEGRAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE 83 82 81 -45 -60 -75 -90 -105 -120 -135 80 0 0.1 1 SAMPLE RATE (Msps) 0 100 200 300 400 500 600 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX1205 Typical Operating Characteristics (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, differential input, fCLK= 2.048MHz, calibrated, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, differential input, fCLK= 2.048MHz, calibrated, TA = +25°C, unless otherwise noted.) EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY TYPICAL FFT (fIN = 504.5kHz, 2048 VALUE RECORD) MAX1205-10 14.0 MAX1205-09 -15 AIN = -0.5dBFS 13.5 -30 13.0 -45 ENOB (Bits) AMPLITUDE (dBFS) MAX1205 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC -60 -75 -90 AIN = -6dBFS 12.5 12.0 11.5 -105 11.0 -120 AIN = -20dBFS 10.5 -135 0 10.0 0 100 200 300 400 500 1 600 FREQUENCY (kHz) 10 100 1000 INPUT FREQUENCY (kHz) Pin Description PIN NAME FUNCTION Digital Input to Start Calibration. ST_CAL = 0: Normal conversion mode. ST_CAL = 1: Start self-calibration. 1 ST_CAL 2, 4, 5 AGND Analog Ground 3, 6 AVDD Analog Power Supply, +5V ±5% 7 DOR Data Out-of-Range Bit 8 D13 Bit 13 (MSB) 9 D12 Bit 12 10 D11 Bit 11 11 D10 Bit 10 12 D9 Bit 9 13 D8 Bit 8 14 D7 Bit 7 15 D6 Bit 6 16 DRVDD Digital Power Supply for the Output Drivers, +3V to +5.25V, DRVDD ≤ DVDD 17, 28, 29 DGND Digital Ground 18 D5 Bit 5 19 D4 Bit 4 20 D3 Bit 3 21 D2 Bit 2 22 D1 Bit 1 23 D0 Bit 0 (LSB) 24 TEST3 6 Test Pin 3. Leave unconnected. _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC PIN NAME FUNCTION 25 TEST2 Test Pin 2. Leave unconnected. 26 TEST1 Test Pin 1. Leave unconnected. 27, 30 DVDD Digital Power Supply, +3V to +5.25V 31 CLK Input Clock. Receives power from AVDD to reduce jitter. 32 DAV Data Valid Clock Output. This clock can be used to transfer the data to a memory or any other data-acquisition system. 33 OE 34 TEST0 Output Enable Input. OE = 0: D0-D13 and DOR are high impedance. OE = 1: All bits are active. Test Pin 0. Leave unconnected. 35 CM 36 RFPF Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages. Positive Reference Voltage. Force input. 37 RFPS Positive Reference Voltage. Sense input. 38 RFNF Negative Reference Voltage. Force input. 39 RFNS Negative Reference Voltage. Sense input. 40 INP Positive Input Voltage 41, 42 N.C. Not Connected. No internal connection. 43 INN Negative Input Voltage 44 END_CAL Digital Output for End of Calibration. END_CAL = 0: Calibration in progress. END_CAL = 1: Normal conversion mode. _______________Detailed Description Converter Operation The MAX1205 is a 14-bit, monolithic, analog-to-digital converter (ADC) capable of conversion rates up to 1Msps. It uses a multistage, fully differential pipelined architecture with digital error correction and self-calibration to provide typically greater than 91dB spuriousfree dynamic range at a 1Msps sampling rate. Its signal-to-noise ratio, harmonic distortion, and intermodulation products are also consistent with 14-bit accuracy up to the Nyquist frequency. This makes the device suitable for applications such as imaging, scanners, data acquisition, and digital communications. Figure 1 shows the simplified, internal structure of the ADC. A switched-capacitor pipelined architecture is used to digitize the signal at a high throughput rate. The first four stages of the pipeline use a low-resolution quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to subtract the quantized analog signal from the input. The residue is then amplified with a fixed gain and passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm which corrects for mismatches between the capacitors in the switched capacitor MDAC. Note that the pipeline introduces latency of four sampling periods between the input being sampled and the output appearing at D13–D0. While the device can handle both single-ended and differential inputs (see Requirements for Reference and Analog Signal Inputs), the latter mode of operation will guarantee best THD and SFDR performance. The differential input provides the following advantages compared to a single-ended operation: • Twice as much signal input span • Common-mode noise immunity • Virtual elimination of the even-order harmonics • Less stringent requirements on the input signal processing amplifiers _______________________________________________________________________________________ 7 MAX1205 Pin Description (continued) MAX1205 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC RFP_ RFN_ CM STAGE1 INP INN AVDD STAGE2 STAGE3 AGND STAGE4 8X S/H ADC ADC MDAC 7 CLK DVDD DAV CLOCK GENERATOR CORRECTION AND CALIBRATION LOGIC END_CAL ST_CAL 17 DGND OE MAX1205 OUTPUT DRIVERS DRVDD DOR D13–D0 Figure 1. Internal Block Diagram Requirements for Reference and Analog Signal Inputs Fully differential switched-capacitor circuits (SC) are used for both the reference and analog inputs (Figure 2). This allows either single-ended or differential signals to be used in the reference and/or analog signal paths. The signal voltage on these pins (INP, INN, RFN_, RFP_) should never exceed the analog supply rail, AVDD, and should not fall below ground. Choice of Reference It is important to choose a low-noise reference, such as the MAX6341, which can provide both excellent load regulation and low temperature drift. The equivalent input circuit for the reference pins is shown in Figure 3. Note that the reference pins drive approximately 1kΩ of CM RFPF resistance on chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within one clock cycle. Accomplish this by choosing an appropriate driving circuit (Figure 4). The capacitors at the reference pins (RFPF, RFNF) provide the dynamic charge required during each clock cycle, while the op amps ensure accuracy of the reference signals. These capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors. The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically the positive reference pin (RFPF) would be driven to 4.096V, and the negative reference pin (RFNF) connected to analog ground. There are sense pins, RFPS and RFNS, which can be used with RFPS RFPF INP RFNF INN RFNF RFPF CM Figure 2. Simplified MDAC Architecture 8 RFNS Figure 3. Equivalent Input at the Reference Pins. The sense pins should not draw any DC current. _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC Common-Mode Voltage The switched capacitor input circuit at the analog input allows signals between AGND and the analog power supply. Since the common-mode voltage has a strong influence on the performance of the ADC, the best results are obtained by choosing VCM to be at half the difference between the reference voltages V RFP and VRFN. Achieve this by using a resistive divider between the two reference potentials. Figure 4 shows a typical driving circuit for good dynamic performance. Analog Signal Conditioning For single-ended inputs the negative analog input pin (INN) is connected to the common-mode voltage pin (CM), and the positive analog input pin (INP) is connected to the input. To take full advantage of the ADC’s superior AC performance up to the Nyquist frequency, drive the chip with differential signals. In communication systems, the signals may inherently be available in differential mode. Medical and/or other applications may only provide sin- gle-ended inputs. In this case, convert the singleended signals into differential ones by using the circuit recommended in Figure 5. Use low-noise, wideband amplifiers such as the MAX4108 to maintain the signal purity over the full-power bandwidth of the MAX1205 input. Lowpass or bandpass signals may be required to improve the signal-to-noise-and-distortion ratio of the incoming signal. For low-frequency signals (<100kHz), active filters may be used. For higher frequencies, passive filters are more convenient. Single-Ended to Differential Conversion Using Transformers An alternative single-ended to differential-ended conversion method is a balun transformer such as the CTX03-13675 from Coiltronics. An important benefit of these transformers is their ability to level-shift singleended signals referred to ground on the primary side to optimum common-mode voltages on the secondary side. At frequencies below 20kHz, the transformer core begins to saturate, causing odd-order harmonics. Clock Source Requirements Pipelined ADCs typically need a 50% duty cycle clock. To avoid this constraint, the MAX1205 provides a V+ RFP = 4.096V 5k CHIP BOUNDARY RFPF IN MAX410 INP MAX4108 RFPS 5k CM V- RFN = 0V RFNF MAX410 V+ RFNS INN MAX4108 CM MAX410 VCM Figure 4. Drive Circuit for the Reference Pins and the CommonMode Pin Figure 5. A simple circuit generates differential signals from a single-ended input referred to analog ground. The commonmode voltage at INP and INN is the same as CM. _______________________________________________________________________________________ 9 MAX1205 external amplifiers to compensate for any resistive drop on these lines, internal or external to the chip. Ensure a correct reference voltage by using proper Kelvin connections at the sense pins. MAX1205 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC divide-by-two circuit, which relaxes this requirement. The clock generator should be chosen commensurate with the frequency range, amplitude, and slew rate of the signal source. If the slew rate of the input signal is small, the jitter requirement on the clock is relaxed. However, if the slew rate is high, the clock jitter needs to be kept at a minimum. For a full-scale amplitude input sine wave, the maximum possible signal-to-noise ratio (SNR) due completely to clock jitter is given by: SNRMAX = 1 2πfINσ JITTER For example, if fIN is 0.5MHz and σJITTER is 20ps RMS, then the SNR limit due to jitter is about 84dB. Generating such a clock source requires a low-noise comparator and a low-phase-noise signal generator. The clock circuit shown in Figure 6 is a possible solution. Calibration Procedure Since the MAX1205 is based on a pipelined architecture, low-resolution quantizers (“coarse ADCs”) are used to approximate the input signal. MDACs of the same resolution are then used to reconstruct the input signal, which is subtracted from the input and the residue amplified by the SC gain stage. This residue is then passed on to the next stage. The accuracy of the MAX1205 is limited by the precision of the MDAC, which is strongly dependent on the matching of the capacitors used. The mismatch between the capacitors is determined and stored in an on-chip memory, which is later used during the conversion of the input signal. During the calibration procedure, the clock must be running continuously. ST_CAL (start of calibration) is initiated by a positive pulse with a minimum width of four clock cycles, but no longer than about 17,400 clock cycles (Figure 8). The ST_CAL input may be asynchronous with the clock, since it is retimed internally. With ST_CAL activated, END_CAL goes low one or two clock cycles later and remains low until the calibration is complete. During this period, the reference voltages must be stable to less than 0.01%; otherwise the calibration will be invalid. During calibration, the analog inputs INP and INN are not used; however, better performance is achieved if these inputs are static. Once END_CAL goes high (indicating that the calibration procedure is complete), the ADC is ready for conversion. Once calibrated, the MAX1205 is insensitive to small changes (<5%) in power-supply voltage or temperature. Following calibration, if the temperature changes more than ±20°C, the device should be recalibrated to maintain optimum performance. N N+1 AIN N+5 N+2 N+4 N+3 tCH tCL CLK SAMPLE CLOCK tS DAV tOD D0–D13 N-3 N-2 N-1 N N+1 Figure 7. Main Timing Diagram CLK V+ ST_CAL min 4 tCLK 0.1µF 0.1µF END_CAL ~17,400 CLK Cycles CLK_IN 1k 5k CLK Figure 8. Timing for Start and End of Calibration MAX961 V+ OE 0.1µF 1k tAC D0–D13 DOR Figure 6. Clock Generation Circuit Using a Low-Noise Comparator 10 Z tREL Z Figure 9. Timing for Bus Access and Bus Relinquish— Controlled by Output Enable (OE) ______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC Applications Information Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR(MAX) = (6.02N + 1.76)dB In reality, there are other noise sources besides quantization noise including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first nine harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to all other ADC output signals: SINAD (dB) = 20log [(SignalRMS / (Noise + Distortion)RMS] Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range for the ADC, Table 1. Two’s Complement Conversion the effective number of bits can be calculated as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first nine harmonics of the input signal to the fundamental itself. This is expressed as: V2 2 + V3 2 + V4 2 + ⋅ ⋅ ⋅ + V9 2 THD = 20log V1 where V1 is the fundamental amplitude, and V2 through V9 are the amplitudes of the 2nd through 9th order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly influence the performance of the MAX1205. At 14-bit resolution, unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections; this adversely affects the SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX1205. Therefore, grounding and power-supply decoupling guidelines should be closely followed. SCALE OFFSET BINARY TWO’S COMPLEMENT ONE’S COMPLEMENT +FSR - 1LSB 1111....1111 0111....1111 0111....1111 +3/4FSR 1110....0000 0110....0000 0110....0000 +1/2FSR 1100....0000 0100....0000 0100....0000 +1/4FSR 1010....0000 0010....0000 0010....0000 +0 1000....0000 0000....0000 0000....0000 -0 — — 1111....1111 -1/4FSR 0110....0000 1110....0000 1101....1111 -1/2FSR 0100....0000 1100....0000 1011....1111 -3/4FSR 0010....0000 1010....0000 1001....1111 -FSR + 1LSB 0000....0001 1000....0001 1000....0000 -FSR 0000....0000 1000....0000 — ______________________________________________________________________________________ 11 MAX1205 Two’s Complement Output The MAX1205 outputs data in two’s complement format. Table 1 shows how to convert the various fullscale inputs into their two’s complement output codes. First, a multilayer printed circuit board (PCB) with separate ground and power-supply planes is recommended. Run high-speed signal traces directly above the ground plane. Since the MAX1205 has separate analog and digital ground buses (AGND and DGND respectively), the PCB should also have separate analog and digital ground sections connected at only one point (star ground). Digital signals should run above the digital ground plane and analog signals should run above the analog ground plane. Digital signals should be kept far away from the sensitive analog inputs, reference inputs senses, common-mode input, and clock input. The MAX1205 has three power-supply inputs: analog VDD (AVDD), digital VDD (DVDD), and drive VDD (DRVDD). Each AVDD input should be decoupled with parallel ceramic-chip capacitors of values 0.1µF and 0.001µF, with these capacitors as close to the pin as possible and with the shortest possible connection to the ground plane. The DVDD pins should also have separate 0.1µF capacitors adjacent to their respective pins, as should the DRV DD pin. Minimize the digital load capacitance. However, if the total load capacitance on each digital output exceeds 20pF, the DRVDD decoupling capacitor should be increased or, preferably, digital buffers should be added. The power-supply voltages should be decoupled with large tantalum or electrolytic capacitors at the point they enter the PCB. Ferrite beads with additional decoupling capacitors forming a pi-network may improve performance. The analog power-supply input (AV DD ) for the MAX1205 is typically +5V while the digital supplies can vary from +5V to +3V. Usually, DVDD and DRVDD pins are connected to the same power supply. Note that the DVDD supply voltage must be greater than or equal to the DRVDD voltage. For example, a digital +3.3V supply could be connected to DRVDD while a cleaner +5V supply is connected to DV DD , resulting in slightly improved performance. Alternatively, the +3.3V supply could be connected to both DRV DD and DV DD . However, the +3.3V supply should not be connected to DVDD while the +5V supply is connected to DRVDD (Table 2). Table 2. Power-Supply Voltage Combinations AVDD (V) DVDD (V) DRVDD (V) ALLOWED/NOT ALLOWED +5 +5 +5 Allowed +5 +5 +3.3 Allowed +5 +3.3 +3.3 Allowed +5 +3.3 +5 Not Allowed ___________________Chip Information TRANSISTOR COUNT: 56,577 SUBSTRATE CONNECTED TO: AGND Package Information MQFP44.EPS MAX1205 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.