DS1921G Thermochron iButton www.maxim-ic.com SPECIAL FEATURES § § § § § § § § § § Digital thermometer measures temperature in 0.5°C increments Accuracy ±1°C from -30°C to +70°C. See EC table for accuracy specification Built-in real-time clock (RTC) and timer has accuracy of ±2 minutes per month per month from 0°C to 45°C Automatically wakes up and measures temperature at user-programmable intervals from 1 to 255 minutes Logs up to 2048 consecutive temperature measurements in protected nonvolatile (NV) random access memory Records a long-term temperature histogram with 2.0°C resolution Programmable temperature-high and temperature-low alarm trip points Records up to 24 time stamps and durations when temperature leaves the range specified by the trip points 512 bytes of general-purpose read/write NV random access memory Communicates to host with a single digital signal at 15.4kbits or 125kbits per second using 1-Wire® protocol § § § § § F5 MICROCAN 5.89 0.51 â 16.25 89 § § § § Digital identification and information by momentary contact Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike Multidrop controller for 1-Wire net Chip-based data carrier compactly stores information Data can be accessed while affixed to object â 21 000000FBC52B 17.35 â 1-Wire Thermochron® IO COMMON iButton FEATURES § Button shape is self-aligning with cup-shaped probes Durable stainless-steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim Presence detector acknowledges when reader first applies voltage Meets UL#913 (4th Edit.). Intrinsically Safe Apparatus: approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations (application pending) GND All dimensions are shown in millimeters. ORDERING INFORMATION DS1921G-F5 -40°C to +85°C F5 iButton EXAMPLES OF ACCESSORIES DS9096P DS9101 DS9093RA DS9093A DS9092 Self-Stick Adhesive Pad Multi-Purpose Clip Mounting Lock Ring Snap-In Fob iButton Probe 1-Wire, Microcan, and iButton are registered trademarks of Dallas Semiconductor 1 of 44 121003 DS1921G iButton DESCRIPTION The DS1921G Thermochron iButton is a rugged, self-sufficient system that measures temperature and records the result in a protected memory section. The recording is done at a user-defined rate, both as a direct storage of temperature values as well as in the form of a histogram. Up to 2048 temperature values taken at equidistant intervals ranging from 1 to 255 minutes can be stored. The histogram provides 63 data bins with a resolution of 2.0°C. If the temperature leaves a user-programmable range, the DS1921G will also record when this happened, for how long the temperature stayed outside the permitted range, and if the temperature was too high or too low. An additional 512 bytes of read/write NV memory allow storing information pertaining to the object to which the DS1921G is associated. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. Every DS1921G is factory-lasered with a guaranteed unique electrically readable 64-bit registration number that allows for absolute traceability. The durable stainless steel package is highly resistant to environmental hazards such as dirt, moisture, and shock. Accessories permit the DS1921G to be mounted on almost any object, including containers, pallets, and bags. APPLICATION The DS1921G Thermochron iButton is an ideal device to monitor the temperature of any object it is attached to or shipped with, such as perishable goods or containers of temperature sensitive chemicals. The read/write NV memory can store an electronic copy of shipping information, date of manufacture and other important data written as clear as well as encrypted files. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS1921G. The device has seven main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bit general-purpose SRAM, 4) 256-bit register page of timekeeping, control, and counter registers, 5) 96 bytes of alarm time stamp and duration logging memory, 6) 126 bytes of histogram memory, and 7) 2048 bytes of data-logging memory. Except for the ROM and the scratchpad, all other memory is arranged in a single linear address space. All memory reserved for logging purposes, counter registers and several other registers are read-only for the user. The timekeeping and control registers are write-protected while the device is programmed for a mission. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode, where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 13. After a ROM function command is successfully executed, the memory functions become accessible and the master may provide any one of the seven available commands. The protocol for these memory function commands is described in Figure 10. All data is read and written least significant bit first. 2 of 44 DS1921G Figure 1. DS1921G BLOCK DIAGRAM 1-Wire Port ROM Function Control IO 64-Bit Lasered ROM Memory Function Control Parasite Powered Circuitry 256-Bit Scratchpad General-Purpose SRAM Internal Timekeeping & Control Reg. & Counters 32.768kHz Oscillator Register Page Alarm Time Stamp and Duration Logging Memory Temperature Core Control Logic Histogram Memory Datalog Memory 3V Lithium PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power whenever the IO input is high. IO will provide sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved, and 2) if the lithium is exhausted for any reason, the ROM may still be read normally. 64-BIT LASERED ROM Each DS1921G contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27 and in the Book of DS19xx iButton Standards. The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the eighth bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC returns the shift register to all 0s. 3 of 44 DS1921G Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL 1-Wire net BUS Master Other Devices DS1921 Command Level: Available Commands: 1-Wire ROM Function Commands DS1921-specific Memory/Control Function Commands Cmd. Data Field Codes: Affected: Read ROM Match ROM Search ROM Skip ROM Overdrive Skip Overdrive Match Conditional Search ROM 33h 55h F0h CCh 3Ch 69h ECh 64-bit Reg. # 64-bit Reg. # 64-bit Reg. # N/A OD-Flag 64-bit Reg. #, OD-Flag 64-bit Reg. #, Cond. Search settings, device status Write Scratchpad Read Scratchpad Copy Scratchpad Read Memory Read Memory w/CRC Clear Memory 0Fh AAh 55h F0h A5h 3Ch Convert Temperature 44h 256-bit scratchpad, flags 256-bit scratchpad 4096-bit SRAM, registers, flags All memory All memory Mission Time Stamp, Mission Samples Counter, Start Delay, Sample Rate, Alarm Time Stamps and Durations, Histogram Memory Memory address 211h Figure 3. 64-BIT LASERED ROM MSB LSB 8-Bit CRC Code MSB LSB 8-Bit Family Code (21h) 48-Bit Serial Number MSB LSB 4 of 44 MSB LSB DS1921G Figure 4. 1-Wire CRC GENERATOR 8 5 4 Polynomial = X + X + X + 1 st nd 1 STAGE X 0 rd 2 STAGE X 1 th 3 STAGE X 2 th 4 STAGE X 3 th 5 STAGE X 4 th 6 STAGE X 5 th 7 STAGE X 6 8 STAGE X 7 X 8 INPUT DATA MEMORY The memory map of the DS1921G is shown in Figure 5. The 4096-bit general-purpose SRAM make up pages 0 through 15. The timekeeping, control, and counter registers fill page 16, called Register Page (see Figure 6). Pages 17 to 19 are assigned to storing the alarm time stamps and durations. The temperature histogram bins begin at page 64 and use up to four pages. The temperature logging memory covers pages 128 to 191. Memory pages 20 to 63, 68 to 127, and 192 to 255 are reserved for future extensions. The scratchpad is an additional page that acts as a buffer when writing to the SRAM memory or the register page. The memory pages 17 and higher are read-only for the user. They are written to or erased solely under supervision of the on-chip control logic. Figure 5. DS1921G MEMORY MAP 32-Byte Intermediate Storage Scratchpad ADDRESS 0000h to 01FFh General-Purpose SRAM (16 Pages) Pages 0 to 15 0200h to 021Fh 32-Byte Register Page Page 16 0220h to 027Fh Alarm Time Stamps and Durations Pages 17 to 19 0280h to 07FFh (Reserved for Future Extensions) Pages 20 to 63 0800h to 087Fh Temperature Histogram Memory Pages 64 to 67 0880h to 0FFFh (Reserved for Future Extensions) Pages 68 to 127 1000h to 17FFh Datalog Memory (64 Pages) Pages 128 to 191 1800h to 1FFFh (Reserved for Future Extensions) Pages 192 to 255 5 of 44 DS1921G Figure 6. DS1921G REGISTER PAGE MAP ADDR 0200h 0201h 0202h b7 0 0 0 b6 b5 b4 10 Seconds 10 Minutes 12/24 20h. 10h. b3 0 0 CENT 020Ah 020Bh 020Ch 020Dh MD 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h EOSC MS MM MH TCB 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh b0 Single Hours AM/PM 0203h 0204h 0205h 0206h 0207h 0208h 0209h b2 b1 Single Seconds Single Minutes 0 0 0 0 Day of Week 0 10 Date Single Date 0 0 10m. Single Months 10 Years Single Years 10 Seconds Alarm Single Seconds Alarm 10 Minutes Alarm Single Minutes Alarm 10ha. 10h. 12/24 Single Hours Alarm A/P alm. 0 0 0 0 Day of Week Alarm Temperature Low Alarm Threshold Temperature High Alarm Threshold Number of Minutes Between Temperature Conversions EMCLR 0 RO TLS THS EM (no function, reads 00h) (no function, reads 00h) Temperature Read Out (Forced Conversion) Low Byte High Byte MEMCLR MIP SIP 0 TLF THF Minutes Hours Date Month Year Low Byte Center Byte High Byte Low Byte Center Byte High Byte TAS TAF Function Access* RealTime Clock Registers R/W; R/W** RealTime Clock Alarm Registers Temp. Alarms R/W; R/W** R/W; R/W** Sample Rate R/W; R** Control (N/A) (N/A) Temp. Start Delay Status R/W; R/W** Mission Time Stamp Mission Samples Counter Device Samples Counter R; R** R; R** R; R** R/W; R/W** R/W; R/W R; R R; R R; R *The first entry in column ACCESS is valid between missions. The second entry shows the applicable access mode while a mission is in progress. **While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only ones), however, will end the mission and overwrite selected writeable registers. TIMEKEEPING The RTC/alarm and calendar information is accessed by reading/writing the appropriate bytes in the register page, address 200h to 206h. Note that some bits are set to 0. These bits will always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD) format. 6 of 44 DS1921G RTC and RTC Alarm Register Bitmap ADDR 0200h 0201h 0202h b7 0 0 0 b6 b5 b4 10 Seconds 10 Minutes 12/24 20h. 10h. b3 b2 b1 Single Seconds Single Minutes Single Hours AM/PM 0203h 0204h 0205h 0206h 0207h 0208h 0209h 0 0 CENT 020Ah MD MS MM MH 0 0 0 0 10 Date 0 0 10m. 10 Years 10 Seconds Alarm 10 Minutes Alarm 10ha. 10h. 12/24 A/P alm. 0 0 0 b0 0 Day of Week Single Date Single Months Single Years Single Seconds Alarm Single Minutes Alarm Single Hours Alarm 0 Day of Week Alarm RTC/Calendar The RTC of the DS1921G can run in either 12-hour or 24-hour mode. Bit 6 of the Hours Register (address 202h) is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the 20hour bit (20 to 23 hours). To distinguish between the days of the week the DS1921G includes a counter with a range from 1 to 7. The assignment of counter value to the day of week is arbitrary. Typically, the number 1 is assigned to a Sunday (U.S. standard) or to a Monday (European standard). The calendar logic is designed to automatically compensate for leap years. For every year value that is either 00 or a multiple of 4 the device will add a 29th of February. This will work correctly up to (but not including) the year 2100. The DS1921G is Y2K-compliant. Bit 7 (CENT) of the Months Register at address 205h serves as a century flag. When the Year Register rolls over from 99 to 00 the century flag will toggle. It is recommended to write the century bit to a 1 when setting the RTC to a time/date between the years 2000 and 2099. RTC Alarms The DS1921G also contains a RTC alarm function. The alarm registers are located in registers 207h to 20Ah. The most significant bit of each of the alarm registers is a mask bit. When all of the mask bits are logic 0, an alarm will occur once per week when the values stored in timekeeping registers 200h to 203h match the values stored in the time of day alarm registers. Any alarm will set the Timer Alarm Flag (TAF) in the device's Status Register (address 214h). The bus master may set the Search Conditions in the Control Register (address 20Eh) to identify devices with timer alarms by means of the Conditional Search function (see ROM Function Commands). 7 of 44 DS1921G RTC Alarm Control ALARM REGISTER MASK BITS (Bit 7 of 207h to 20Ah) MS MM MH MD 1 1 1 1 Alarm once per second. 0 1 1 1 Alarm when seconds match (once per minute). 0 0 1 1 Alarm when minutes and seconds match (once every hour). 0 0 0 1 Alarm when hours, minutes and seconds match (once every day). 0 0 0 0 Alarm when day, hours, minutes, and seconds match (once every week). Temperature Conversion The DS1921G measures temperatures with a resolution of 0.5°C. Temperature values are represented in a single byte as an unsigned binary number, which translates into a theoretical range of 128°C. The range, however, has been limited to values from 0000 0000 (00h) through 1111 1010 (FAh). The codes 01h to F9h are considered valid temperature readings. If a temperature conversion yields a temperature that is out-of-range, it will be recorded as 00h (if too low) or FAh (if too high). Since out-of-range results are accumulated in histogram bins 0 and 62 (see section Temperature Logging and Histogram) the data in these bins is of limited value. For this reason the specified temperature range of the DS1921G is considered to begin at code 04h and end at code F7h, which corresponds to histogram bins 1 to 61. With T[7..0] representing the decimal equivalent of a temperature reading, the temperature value is calculated as J (°C) = T[7…0] / 2 - 40.0 This equation is valid for converting temperature readings stored in the datalog memory as well as for data read from the forced temperature conversion readout Register (address 211h). To specify the high or low temperature alarm thresholds, this equation needs to be resolved to T[7…0] = 2 * J (°C) + 80.0 A value of 23°C, for example, thus translates into 126 decimal or 7Eh. This corresponds to the binary patterns 0111 1110, which could be written to a Temperature Alarm Register (address 020Bh and 020Ch, respectively). Temperature Alarm Register Map ADDR 020Bh 020Ch b7 b6 b5 b4 b3 b2 Temperature Low Alarm Threshold Temperature High Alarm Threshold 8 of 44 b1 b0 DS1921G Sample Rate The content of the Sample Rate Register (address 020Dh) determines how many minutes the temperature conversions are apart from each other during a mission. The sample rate may be any value from 1 to 255, coded as an unsigned 8-bit binary number. If the memory has been cleared (Status Register bit MEMCLR = 1) and a mission is enabled (Status Register bit EM = 0), writing a non-zero value to the Sample Rate Register will start a mission. For a full description of the correct sequence of steps to start a temperaturelogging mission see sections Missioning or Missioning Example. Sample Rate Register Map ADDR 020Dh b7 b6 b5 b4 b3 Sample Rate b2 b1 b0 Control Register The DS1921G is set up for its operation by writing appropriate data to its special function registers that are located in the register page. Several functions that are controlled by a single bit only are combined into a single byte called Control Register (address 20Eh). This register can be read and written. If the device is programmed for a mission, writing to the Control Register will end the mission and change the register contents. Control Register Bitmap ADDR 020Eh b7 b6 EOSC EMCLR b5 0 b4 EM b3 RO b2 TLS b1 THS b0 TAS The functional assignments of the individual bits are explained in the table below. Bit 5 has no function. It always reads 0 and cannot be written to 1. Control Register Details BIT DESCRIPTION EOSC: Enable Oscillator BIT(S) b7 EMCLR: Memory Clear Enable b6 EM: Enable Mission b4 RO: Rollover Enable/Disable b3 DEFINITION This bit controls the crystal oscillator of the RTC. When set to logic 0, the oscillator will start operation. When written to logic 1, the oscillator will stop and the device is in a low-power data retention mode. This bit must be 0 for normal operation. The RTC must have advanced at least 1 second before a mission start will be accepted. This bit needs to be set to logic 1 to enable the Clear Memory function, which is invoked as a memory function command. The Time-Stamp, Histogram Memory as well as the Mission Time Stamp, Mission Samples Counter, Mission Start Delay and Sample Rate will be cleared only if the Clear Memory command is issued with the next access to the device. The EMCLR bit will return to 0 as the next memory function command is executed. This bit controls whether the DS1921G will begin a mission as soon as the sample rate is written. To enable the device for a mission, this bit must be 0. This bit controls whether the temperature logging memory is overwritten with new data or whether data logging is stopped once the memory is filled with data during a mission. Setting this bit to a 1 enables the rollover and data logging continues at the beginning overwriting previously collected data. Clearing this bit to 0 disables the rollover and no further temperature values will be stored in the temperature logging memory once it is filled with data. This will not stop the mission. The device will continue measuring temperatures and updating the histogram and alarm time stamps and durations. 9 of 44 BIT DESCRIPTION TLS: Temperature Low Alarm Search BIT(S) b2 THS: Temperature High Alarm Search b1 TAS: Timer Alarm Search b0 DS1921G DEFINITION If this bit is 1, the device will respond to a Conditional Search command if during a mission the temperature has reached or is lower than the Low Temperature Threshold stored at address 020Bh. If this bit is 1, the device will respond to a Conditional Search command if during a mission the temperature has reached or is higher than the High Temperature Threshold stored at address 020Ch. If this bit is 1, the device will respond to a Conditional Search command if during a mission a timer alarm has occurred. Since a timer alarm cannot be disabled, the TAF flag usually reads 1 during a mission. Therefore it may be advisable to set the TAS bit to a 0, in most cases. Mission Start Delay Counter The content of the Mission Start Delay Counter determines how many minutes the device will wait before starting the logging process. The mission start delay value is stored as unsigned 16-bit integer number at addresses 212h (low byte) and 213h (high byte). The maximum delay is 65535 minutes, equivalent to 45 days, 12 hours, and 15 minutes. For a typical mission, the Mission Start Delay is 0. If a mission is too long for a single DS1921G to store all temperature readings at the selected sample rate, one can use several devices, staggering the Mission Start Delay to record the full period. In this case, the RO bit in the control register (address 020Eh) must be set to 0 to prevent overwriting of the recorded temperature log after the datalog memory is full. See Mission Start and Logging Process description and flow chart for details. Status Register The Status Register holds device status information and alarm flags. The register is located at address 214h. Writing to this register will not necessarily end a mission. Status Register Bitmap ADDR 0214h b7 b6 TCB MEMCLR b5 MIP b4 SIP b3 0 b2 TLF b1 THF b0 TAF The functional assignments of the individual bits are explained in the table below. The bits MIP, TLF, THF and TAF can only be written to 0. All other bits are read-only. Bit 3 has no function. Status Register Details BIT DESCRIPTION TCB: Temperature Core Busy MEMCLR: Memory Cleared BIT(S) b7 b6 DEFINITION If this bit reads 0 the DS1921G is currently performing a temperature conversion, either self-initiated because of a mission being in progress or initiated by a command when a mission is not in progress. The TCB bit goes low just before a conversion starts and returns to high just after the result is latched into the readout register at address 0211h. If this bit reads 1, the memory pages 17 and higher (alarm time stamps/durations, temperature histogram, excluding datalog memory), as well as the Mission Time Stamp, Mission Samples Counter, Mission Start Delay and Sample Rate have been cleared to 0 from executing a Clear Memory function command. The MEMCLR bit will return to 0 as soon as writing a non-0 value to the Sample Rate Register starts a new mission, provided that the EM bit is also 0. The memory has to be cleared in order for a mission to start. 10 of 44 BIT DESCRIPTION MIP: Mission in Progress BIT(S) b5 SIP: Sample in Progress b4 TLF: Temperature Low Flag b2 THF: Temperature High Flag b1 TAF: Timer Alarm Flag b0 DS1921G DEFINITION If this bit reads 1 the DS1921G has been set up for a mission and this mission is still in progress. A mission is started if the EM bit of the Control Register (address 20Eh) is 0 and a non-zero value is written to the Sample Rate Register, address 20Dh. The MIP bit returns from logic 1 to logic 0 when a mission is ended. A mission will end with the first write attempt (Copy Scratchpad command) to any register in the address range of 200h to 213h. Alternatively, a mission can be ended by directly writing to the Status Register and setting the MIP bit to 0. The MIP bit cannot be set to 1 by writing to the status register. If this bit reads 1 the DS1921G is currently performing a temperature conversion as part of a mission in progress. The mission samples occur on the seconds rollover from 59 to 00. The SIP bit will change from 0 to 1 approximately 250ms before the actual temperature conversion begins allowing the circuitry of the chip to wake-up. A temperature conversion including a wake-up phase takes maximum 875ms. During this time read accesses to the memory pages 17 and higher are permissible but may reveal invalid data. Logic 1 in the Temperature Low Flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or lower than the value in the Temperature Low Threshold Register. The Temperature Low Flag can be cleared at any time by writing this bit to 0. This flag must be cleared before starting a new mission. Logic 1 in the Temperature High Flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or higher than the value in the Temperature High Threshold Register. The Temperature High Flag can be cleared at any time by writing this bit to 0. This flag must be cleared before starting a new mission. If this bit reads 1, a RTC alarm has occurred (see TIMEKEEPING section for details). The Timer Alarm Flag can be cleared at any time by writing this bit to logic 0. Since the timer alarm cannot be disabled, the TAF flag usually reads 1 during a mission. This flag should be cleared before starting a new mission. Mission Time Stamp The Mission Time Stamp indicates the time and date of the first temperature conversion of a mission. Subsequent temperature conversions will take place as many minutes apart from each other as specified by the value in the Sample Rate Register. Mission samples occur on minute boundaries. Mission Time Stamp Register Bitmap ADDR 0215h 0216h 0217h 0218h 0219h b7 0 0 0 0 b6 b5 10 Minutes b4 b3 b2 b1 Single Minutes 12/24 20h. AM/PM 10h. Single Hours 0 10 Date 0 0 10m. 10 Years Single Date Single Months Single Years b0 Mission Samples Counter The Mission Samples Counter indicates how many temperature measurements have taken place during the current mission in progress (if MIP = 1) or during the latest mission (if MIP = 0). The value is stored as an unsigned 24-bit integer number. This counter is reset through the Clear Memory command. 11 of 44 DS1921G Mission Samples Counter Register Map ADDR 021Ah 021Bh 021Ch b7 b6 b5 b4 b3 Low Byte Center Byte High Byte b2 b1 b0 Device Samples Counter The Device Samples Counter indicates how many temperature measurements have taken place since the device was assembled at the factory. The value is stored as an unsigned 24-bit integer number. The maximum number that can be represented in this format is 16777215, which is higher than the expected lifetime of the DS1921G iButton. This counter cannot be reset under software control. Device Samples Counter Register Map ADDR 021Dh 021Eh 021Fh b7 b6 b5 b4 b3 Low Byte Center Byte High Byte b2 b1 b0 Temperature Logging and Histogram Once setup for a mission, the DS1921G logs the temperature measurements simultaneously byte after byte in the datalog memory as well as in histogram form in the histogram memory. The datalog memory is able to store 2048 temperature values measured at equidistant time points. The first temperature value of a mission is written to address location 1000h of the datalog memory, the second value to address location 1001h and so on. Knowing the starting time point (Mission Time Stamp), the interval between temperature measurements, the Mission Samples Counter, and the rollover setting, one can reconstruct the time and date of each measurement stored in the datalog. There are two alternatives to the way the DS1921G will behave after the 2048 bytes of datalog memory is filled with data. With rollover disabled (RO = 0), the device will fill the datalog memory with the first 2048 mission samples. Additional mission samples are not logged in the datalog, but the histogram, and temperature alarm ram continue to update. With rollover enabled (RO = 1), the datalog will wrap around, and overwrite previous data starting at 1000h for the every 2049th mission sample. In this mode the device stores the last 2048 mission samples. For the temperature histogram, the DS1921G provides 63 bins that begin at memory address 0800h. Each bin consists of a 16-bit, non-rolling-over binary counter that is incremented each time a temperature value acquired during a mission falls into the range of the bin. The least significant byte of each bin is stored at the lower address. Bin 0 begins at memory address 0800h, bin 1 at 0802h, and so on up to 087Ch for bin 62, as shown in Figure 7. The number of the bin to be updated after a temperature conversion is determined by cutting off the two least significant bits of the binary temperature value. Out of range values are range locked and counted as 00h or FAh. 12 of 44 DS1921G Figure 7. Histogram Bin and Temperature Cross-Reference TEMPERATURE READING TEMP. EQUIV. IN °C HISTOGRAM BIN NUMBER HISTOGRAM BIN ADDRESS 00h -40.0 or lower 0 800h to 801h 01h -39.5 0 800h to 801h 02h -39.0 0 800h to 801h 03h -38.5 0 800h to 801h 04h -38.0 1 802h to 803h 05h -37.5 1 802h to 803h 06h -37.0 1 802h to 803h 07h -36.5 1 802h to 803h 08h -36.0 2 804h to 805h F3h +81.5 60 878h to 879h F4h +82.0 61 87Ah to 87Bh F5h +82.5 61 87Ah to 87Bh F6h +83.0 61 87Ah to 87Bh F7h +83.5 61 87Ah to 87Bh F8h +84.0 62 87Ch to 87Dh F9h +84.5 62 87Ch to 87Dh FAh +85.0 or higher 62 87Ch to 87Dh Since each data bin is 2 bytes it can increment up to 65535 times. Additional measurements for a bin that has already reached its maximum value will not be counted; the bin counter will remain at its maximum value. With the fastest sample rate of one sample every minute, a 2-byte bin is sufficient for up to 45 days if all temperature readings fall into the same bin. Temperature Alarm Logging For some applications it may be essential to not only record temperature over time and the temperature histogram, but also record when exactly the temperature has exceeded a predefined tolerance band and for how long the temperature stayed outside the desirable range. The DS1921G can log high and low durations. The tolerance band is specified by means of the Temperature Alarm Threshold Registers, addresses 20Bh and 20Ch in the register page. One can set a high and a low temperature threshold. See section Temperature Conversion for the data format the temperature has to be written in. As long as the temperature values stay within the tolerance band (i.e., are higher than the low threshold and lower than the high threshold), the DS1921G will not record any temperature alarm. If the temperature during a mission reaches or exceeds either threshold, the DS1921G will generate an alarm and set either the Temperature High Flag (THF) or the Temperature Low Flag (TLF) in the Status Register (address 214h). This way, if the search conditions (address 20Eh) are set accordingly, the master can quickly identify devices with temperature alarms by means of the Conditional Search function (see ROM Function Commands). The device also generates a time stamp of when the alarm occurred and begins recording the duration of the alarming temperature. Time stamps and durations where the temperature leaves the tolerance band are stored in the address range 0220h to 027Fh, as shown in Figure 8. This allocation allows recording 24 individual alarm events and periods (12 periods for too hot and 12 for too cold). The date and time of each of these periods can be determined from the Mission Time Stamp and the time distance between each temperature reading. 13 of 44 DS1921G Figure 8. Alarm Time Stamps and Durations Address Map ADDRESS DESCRIPTION ALARM EVENT 0220h Mission Samples Counter Low Byte 0221h Mission Samples Counter Center Byte 0222h Mission Samples Counter High Byte 0223h Alarm Duration Counter 0224h to 0227h Alarm Time Stamp and Duration Low Alarm 2 0228h to 024Fh Alarm Time Stamp and Durations Low Alarms 3 to 12 0250h Mission Samples Counter Low Byte 0251h Mission Samples Counter Center Byte 0252h Mission Samples Counter High Byte 0253h Alarm Duration Counter 0254h to 0257h Alarm Time Stamp and Duration High Alarm 2 0258h to 027Fh Alarm Time Stamp and Durations High Alarms 3 to 12 Low Alarm 1 High Alarm 1 The alarm time stamp is a copy of the Mission Samples Counter when the alarm first occurred. The least significant byte is stored at the lower address. One address higher than the time stamp the DS1921G maintains a 1-byte duration counter that stores the number of samples the temperature was found to be beyond the threshold. If this counter has reached its limit after 255 consecutive temperature readings and the temperature has not yet returned to within the tolerance band, the device will issue another time stamp at the next higher alarm location and open another counter to record the duration. If the temperature returns to normal before the counter has reached its limit, the duration counter of the particular time stamp will not increment any further. Should the temperature again cross this threshold, it will be recorded at the next available alarm location. This algorithm is implemented for the low as well as for the high temperature threshold. MISSIONING The typical task of the DS1921G is recording the temperature of a temperature-sensitive object. Before the device can perform this function, it needs to be configured. This procedure is called missioning. First of all, DS1921G needs to have its RTC set to valid time and date. This reference time may be UTC (also called GMT, Greenwich Mean Time) or any other time standard that was chosen for the application. The clock must be running (EOSC = 0) for at least one second. Setting a RTC alarm is optional. The memory assigned to storing alarm time stamps and durations, temperature histogram, as well as the Mission Time Stamp, Mission Samples Counter, Mission Start Delay and Sample Rate must be cleared using the Memory Clear command. In case there were temperature alarms in the previous mission, the TLF and THF flags need to be cleared manually. To enable the device for a mission, the EM flag must be set to 0. These are general settings that have to be made regardless of the type of object to be monitored and the duration of the mission. Next, the low temperature and high temperature thresholds to specify the temperature tolerance band must be defined. How to convert a temperature value into the binary code to be written to the threshold registers is described under Temperature Conversion earlier in this document. 14 of 44 DS1921G The state of the Search Condition bits in the Control Register does not affect the mission. If multiple devices are connected to form a 1-Wire net, the setting of the search condition will enable devices to participate in the conditional search if certain events such as timer or temperature alarm have occurred. Details on the search conditions are found in the section ROM Function Commands later in this document and in the Control Register description. The setting of the RO bit (rollover enable) and sample rate depends on the duration of the mission and the monitoring requirements. If the most recent temperature history is important, the rollover should be enabled (RO = 1). Otherwise, one should estimate the duration of the mission in minutes and divide the number by 2048 to calculate the value of the sample rate (number of minutes between temperature conversions). If the estimated duration of a mission is 10 days (= 14400 minutes) for example, then the 2048-byte capacity of the datalog memory would be sufficient to store a new value every 7 minutes. If the datalog memory of the DS1921G is not large enough to store all temperature readings, one can use several devices and set the Mission Start Delay to values that make the second device start recording as soon as the memory of the first device is full, and so on. The RO-bit needs to be set to 0 to disable rollover that would otherwise overwrite the recorded temperature log. After the RO bit and the Mission Start Delay are set, the Sample Rate Register is the last element of data that is written. The sample rate may be any value from 1 to 255, coded as an unsigned 8-bit binary number. As soon as the sample rate is written, the DS1921G will set the MIP flag and clear the MEMCLR flag. After as many minutes as specified by the Mission Start Delay are over, the device will wait for the next minute boundary, then wake up, copy the current time and date to the Mission Time Stamp Register, and make the first temperature conversion of the mission. This increments both the Mission Samples Counter and Device Samples Counter. All subsequent temperature measurements are taken on minute boundaries specified by the value in the Sample Rate Register. One may read the memory of the DS1921G to watch the mission as it progresses. Care should be taken to avoid memory access conflicts. See section Memory Access Conflicts for details. MEMORY/CONTROL FUNCTION COMMANDS The Memory/Control Function Flow Chart (Figure 10) describes the protocols necessary for accessing the memory and the special function registers of the DS1921G. An example on how to use these and other functions to set up the DS1921G for a mission is included at the end of this document, preceding the Electrical Characteristics section. The communication between master and DS1921G takes place either at regular speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive Mode, the DS1921G assumes regular speed. Internal memory access during a mission has priority over external access through the 1-Wire interface. This can affect the Read Memory commands described below. See section Memory Access Conflicts for details. ADDRESS REGISTERS AND TRANSFER STATUS Because of the serial data transfer, the DS1921G employs three address registers, called TA1, TA2, and E/S (Figure 9). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte counter and transfer status register. It is used to verify data integrity with Write commands. Therefore, the master only has read access to this register. The lower 5 bits of the E/S Register indicate the address of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S Register, called PF or “partial byte flag,” is set if the number of data bits sent by the master is not an integer multiple of 8. Bit 6 is always a 0. Note that the lowest 5 bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target address for a Write command is 13Ch, for example, then the scratchpad will store 15 of 44 DS1921G incoming data beginning at the byte offset 1Ch and will be full after only 4 bytes. The corresponding ending offset in this example is 1Fh. For best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, (i.e., the byte offset will be 0). Thus, the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1Fh. However, it is possible to write 1 or several contiguous bytes somewhere within a page. The ending offset together with the Partial and Overflow Flag is mainly a means to support the master checking the data integrity after a Write command. The highest valued bit of the E/S Register, called AA or Authorization Accepted, indicates that a valid copy command for the scratchpad has been received and executed. Writing data to the scratchpad clears this flag. Figure 9. ADDRESS REGISTERS Bit # 7 6 5 4 3 2 1 0 Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0 Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8 Ending Address with Data Status (E/S) (Read Only) AA 0 PF E4 E3 E2 E1 E0 WRITING WITH VERIFICATION To write data to the DS1921G, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad and to verify data integrity. As preamble to the scratchpad data, the DS1921G sends the requested target address TA1 and TA2 and the contents of the E/S Register. If the PF flag is set, data did not arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the device. If everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. Now the master can continue verifying every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. This command must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the master has read them verifying the scratchpad. As soon as the DS1921G has received these bytes, it will copy the data to the requested location beginning at the target address. Write Scratchpad Command [0Fh] After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4:E0) will be the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete, its content will be ignored and the partial byte flag (PF) will be set. When executing the Write Scratchpad command, the CRC generator inside the DS1921G (see Figure 16) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC 16 of 44 DS1921G generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read time slots and will receive an inverted CRC16 generated by the DS1921G. The range 200h to 213h of the register page is protected during a mission. See Figure 6, Register Page Map, for the access type of the individual registers between and during missions. Read Scratchpad Command [AAh] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:T0), as shown in Figure 9. Regardless of the actual ending offset, the master may read data until the end of the scratchpad after which it will receive an inverted CRC16 of the command code, Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. After the CRC is read, the bus master will read logical 1s from the DS1921G until a reset pulse is issued. Copy Scratchpad [55h] This command is used to copy data from the scratchpad to the writable memory sections. Applying Copy Scratchpad to the Sample Rate Register can start a mission provided that several preconditions are met. See Mission Start and Logging Process description and the flow chart in Figure 11 for details. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A pattern of alternating 1s and 0s will be transmitted after the data has been copied until the master issues a reset pulse. While the copy is in progress any attempt to reset the part will be ignored. Copy typically takes 2µs per byte. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. The AA flag will remain at logic 1 until it is cleared by the next Write Scratchpad command. Note that Copy Scratchpad when applied to the address range 200h to 213h during a mission will end the mission. Read Memory [F0h] The Read Memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the 2 bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 0s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS1921G provides a means to accomplish error-free writing to the memory section. To safeguard data in the 1-Wire environment when reading and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to verify whether if the received data is correct. (See Application Note 114 for the recommended file structure.) 17 of 44 DS1921G Figure 10-1. MEMORY/CONTROL FUNCTION FLOW CHART From ROM Functions Flow Chart (Figure 13) Master TX Memory or Control Fkt. Command 0FH Write Scratchpad Y Y DS1921 sets EMCLR = 0 Master TX TA1 (T7:T0), TA2 (T15:T8) Master RX TA1 (T7:T0), TA2 (T15:T8) DS1921 sets Scratchpad Offset = (T4:T0) and Clears (PF, AA) Master RX Ending Offset with Data Status (E/S) DS1921 sets Scratchpad Offset = (T4:T0) DS1921 sets (E4:E0) = Scratchpad Offset Master TX Reset? DS1921 Increments Scratchpad Offset Master RX Data Byte from Scratchpad Offset Y Master TX Reset? DS1921 Increments Scratchpad Offset N Scratchpad Offset = 11111b? Partial Byte Written? Y Y N DS1921 sets EMCLR = 0 Master TX Data Byte to Scratchpad Offset N To Figure 10 nd 2 Part AAH Read Scratchpad N Master TX Reset? N Y N Y N Scratchpad Offset = 11111b? Y Master RX CRC16 of Command, Address Data, E/S Byte, and Data Starting at the Target Address PF = 1 N Master RX CRC16 of Command, Address, Data Y Y Master TX Reset? N Master TX Reset? Master RX "1"s N Master RX "1"s To ROM Functions Flow Chart (Figure 13) 18 of 44 From Figure 10 nd 2 Part DS1921G Figure 10-2. MEMORY/CONTROL FUNCTION FLOW CHART From Figure 10 st 1 Part 55H Copy Scratchpad To Figure 10 rd 3 Part F0H Read Memory N N Y Y DS1921 sets EMCLR = 0 DS1921 sets EMCLR = 0 Master TX TA1 (T7:T0), TA2 (T15:T8) Master TX TA1 (T7:T0), TA2 (T15:T8) Master TX E/S Byte DS1921 sets Memory Address = (T15:T0) Authorization Code Match? Master RX Data Byte from Memory Address N DS1921 Increments Address Counter Y AA = 1 DS1921 Copies Scratchpad Data to Memory Y Master TX Reset? N N N Master RX "1"s Master RX "1"s Copying Finished End of Memory? Y Master TX Reset? Y DS1921 TX "0" N Master RX "0"s Y Y Master TX Reset? N DS1921 TX "1" N Master TX Reset? Y To Figure 10 st 1 Part From Figure 10 rd 3 Part 19 of 44 DS1921G Figure 10-3. MEMORY/CONTROL FUNCTION FLOW CHART From Figure 10 nd 2 Part A5H Read Mem. w/CRC To Figure 10 th 4 Part N Y DS1921 sets EMCLR = 0 Master TX TA1 (T7:T0), TA2 (T15:T8) Decision made by DS1921 DS1921 sets Memory Address = (T15:T0) Y Decision made by Master End of Memory? N Master RX 00 Byte Master RX Data Byte from Memory Address Y DS1921 Increments Address Counter Master TX Reset? N N End of Page? Y Master RX CRC16 of Command, Address, Data st (1 Pass); CRC16 of Data (Subsequent Passes) Y CRC OK? N Master TX Reset To Figure 10 nd 2 Part From Figure 10 th 4 Part 20 of 44 DS1921G Figure 10-4. MEMORY/CONTROL FUNCTION FLOW CHART From Figure 10 rd 3 Part 3CH Clear Memory 44H Convert Temp. N Y N Y DS1921 sets EMCLR = 0 N EMCLR = 1? Y DS1921 clears Mission Time Stamp, Mission Samples Counter, Mission Start Delay, Sample Rate Register Y Mission in Progress? N DS1921 clears Alarm Time Stamps and Durations DS1921 clears Histogram Memory DS1921 Starts Temperature Conversion Process DS1921 sets MEMCLR = 1 Master TX Reset? DS1921 sets TCB\ = 0 DS1921 Performs a Temp. Conversion DS1921 copies Result to Address 0211h DS1921 sets TCB\ = 1 DS1921 sets EMCLR = 0 N Temperature Conversion Process N End of Process Master TX Reset? Y Y N Master TX Reset? Y To Figure 10 rd 3 Part 21 of 44 DS1921G Read Memory with CRC [A5h] The Read Memory with CRC command is used to read memory data that cannot be packetized, such as the register page and the data recorded by the device during a mission. The command works essentially the same way as the simple Read Memory, except for the 16-bit CRC that the DS1921G generates and transmits following the last data byte of a memory page. After having sent the command code of the Read Memory with CRC command, the bus master sends a 2byte address (TA1 = T7:T0, TA2 = T15:T8) that indicates a starting byte location. With the subsequent read data time slots the master receives data from the DS1921G starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 16 additional read data time slots and receive an inverted 16-bit CRC. With subsequent read data time slots the master will receive data starting at the beginning of the next page followed again by the inverted CRC for that page. This sequence will continue until the bus master resets the device. With the initial pass through the Read Memory with CRC flow, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator followed by the 2 address bytes and the contents of the data memory. Subsequent passes through the Read Memory with CRC flow will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page. After the 16-bit CRC of the last page is read, the bus master will receive logical 0s from the DS1921G and inverted CRC16s at page boundaries until a reset pulse is issued. The Read Memory with CRC command sequence can be ended at any point by issuing a reset pulse. Clear Memory [3Ch] The Clear Memory command is used to clear the Sample Rate, Mission Start Delay, Mission Time Stamp, and Mission Samples Counter in the register page and the Temperature Alarm Memory and the Temperature Histogram Memory. These memory areas must be cleared for the device to be set up for another mission. The Clear Memory command does not clear the datalog memory or the temperature and timer alarm flags in the Status Register. The RTC oscillator must be on and have counted at least 1 second, before issuing the command. For the Clear Memory command to function the EMCLR bit in Control Register must be set to 1, and the Clear Memory command must be issued with the very next access to the device’s memory functions. Issuing any other memory function command will reset the EMCLR bit. The Clear Memory process takes 500µs. When the command is completed the MEMCLR bit in the Status Register will read 1 and the EMCLR bit will be 0. Convert Temperature [44h] If a mission is not in progress (MIP = 0) the Convert Temperature command can be issued to measure the current temperature of the device. The result of the temperature conversion will be found at memory address 211h in the register page. This command takes maximum 90ms to complete. During this time the device remains fully accessible for memory/control and ROM function commands. 22 of 44 DS1921G Mission Start and Logging Process The DS1921G does not use a special command to start a mission. Instead, a mission is started by writing a non-zero value to the Sample Rate Register using the Copy Scratchpad command. As shown in Figure 11, a new mission can only be started if the previous mission has been stopped (MIP = 0), the memory is cleared (MEMCLR = 1) and the mission is enabled (EM = 0). If the new sample rate is different from zero, the value will be copied to the sample rate register. At the same time the MIP bit will be set and the MEMCLR bit will be cleared to indicate that the device is on a mission. Next the Mission Start Delay counter will start decrementing every minute until it is down to 0. Now the DS1921G will wait until the next minute boundary and start the logging process, which as its first action copies the applicable RTC registers to the Mission Time Stamp. Figure 11. MISSION START AND LOGGING PROCESS The Mission Start Process is invoked when the Copy Scratchpad function is used to set a new sample rate by writing to the Sample Rate Register at address 020Dh. One minute after the start delay countdown is over, the Logging Process begins and the Mission Start Process ends. Logging Process Mission Start Process Y MIP = 1? N EM = 0? DS1921 Copies RTC to Mission Time Stamp DS1921 Sets MIP = 0 N DS1921 sets Datalog Address = 1000h N DS1921 Measures Temperature Y DS1921 Updates Histogram, Device Samples Counter, Mission Samples Counter and Alarm, if applicable Y MEMCLR = 1 Y New Sample Rate = 0? N N DS1921 Copies new Sample Rate from Scratchpad to Sample Rate Register Y DS1921 sets MIP = 1; MEMCLR = 0 Start Delay Counter = 0? N N N MIP = 1? Y DS1921 Waits Until Next Minute Boundary Datalog Address = 1800h? DS1921 Stores Temp. at Datalog Address Y DS1921 Increments Datalog Address DS1921 Waits Until Next Minute Boundary DS1921 Waits One Sample Period DS1921 Logging Process Y RO = 1? Y DS1921 Stores Temp. at Datalog Address DS1921 Increments lower 11 bits of Datalog Address MIP = 1? N End of Process DS1921 Decrements Start Delay Counter End of Process 23 of 44 DS1921G Stop Mission The DS1921G does not have a special command to stop a mission. A mission can be stopped at any time by writing to any address in the range of 0200h to 0213h or by writing the MIP bit of the Status Register at address 0214h to 0. Either approach involves the use of the Copy Scratchpad command. There is no need for the Mission Start Delay to expire before a mission can be stopped (see Figure 11). MEMORY ACCESS CONFLICTS While a mission is in progress, periodically a temperature sample is taken and stored in the datalog, histogram, and potentially alarm memory. This "internal activity" has priority over a Read Memory or Read Memory with CRC access to these pages. If a conflict occurs, the data read may be invalid, even if the CRC value matches the data. To ensure that the data read is valid, it is recommended to first read the SIP bit of the Status Register. If the SIP bit is set, delay reading the datalog, histogram, and alarm memory until SIP is 0. The interference is more likely to be seen with a high sample rate (1 sample every minute). Since all mission samples occur on the seconds rollover (59 to 00), memory conflicts can be avoided by first reading the RTC seconds counter. For example, if it takes two seconds to read the datalog, then avoid starting the memory read if the seconds counter is 58, 59 or 00. Alternatively, one can read the affected memory section twice and accept the data only if both readings match. In any case, when writing driver software, it is important to know about the possibility of interference and to take measures to work around it. 1-WIRE BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS1921G is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or tri-state outputs. The 1-Wire port of the DS1921G is open-drain with an internal circuit equivalent to that shown in Figure 12. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a maximum data rate of 16.3kbits per second. The speed can be boosted to 142kbits per second by activating the Overdrive mode. The DS1921G is not guaranteed to be fully compliant to the iButton Standard. Its maximum data rate in standard speed mode is 15.4kbits per second and 125kbits per second in Overdrive. The value of the pullup resistor primarily depends on the network size and load conditions. The DS1921G requires a pullup resistor of maximum 2.2kW at any speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset. Note that the DS1921G does not quite meet the full 16µs maximum low time of the normal 1-Wire bus Overdrive timing. With the DS1921G the bus must be left low for no longer than 15µs at Overdrive speed to ensure that no DS1921G on the 1-Wire bus performs a reset. The DS1921G will communicate properly when used in conjunction with a DS2480B or DS2490 1-Wire driver and adapters that are based on these driver chips. 24 of 44 DS1921G Figure 12. HARDWARE CONFIGURATION BUS MASTER VPUP DS1921 1-Wire PORT RPUP RX DATA TX RX = RECEIVE Open Drain Port Pin RX TX 5 µA Typ. TX = TRANSMIT 100 W MOSFET TRANSACTION SEQUENCE The protocol for accessing the DS1921G via the 1-Wire port is as follows: § § § § Initialization ROM Function Command Memory/Control Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1921G is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the seven ROM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 13). Read ROM [33h] This command allows the bus master to read the DS1921G's 8-bit family code, unique 48-bit serial number and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1921G on a multidrop bus. Only the DS1921G that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All other slaves will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. 25 of 44 DS1921G Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Conditional Search [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the specified condition will participate in the search. The condition is specified by the bit functions TAS, THS, and TLS in the Control Register, address 20Eh. The Conditional Search ROM provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a temperature leaving the tolerance band. After each pass of the conditional search that successfully determined the 64-bit ROM code for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. For the conditional search, one can select any combination of the three search conditions by writing the associated bit to a logical 1. These bits correspond directly to the flags in the Status Register of the device. If the flag in the status register reads 1 and the corresponding bit in the Control Register is a logical 1 too, the device will respond to the Conditional Search command. If more than one bit search condition is selected, the first event occurring will make the device respond to the Conditional Search command. Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). 26 of 44 DS1921G Figure 13-1. ROM FUNCTIONS FLOW CHART Master TX Reset Pulse From Memory/Control Functions Flow Chart (Figure 10) N Short Reset Pulse? OD = 0 Y 33H Read ROM? N Y DS1921 TX Presence Pulse 2) Master TX ROM Function Command 1) 55H Match ROM? From Figure 13 nd 2 Part F0H Search ROM? N Y To Figure 13 nd 2 Part ECH Cond. Search ROM? N Y N Y N Cond. Met? Y DS1921 TX Family Code 1 Byte 1) Master TX Bit 0 Bit 0 Match? 1) N N DS1921 TX Bit 0 1) DS1921 TX Bit 0 DS1921 TX Bit 0 1) DS1921 TX Bit 0 1) Master TX Bit 0 1) Master TX Bit 0 1) Y DS1921 TX Serial Number 6 Bytes Bit 1 Match? 1) N N 1) DS1921 TX Bit 1 1) DS1921 TX Bit 1 1) DS1921 TX Bit 1 1) Master TX Bit 1 1) Master TX Bit 1 1) 1) N N 2) To be transmitted or received at Overdrive speed if OD = 1. The Presence Pulse will be short if OD = 1. Y DS1921 TX Bit 63 1) DS1921 TX Bit 63 1) DS1921 TX Bit 63 1) Bit 63 Match? Y 1) Bit 1 Match? DS1921 TX Bit 63 1) Master TX Bit 63 Bit 63 Match? N Bit 1 Match? Y 1) Master TX Bit 63 Y DS1921 TX Bit 1 Y DS1921 TX CRC Byte Bit 0 Match? Y 1) Master TX Bit 1 N Bit 0 Match? 1) 1) Master TX Bit 63 N Bit 63 Match? Y To Memory/Control Functions Flow Chart (Figure 10) 27 of 44 Y 1) To Figure 13 nd 2 Part From Figure 13 nd 2 Part DS1921G Figure 13-2. ROM FUNCTIONS FLOW CHART To Figure 13 st 1 Part From Figure 13 st 1 Part N CCH Skip ROM? 3CH Overdrive Skip ROM? Y N 69H Overdrive Match? Y OD = 1 N Y OD = 1 Master TX Bit 0 Bit 0 Match? 3) N Y Master TX Bit 1 3) Y Master TX Reset Pulse? Bit 1 Match? N Y Master TX Bit 63 Bit 63 Match? From Figure 13 st 1 Part To Figure 13 st 1 Part Y 3) Always to be transmitted at Overdrive speed. 28 of 44 N 3) N DS1921G Overdrive Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS1921G in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). Overdrive Match ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS1921G on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS1921G that exactly matches the 64-bit ROM sequence will respond to the subsequent memory/control function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command will remain in Overdrive mode. All overdrivecapable slaves will return to standard speed at the next Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 1-WIRE SIGNALING The DS1921G requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read Data. Except for the presence pulse the bus master initiates all these signals. The DS1921G can communicate at two different speeds: standard speed and Overdrive speed. If not explicitly set into the Overdrive mode, the DS1921G will communicate at standard speed. While in Overdrive Mode the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to make this rise is seen in Figure 14 as ‘e’ and its duration depends on the pullup resistor (RPUP) used and capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS1921G when determining a logical level, but not for triggering any events. The initialization sequence required to begin any communication with the DS1921G is shown in Figure 14. A Reset Pulse followed by a Presence Pulse indicates the DS1921G is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480µs or longer will exit the Overdrive Mode returning the device to standard speed. If the DS1921G is in Overdrive Mode and tRSTL is no longer than 80µs, the device will remain in Overdrive Mode. 29 of 44 DS1921G Figure 14. INITIALIZATION PROCEDURE (RESET AND PRESENCE PULSES) MASTER TX RESET PULSE tMSP e VPUP VIHMASTER VTH VTL VILMAX 0V MASTER RX PRESENCE PULSE tF tRSTL RESISTOR tPDH MASTER tPDL tRSTH tREC DS1921G After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold VTH is crossed, the DS1921G waits for tPDH and then transmits a Presence Pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the DS1921G is ready for data communication. In a mixed population network, tRSTH should be extended to minimum 480µs at standard speed and 48µs at Overdrive speed to accommodate other 1Wire devices. Read/Write Time Slots Data communication with the DS1921G takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time-slots transfer data from slave to master. The definitions of the write and read time slots are illustrated in Figure 15. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold VTL, the DS1921G starts its internal timing generator that determines when the data line will be sampled during a write time slot and how long data will be valid during a read time slot. Master to Slave For a write-one time slot, the voltage on the data line must have crossed the VTH threshold after the write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. The voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the DS1921G needs a recovery time tREC before it is ready for the next time slot. 30 of 44 DS1921G Figure 15. READ/WRITE TIMING DIAGRAM Write-One Time Slot tW1L VPUP VIHMASTER VTH VTL VILMAX 0V tF e tSLOT RESISTOR MASTER Write-Zero Time Slot tW0L VPUP VIHMASTER VTH VTL VILMAX 0V tF tSLOT RESISTOR tREC MASTER Read-Data Time Slot tMSR tRL VPUP VIHMASTER VTH Master Sampling Window VTL VILMAX 0V tF d RESISTOR tREC tSLOT MASTER DS1921G Slave to Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS1921G will start pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS1921G will not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL + d (rise rime) on one side and the internal timing generator of the DS1921G on the other side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line. For most reliable communication, tRL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS1921G to get ready for the next time slot. 31 of 44 DS1921G CRC GENERATION With the DS1921G there are two different types of Cyclic Redundancy Checks (CRCs). One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1921G to determine if the ROM data has been received error-free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non-inverted) form. It is computed at the factory and lasered into the ROM. The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function X16 + X15 + X2 + 1. This CRC is used for error detection when reading data memory using the Read Memory with CRC command and for fast verification of a data transfer when writing to or reading from the scratchpad. In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC-generator inside the DS1921G chip (Figure 16) will calculate a new 16-bit CRC as shown in the command flow chart of Figure 10. The bus master compares the CRC value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the CRC error. With the initial pass through the Read Memory with CRC flow chart, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the 2 address bytes and the data bytes. Subsequent passes through the Read Memory with CRC flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the data bytes. With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then shifting in the command code, the Target Addresses TA1 and TA2 and all the data bytes. The DS1921G will transmit this CRC only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. The data may start at any location within the scratchpad. With the Read Scratchpad command the CRC is generated by first clearing the CRC generator and then shifting in the command code, the Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data starting at the target address. The DS1921G will transmit this CRC only if the reading continues through the end of the scratchpad, regardless of the actual ending offset. For more information on generating CRC values see Application Note 27 or the Book of DS19xx iButton Standards. 32 of 44 DS1921G Figure 16. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL 16 Polynomial = X st nd 1 STAGE 0 th 8 2 X th 10 STAGE 9 X 10 X 11 X 12 X 13 X 8 STAGE 7 X th 14 STAGE X th 7 STAGE 6 X th 13 STAGE th 6 STAGE 5 X th 12 STAGE th 5 STAGE 4 X th 11 STAGE 2 +X +1 th 4 STAGE 3 X th 9 STAGE th 3 STAGE 1 X X rd 2 STAGE 15 +X th 15 STAGE 14 X 16 STAGE 15 X 16 X INPUT DATA CRC OUTPUT Command-Specific 1-Wire Communication Protocol — Legend Symbol RST PD Select WS RS CPS RM RMC CM CT TA TA-E/S <data to EOS> <data to EOP> <data to EOM> <00 to EOP> <32 bytes> <data> CRC16\ FF loop AA loop 00 loop Description 1-Wire Reset Pulse generated by master 1-Wire Presence Pulse generated by slave Command and data to satisfy the ROM function protocol (Skip ROM, Search ROM, etc.) Command "Write Scratchpad" Command "Read Scratchpad" Command "Copy Scratchpad" Command "Read Memory" Command "Read Memory with CRC" Command "Clear Memory" Command "Convert Temperature" Target Address TA1, TA2 Target Address TA1, TA2 with E/S byte Transfer of as many data bytes as are needed to reach the scratchpad offset 1Fh Transfer of as many data bytes as are needed to reach the end of a memory page Transfer of as many data bytes as are needed to reach the end of the datalog memory Transfer of as many 00h bytes as are needed to reach a memory page boundary Transfer of 32 bytes Transfer of an undetermined amount of data Transfer of an inverted CRC16 Indefinite loop where the master reads FFh bytes Indefinite loop where the master reads AAh bytes Indefinite loop where the master reads 00h bytes 33 of 44 DS1921G Command-Specific 1-Wire Communication Protocol — Color Codes Master to slave Slave to master Write Scratchpad, reaching the end of the Scratchpad RST PD Select WS TA <data to EOS> CRC16\ FF loop Write Scratchpad, not reaching the end of the Scratchpad RST PD Select WS TA <data> RS TA-E/S RST PD Read Scratchpad RST PD Select <data to EOS> CRC16\ FF loop Copy Scratchpad (success) RST PD Select CPS TA-E/S AA loop Copy Scratchpad (invalid TA-E/S) RST PD Select CPS TA-E/S FF loop Read Memory (success) RST PD Select RM TA <data to EOM> 00 loop Read Memory (invalid address) RST PD Select RM TA 00 loop Reading reserved pages 20 through 63 or 68 through 127 or pages 192 and higher (beyond datalog memory) will result in 00h bytes. Read Memory with CRC (success) RST PD Select RMC TA <data to EOP> CRC16\ <32 bytes> CRC16\ The "32 bytes" are either valid page data or 00h bytes when reading reserved pages 20 through 63 or 68 Loop through 127 or pages 192 and higher (beyond datalog memory). 34 of 44 DS1921G Read Memory with CRC (invalid address) RST PD Select RMC TA <00 to EOP> The "32 bytes" are all 00h. CRC16\ <32 bytes> CRC16\ Loop Clear Memory RST PD Select CM FF loop To verify success, read the Status Register at address 0214h. If MEMCLR is 1, the command was executed successfully. Convert Temperature RST PD Select CT FF loop To read the result and to verify success, read the addresses 0211h (result) and the Device Samples Counter at address 021Dh to 021Fh. If the count has incremented, the command was executed successfully. 35 of 44 DS1921G MISSION EXAMPLE: PREPARE AND START A NEW MISSION Assumption: The previous mission has come to an end. To end an ongoing mission write the MIP bit in the Status Register to 0. The preparation of a DS1921G for a mission including the start of the mission requires up to four steps: Step 1: set the RTC (if it needs to be adjusted) Step 2: clear the data of the previous mission Step 3: set the search condition and mission start delay, clear alarm flags Step 4: set the temperature alarms and write the sample rate to start the mission STEP 1 Let the actual time be 15:30:00 hours on Monday, the 1st of April in 2002. This results in the following data to be written to the RTC registers: Address: Data: 200h 00h 201h 30h 202h 15h 203h 01h 204h 81h 205h 04h 206h 02h With only a single DS1921G connected to the bus master, the communication of step 1 is as follows: MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 00h 02h <7 data bytes> (Reset) (Presence) CCh AAh 00h 02h 06h <7 data bytes> (Reset) (Presence) CCh 55h 00h 02h 06h (Reset) (Presence) 36 of 44 COMMENTS Reset pulse (480µs to 960µs) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 00h TA2, address = 0200h Write 7 bytes of data to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 00h Read TA2, address = 0200h Read E/S, ending offset = 6h, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 (AUTHORIZATION CODE) E/S Reset pulse Presence pulse DS1921G STEP 2 Set the EMCLR bit to 1, enable the RTC and then execute the Clear Memory command. The RTC oscillator must be stable before the Clear Memory command is issued. Wait 500 µs after issuing the Clear Memory command before proceeding to Step 3. This results in the following data to be written to the Status Register: Address: Data: 20Eh 40h With only a single DS1921G connected to the bus master, the communication of step 2 is as follows: MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX TX TX TX RX DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 0Eh 02h 40h (Reset) (Presence) CCh AAh 0Eh 02h 0Eh 40h (Reset) (Presence) CCh 55h 0Eh 02h 0Eh (Reset) (Presence) CCh 3Ch (Reset) (Presence) 37 of 44 COMMENTS Reset pulse (480µs to 960µs) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 0Eh TA2, address = 020Eh Write status byte to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 0Eh Read TA2, address = 020Eh Read E/S, ending offset = 0Eh, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 (AUTHORIZATION CODE) E/S Reset pulse Presence pulse Issue Skip ROM command Issue Clear Memory command Reset pulse Presence pulse DS1921G STEP 3 In this example, the rollover is disabled and the search condition is set for a high temperature only. The mission is to start with a delay of 90 (005Ah) minutes and the alarm flags TLF, THF, and TAF are cleared. This results in the following data to be written to the special function registers: Address: Data: 20Eh 02h 20Fh 00h* 210h 00h* 211h 00h* 212h 5Ah 213h 00h 214h 00h * Writing through address locations 20Fh to 211h is faster than accessing the Mission Start Delay Register in a separate cycle. The write attempt has no effect on the contents of these registers. With only a single DS1921G connected to the bus master, the communication of step 3 is as follows: MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 0Eh 02h <7 data bytes> (Reset) (Presence) CCh AAh 0Eh 02h 14h <7 data bytes> (Reset) (Presence) CCh 55h 0Eh 02h 13h (Reset) (Presence) 38 of 44 COMMENTS Reset Pulse (480µs to 960µs) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 0Eh TA2, address = 020Eh Write 7 bytes of data to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 0Eh Read TA2, address = 020Eh Read E/S, ending offset = 14h, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 (AUTHORIZATION CODE) E/S Reset pulse Presence pulse DS1921G STEP 4 In this example, the temperature alarms are set to -5°C for the low temperature threshold and 0°C for the high temperature threshold. The sample rate is once every 10 minutes, allowing the mission to last up to 14 days. This results in the following data to be written to the special function registers: Address: Data: 20Bh 46h 20Ch 50h 20Dh 0Ah With only a single DS1921G connected to the bus master, the communication of step 4 is as follows: MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX DATA (LSB FIRST) (Reset) (Presence) CCh 0Fh 0Bh 02h <3 data bytes> (Reset) (Presence) CCh AAh 0Bh 02h 0Dh <3 data bytes> (Reset) (Presence) CCh 55h 0Bh 02h 0Dh (Reset) (Presence) COMMENTS Reset pulse (480µs to 960µs) Presence pulse Issue Skip ROM command Issue Write Scratchpad command TA1, beginning offset = 0Bh TA2, address = 020Bh Write 3 bytes of data to scratchpad Reset pulse Presence pulse Issue Skip ROM command Issue Read Scratchpad command Read TA1, beginning offset = 0Bh Read TA2, address = 020Bh Read E/S, ending offset = 0Dh, flags = 0h Read scratchpad data and verify Reset pulse Presence pulse Issue Skip ROM command Issue Copy Scratchpad command TA1 TA2 (AUTHORIZATION CODE) E/S Reset pulse Presence pulse If step 4 was successful, the MIP bit in the Status Register will be 1, the MEMCLR bit will be 0, and the mission start delay will be counting down. 39 of 44 DS1921G PHYSICAL SPECIFICATION Size Weight Safety See mechanical drawing 3.3g Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, approval under Entity Concept for use in Class I, Division 1, Group A, B, C, and D Locations (application pending) ABSOLUTE MAXIMUM RATINGS* IO Voltage to GND IO Sink Current Temperature Range Storage Temperature Range -0.5V, +6V 20mA -40°C to +85°C** -40°C to +50°C** * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ** Storage or operation above 50°C significantly reduces battery life. ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 5.25V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS IO pin general data 1-Wire Pullup RPUP Resistance Input Capacitance CIO Input Load Current IL IO pin at VPUP High-to-Low VPUP > 4.5V VTL Switching Threshold Input Low Voltage VIL Low-to-High VPUP > 4.5V VTH Switching Threshold Output low voltage at VOL 4mA Standard Speed, RPUP = 2.2kW Overdrive Speed, Recovery Time tREC RPUP = 2.2kW Overdrive Speed, directly prior to reset pulse; RPUP = 2.2kW Standard Speed Timeslot Duration tSLOT Overdrive Speed 40 of 44 MIN TYP 100 1.14 0.71 1.00 0.66 MAX UNITS NOTES 2.2 kW 1, 2 800 10 2.70 2.70 0.30 2.70 2.70 pF µA 3, 16 4 5, 6, 7, 16 1, 5, 8 5, 6, 9, 16 0.4 V 5, 10 µs 1, 16 µs 1, 15 V V V 5 2 5 65 8 DS1921G PARAMETER SYMBOL CONDITIONS IO pin, 1-Wire Reset, Presence detect cycle Standard Speed, VPUP > 4.5V Reset Low Time tRSTL Standard Speed Overdrive Speed Presence Detect High Standard Speed tPDH Time Overdrive Speed Presence Detect Low Standard Speed tPDL Time Overdrive Speed Presence Detect Standard Speed tMSP Sample Time Overdrive Speed IO pin, 1-Wire Write Standard Speed Write-0 Low Time tW0L Overdrive Speed Standard Speed Write-1 Low Time tW1L Overdrive Speed IO pin, 1-Wire Read Standard Speed Read Low Time tRL Overdrive Speed Standard Speed Read Sample Time tMSR Overdrive Speed Real Time Clock Frequency Deviation -5°C to +46°C DF Temperature Converter Tempcore Operating TTC Range Conversion Time tCONV Thermal Response tRESP Time Constant -40°C to <-30°C -30°C to +70°C Conversion Error DJ >+70°C to +85°C Number of NCONV Conversions 41 of 44 MIN TYP MAX UNITS NOTES 480 640 540 48 15 1.1 60 7.5 60 6 640 80 60 6 270 24 75 8.6 60 6 5 1 120 15 15 - e 2-e 5 1 tRL + d tRL + d 15 - d 2-d 15 2 -48 +46 PPM -40 +85 °C 19 90 ms 130 -1.3 -1.0 -1.3 +1.3 +1.0 +1.3 (see graphs) µs 1, 15 µs 15 µs 15 µs 1, 16 µs 1, 15 µs 1, 11 µs 1, 12 µs 1, 12 s 13 °C 17 --- 14, 16 DS1921G NOTES 1) System Requirement. 2) Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. 3) Capacitance on IO could be 800pF when power is first applied. If a 2.2kW resistor is used to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitor will not affect normal communication. 4) Input load is to ground. 5) All voltages are referenced to ground. 6) VTL, VTH are a function of the internal supply voltage. 7) Voltage below which, during a falling edge on IO, a logic 0 is detected. 8) The voltage on IO needs to be less or equal to VILMAX whenever the master drives the line low. 9) Voltage above which, during a rising edge on IO, a logic 1 is detected. 10) The I-V characteristic is linear for voltages less than 1V. 11) e represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. 12) d represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. 13) This number was derived from a test conducted by Cemagref in Antony, France, in July of 2000. http://www.cemagref.fr/English/index.htm Test Report No. E42 14) The number of temperature conversions (= Samples) possible with the built-in energy source depends on the operating and storage temperature of the device. When not in use for a mission, the RTC oscillator should be turned off and device should be stored at a temperature not exceeding 25°C. Under this condition the shelf life time is 10 years minimum. 15) Highlighted numbers are not in compliance with the published iButton standards. See comparison table below. 16) These values are derived from simulation across process, voltage, and temperature and are not production tested. 17) Total accuracy is DJ plus 0.25°C quantization due to the 0.5°C digital resolution of the device. Parameter Name tSLOT (incl. tREC) tRSTL tPDH tPDL tW0L Standard Values Standard Speed Overdrive Speed min max min max 61µs (undef.) 7µs (undef.) 480µs (undef.) 48µs 80µs 15µs 60µs 2µs 6µs 60µs 240µs 8µs 24µs 60µs 120µs 6µs 16µs 1) Intentional change, longer recovery time between time slots. 42 of 44 DS1921GValues Standard Speed Overdrive Speed min max min max 65µs 1) (undef.) 8µs 1) (undef.) 540µs 640µs 48µs 80µs 15µs 60µs 1.1µs 6µs 60µs 270µs 7.5µs 24µs 60µs 120µs 6µs 15µs DS1921G RTC Deviation vs Temperature Lower Limit Upper Limit RTC Deviation (Minutes/Month) 4 2 0 -2 -4 -6 -8 -10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Minimum Product Lifetime vs Temperature at Different Sample Rates Every Minute Every 3 Min. No Samples Osc. Off Every 10 Min. Min. Product Lifetime (years) 11.00 10.00 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (°C) 43 of 44 60 70 80 DS1921G Minimum Product Lifetime vs Sample Rate at Different Temperatures -40°C -20 °C 15°C 40°C 45°C 50°C 55°C 60°C 70°C 85°C Minimum Product Lifetime (years) 11.00 10.00 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 1 10 100 1000 Minutes between Samples Accuracy Limits Upper Limit Lower Limit 2 1.5 Accuracy in °C 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 -1 -1.5 -2 Temperature in °C 44 of 44 60 70 80