MAXIM MAX5816

19-6149; Rev 0; 2/12
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
General Description
The MAX5816 4-channel, low-power, 12-bit, voltageoutput digital-to-analog converter (DAC) includes output
buffers and an internal reference that is selectable to be
2.048V, 2.500V, or 4.096V. The MAX5816 accepts a wide
supply voltage range of 2.7V to 5.5V with extremely low
power (3mW) consumption to accommodate most lowvoltage applications. A precision external reference input
allows rail-to-rail operation and presents a 100kI (typ)
load to an external reference.
The MAX5816 has an I2C-compatible, 2-wire interface that
operates at clock rates up to 400kHz. The DAC output is
buffered and has a low supply current of less than 250FA
per channel and a low offset error of Q0.5mV (typ). On
power-up, the MAX5816 resets the DAC outputs to zero,
providing additional safety for applications that drive
valves or other transducers which need to be off on power-up. The internal reference is initially powered down to
allow use of an external reference. The MAX5816 allows
simultaneous output updates using software LOAD commands. Multiple devices can simultaneously be updated
using software load command in combination with the
broadcast ID.
Benefits and Features
SFour High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment

±1 LSB INL Buffered Voltage Output

Guaranteed Monotonic Over All Operating
Conditions

Independent Mode Settings for Each DAC
SThree Precision Selectable Internal References

2.048V, 2.500V, or 4.096V
SInternal Output Buffer

Rail-to-Rail Operation with External Reference
4.5µs Settling Time
Outputs Directly Drive 2kI Loads
SSmall 3mm x 3mm 10-Pin TDFN Package
SWide 2.7V to 5.5V Supply Range
SFast 400kHz I2C-Compatible, 2-Wire Serial
Interface
SPower-On-Reset to Zero-Scale DAC Output
SThree Software-Selectable Power-Down Output
Impedances

1kI, 100kI, or High Impedance
The MAX5816 is available in a 10-pin TDFN package and
is specified over the -40NC to +125NC temperature range.
Applications
Functional Diagram
Programmable Voltage and Current Sources
Gain and Offset Adjustment
VDD
Automatic Tuning and Optical Control
REF
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
Data Acquisition
Ordering Information appears at end of data sheet.
MAX5816
INTERNAL REFERENCE/
EXTERNAL BUFFER
SCL
SDA
1 OF 4 DAC CHANNELS
I2C SERIAL
INTERFACE
CODE
REGISTER
DAC
LATCH
8 -/10-/12-BIT
DAC
OUTA
BUFFER
ADDR
OUTB
CODE
POR
CLEAR/
RESET
LOAD
OUTC
CLEAR/
RESET
DAC CONTROL LOGIC
100kI
1kI
OUTD
POWER-DOWN
GND
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX5816.related
���������������������������������������������������������������� Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND..............................................................-0.3V to +6V
OUT_, REF to GND.....0.3V to the lower of (VDD + 0.3V) and +6V
SCL, SDA to GND....................................................-0.3V to +6V
ADDR to GND.........-0.3V to the lower of (VDD + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TDFN (derate at 24.4mW/NC above 70NC)..............1951.2mW
Maximum Continuous Current into Any Pin..................... Q50mA
Operating Temperature..................................... -40NC to +125NC
Storage Temperature........................................ -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow)..................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θJA) ..........41NC/W
Junction-to-Case Thermal Resistance (θJC)..................9NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC PERFORMANCE (Note 3)
Resolution and Monotonicity
N
12
Integral Nonlinearity (Note 4)
INL
-1
Q0. 5
+1
LSB
Differential Nonlinearity (Note 4)
DNL
-1
Q0.2
+1
LSB
OE
-5
Q0.5
+5
mV
GE
-1.0
Q0.1
Offset Error (Note 5)
Offset Error Drift
Bits
Q10
Gain Error (Note 5)
Gain Temperature Coefficient
With respect to VREF
Zero-Scale Error
Full-Scale Error
With respect to VREF
FV/NC
+1.0
%FS
ppm of
FS/NC
Q3.0
0
10
mV
-0.5
+0.5
%FS
DAC OUTPUT CHARACTERISTICS
No load
Output Voltage Range (Note 6)
0
VDD
2kI load to GND
0
VDD 0.2
2kI load to VDD
0.2
VDD
V
���������������������������������������������������������������� Maxim Integrated Products 2
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Load Regulation
CONDITIONS
VOUT = VFS/2
DC Output Impedance
VOUT = VFS/2
Maximum Capacitive Load
Handling
CL
Resistive Load Handling
RL
Short-Circuit Output Current
TYP
300
VDD = 5V Q10%,
|IOUT| P 10mA
300
VDD = 3V Q10%,
|IOUT| P 5mA
0.3
VDD = 5V Q10%,
|IOUT| P 10mA
0.3
MAX
UNITS
FV/mA
I
500
2
VDD = 5.5V
DC Power-Supply Rejection
MIN
VDD = 3V Q10%,
|IOUT| P 5mA
pF
kI
Sourcing (output
shorted to GND)
30
Sinking (output
shorted to VDD)
50
mA
VDD = 3V Q10% or 5V Q10%
100
FV/V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Positive and negative
1.0
V/Fs
Voltage-Output Settling Time
¼ scale to ¾ scale, to P 1 LSB
4.5
Fs
DAC Glitch Impulse
Major code transition
2
nV*s
Channel-to-Channel
Feedthrough (Note 7)
External reference
3.5
Internal reference
3.3
Digital Feedthrough
Code = 0, all digital inputs from 0V to VDD
0.2
nV*s
Startup calibration time (Note 8)
200
Fs
From power-down
50
Fs
Power-Up Time
SR
External reference
Output Voltage-Noise Density
(DAC Output at Midscale)
f = 1kHz
nV*s
90
f = 10kHz
82
2.048V internal
reference
f = 1kHz
112
f = 10kHz
102
2.5V internal
reference
f = 1kHz
125
f = 10kHz
110
4.096V internal
reference
f = 1kHz
160
f = 10kHz
145
nV/√Hz
���������������������������������������������������������������� Maxim Integrated Products 3
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
External reference
2.048V internal
reference
Integrated Output Noise
(DAC Output at Midscale)
2.5V internal
reference
TYP
f = 0.1Hz to 10Hz
12
f = 0.1Hz to 10kHz
76
f = 0.1Hz to 300kHz
385
f = 0.1Hz to 10Hz
14
f = 0.1Hz to 10kHz
91
f = 0.1Hz to 300kHz
450
f = 0.1Hz to 10Hz
15
f = 0.1Hz to 10kHz
99
f = 0.1Hz to 300kHz
470
f = 0.1Hz to 10Hz
16
f = 0.1Hz to 10kHz
124
f = 0.1Hz to 300kHz
490
f = 1kHz
114
f = 10kHz
99
2.048V internal
reference
f = 1kHz
175
f = 10kHz
153
2.5V internal
reference
f = 1kHz
200
f = 10kHz
174
4.096V internal
reference
f = 1kHz
295
f = 10kHz
255
f = 0.1Hz to 10Hz
13
f = 0.1Hz to 10kHz
94
f = 0.1Hz to 300kHz
540
f = 0.1Hz to 10Hz
19
f = 0.1Hz to 10kHz
143
f = 0.1Hz to 300kHz
685
f = 0.1Hz to 10Hz
21
f = 0.1Hz to 10kHz
159
f = 0.1Hz to 300kHz
705
f = 0.1Hz to 10Hz
26
f = 0.1Hz to 10kHz
213
f = 0.1Hz to 300kHz
750
4.096V internal
reference
External reference
Output Voltage-Noise Density
(DAC Output at Full Scale)
MIN
External reference
2.048V internal
reference
Integrated Output Noise
(DAC Output at Full Scale)
2.5V internal
reference
4.096V internal
reference
MAX
UNITS
FVP-P
nV/√Hz
FVP-P
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Current
IREF
Reference Input Impedance
RREF
1.24
VREF = VDD = 5.5V
VDD
55
75
100
74
V
FA
kI
���������������������������������������������������������������� Maxim Integrated Products 4
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VREF = 2.048V, TA = +25NC
2.043
2.048
2.053
VREF = 2.5V, TA = +25NC
2.494
2.5
2.506
VREF = 4.096V, TA = +25NC
4.086
4.096
4.106
Q10
Q25
UNITS
REFERENCE OUPUT
Reference Output Voltage
VREF
Reference Temperature
Coefficient
Reference Drive Capacity
External load
Reference Capacitive Load
Reference Load Regulation
ISOURCE = 0 to 500FA
Reference Line Regulation
V
ppm/NC
25
kI
200
pF
2
mV/mA
0.05
mV/V
POWER REQUIREMENTS
Supply Voltage
VDD
Supply Current (Note 9)
IDD
VREF = 4.096V
4.5
5.5
All other options
2.7
5.5
Internal reference,
VDD = 5.5V
External reference
Power-Down Mode Supply
Current
IPD
VREF = 2.048V
0.85
1.25
VREF = 2.5V
0.9
1.25
VREF = 4.096V
1.1
1.40
VDD = VREF = 3V
0.65
1.1
VDD = VREF = 5V
0.9
1.25
All DACs off, internal reference ON
140
All DACs off, internal reference OFF,
TA = -40NC to +85NC
0.5
1
All DACs off, internal reference OFF,
TA = +125NC
1.2
2.5
V
mA
FA
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR)
Input High Voltage
VIH
2.7V < VDD < 5.5V
Input Low Voltage
VIL
2.7V < VDD < 5.5V
Hysteresis Voltage
VH
Input Leakage Current
IIN
Input Capacitance (Note 10)
CIN
ADDR Pullup/Pulldown Strength
RPU, RPD
0.7 x
VDD
V
0.3 x
VDD
0.15
VIN = 0V or VDD
(Note 11)
Q0.1
30
50
V
V
Q1
FA
10
pF
90
kI
0.2
V
DIGITAL OUTPUT (SDA)
Output Low Voltage
VOL
ISINK = 3mA
���������������������������������������������������������������� Maxim Integrated Products 5
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 2)
PARAMETER
I2C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS (SCL, SDA)
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
Fs
tHD;STA
0.6
Fs
SCL Pulse Width Low
tLOW
1.3
Fs
SCL Pulse Width High
tHIGH
0.6
Fs
Setup Time for Repeated START
Condition
tSU;STA
0.6
Fs
Data Hold Time
tHD;DAT
0
Data Setup Time
tSU;DAT
100
SDA and SCL Receiving
Rise Time
tr
20 +
CB/10
300
ns
SDA and SCL Receiving
Fall Time
tf
20 +
CB/10
300
ns
SDA Transmitting Fall Time
tf
20 +
CB/10
250
ns
tSU;STO
0.6
Bus Capacitance Allowed
CB
10
Pulse Width of Suppressed Spike
tsp
Hold Time Repeated for a
START Condition
Setup Time for STOP Condition
900
ns
ns
Fs
400
50
pF
ns
Note 2: Limits are 100% production tested at TA = +25°C and/or TA = +125°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25°C and are
not guaranteed.
Note 3: DC Performance is tested without load.
Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 5: Gain and offset tested at code 4065 and 30, respectively with VREF = VDD.
Note 6: Subject to zero and full-scale error limits and VREF settings.
Note 7: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 8: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 9: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDD.
Note 10:Guaranteed by design.
Note 11:An unconnected condition on the ADDR pin is sensed via a resistive pullup and pulldown operation; for proper operation,
the ADDR pin should be tied to VDD, GND, or left unconnected with minimal capacitance.
���������������������������������������������������������������� Maxim Integrated Products 6
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
SDA
tLOW
tf
tSU;DAT
tr
tSP
tHD;STA
tf
tBUF
tr
SCL
tHD;STA
S
tHIGH
tSU;STO
tSU;STA
tHD;DAT
Sr
P
S
Figure 1. I2C Serial Interface Timing Diagram
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
VDD = VREF = 5V
NO LOAD
0.8
0.6
DNL vs. CODE
1.0
MAX5816 toc02
0.6
0.6
0.4
0.2
0.2
0.2
-0.2
DNL (LSB)
0.4
0
0
-0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
VDD = VREF = 3V
NO LOAD
0.8
0.4
INL (LSB)
INL (LSB)
MAX5816 toc01
VDD = VREF = 3V
NO LOAD
0.8
INL vs. CODE
1.0
MAX5816 toc03
INL vs. CODE
1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
���������������������������������������������������������������� Maxim Integrated Products 7
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5816 toc04
VDD = VREF = 5V
NO LOAD
0.6
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
1.0
512 1024 1536 2048 2560 3072 3584 4096
0
-0.2
-0.4
MIN DNL
MIN INL
MIN DNL
-0.6
MIN INL
-0.8
-1.0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN-ERROR
vs. SUPPLY VOLTAGE
0.6
ZERO-SCALE ERROR
1.0
0.8
0.6
0.4
VREF = 2.5V (EXTERNAL)
NO LOAD
ZERO-SCALE ERROR
0.020
0.016
0.012
0
-0.2
OFFSET ERROR
-0.4
0.2
OFFSET ERROR (VDD = 5V)
0
-0.2
-0.4
OFFSET ERROR (VDD = 3V)
ERROR (%fs)
ERROR (mV)
0.2
0.004
0
-0.004
-0.6
-0.012
-0.8
-0.8
-0.016
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
5.1
5.5
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.020
-1.0
3.1
FULL-SCALE ERROR
-0.008
-0.6
-1.0
GAIN ERROR
0.008
0.4
2.7
MAX DNL
0.2
CODE (LSB)
VREF = 2.5V (EXTERNAL)
NO LOAD
0.8
MAX INL
0.4
MAX DNL
0.2
-0.4
0.6
ERROR (LSB)
ERROR (LSB)
0.2
0
ERROR (mV)
MAX INL
0.4
MAX5816 toc07
DNL (LSB)
0.4
VDD = VREF = 3V
0.8
MAX5816 toc09
0.6
VDD = VREF = 3V
0.8
MAX5816 toc08
0.8
INL AND DNL vs. TEMPERATURE
1.0
MAX5816 toc06
INL AND DNL vs. SUPPLY VOLTAGE
1.0
MAX5816 toc05
DNL vs. CODE
1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
���������������������������������������������������������������� Maxim Integrated Products 8
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
-0.05
1.0
MAX5816 toc11
0.8
VREF (INTERNAL) = 2.048V,
VDD = 5V
VREF (EXTERNAL) = VDD = 3V
0.4
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.8
TA = +25°C
0.4
3.9
4.3
0
2.7
4.7
VDD = VREF = 5V
VDD = 5V,
VREF = 4.096V
1.2
VDD = 5V,
VREF = 2.5V
1.0
0.8
0.6
VDD = VREF = 3V
0.4
5.1
5.5
3.5
3.9
4.3
4.7
5.1
5.5
60
VDD = 5V,
VREF = 2.048V
VDD = VREF
NO LOAD
50
40
VREF = 5V
30
VREF = 3V
20
10
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
SUPPLY VOLTAGE (V)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
CODE (LSB)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5816 toc16
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
VOUT
0.5V/div
3.1
IREF (EXTERNAL) vs. CODE
0.2
TA = -40°C
3.5
0.1
REFERENCE CURRENT (µA)
TA = +125°C
3.1
0.3
VDD (V)
NO LOAD
1.4
SUPPLY CURRENT (mA)
1.2
2.7
VREF (INTERNAL) = 2.048V,
VDD = 5V
0.4
IVDD vs. CODE
1.6
MAX5816 toc13
POWER-DOWN MODE
ALL DACs
0
VREF (INTERNAL) = 2.5V
0.5
TEMPERATURE (°C)
POWER-DOWN MODE SUPPLY CURRENT
vs. TEMPERATURE
TA = +85°C
VREF = 2.5V (EXTERNAL)
0.6
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1.6
0.7
0.2
0.6
-0.10
POWER-DOWN SUPPLY CURRENT (mA)
0.8
MAX5816 toc15
GAIN ERROR (VDD = 3V)
VREF (INTERNAL) = 4.096V,
VDD = 5V
VREF (INTERNAL) = 2.5V,
VDD = 5V
3/4 SCALE TO 1/4 SCALE
1/4 SCALE TO 3/4 SCALE
MAX5816 toc17
0
FULL-SCALE ERROR
1.2
NO LOAD
VREF (INTERNAL) = 4.096V
OUT_ = FULL SCALE
TA = +25°C
0.9
SUPPLY CURRENT (mA)
GAIN ERROR (VDD = 5V)
OUT_ = FULL SCALE
NO LOAD
VREF (EXTERNAL) = VDD = 5V
1.0
MAX5816 toc14
ERROR (%fsr)
0.05
SUPPLY CURRENT (mA)
VREF = 2.5V (EXTERNAL)
NO LOAD
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1.4
MAX5816 toc10
0.10
MAX5816 toc12
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
4.3µs
VOUT
0.5V/div
ZOOMED VOUT
1 LSB/div
ZOOMED VOUT
1 LSB/div
3.75µs
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
4µs/div
4µs/div
����������������������������������������������������������������� Maxim Integrated Products 9
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5816 toc18
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GLITCH IMPULSE = 2nV*s
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GLITCH IMPULSE = 2nV*s
ZOOMED VOUT
1.25mV/div
ZOOMED VOUT
1.25mV/div
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
2µs/div
MAX5816 toc19
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
2µs/div
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
POWER-ON RESET TO 0V
MAX5816 toc21
MAX5816 toc20
VSCL
5V/div
36TH EDGE
DAC OUTPUT
500mV/div
VDD
2V/div
VDD = VREF = 5V
10kI LOAD TO VDD
0V
0V
VOUT
2V/div
0V
VDD = 5V, VREF = 2.5V
EXTERNAL
0V
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC,
RL = 2kI, CL = 200pF)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC, NO LOAD)
TRANSITIONING
DAC
1V/div
RL = 2kI
STATIC DAC
1.25mV/div
NO LOAD
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.5nV*s
4µs/div
MAX5816 toc23
20µs/div
MAX5816 toc22
10µs/div
TRIGGER PULSE
10V/div
TRANSITIONING
DAC
1V/div
NO LOAD
STATIC DAC
1.25mV/div
NO LOAD
TRIGGER PULSE
10V/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.8nV*s
5µs/div
���������������������������������������������������������������� Maxim Integrated Products 10
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, RL = 2kI, CL = 200pF)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, NO LOAD) MAX5816 toc25
MAX5816 toc24
TRANSITIONING
DAC
1V/div
RL = 2kI
STATIC DAC
1.25mV/div
NO LOAD
STATIC DAC
1.25mV/div
NO LOAD
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.1nV*S
TRIGGER PULSE
10V/div
4µs/div
5µs/div
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
VDD = VREF
8
6
200
2
0
VDD = 3V
-2
-300
-8
-400
VOUT (V)
3.50
3.00
2.50
VDD = 3V, SOURCING
2.00
1.50
VDD = 3V AND 5V
SINKING
1.00
VDD = VREF
DAC = FULL SCALE
0.50
0
0
10
20
30
40
50
60
-30 -20 -10 0
10 20 30 40 50 60 70
IOUT (mA)
IOUT (mA)
NOISE-VOLTAGE DENSITY
VS. FREQUENCY (DAC AT MIDSCALE)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
MAX5816 toc31
MAX5816 toc30
350
NOISE-VOLTAGE DENSITY (nV/√Hz)
MAX5816 toc29
VDD = 5V, SOURCING
4.00
VDD = 3V
-500
-30 -20 -10
4.50
-100
-6
-10
5.00
0
-200
HEADROOM AT RAILS
vs. OUTPUT CURRENT
VDD = 5V
100
-4
50ns/div
VDD = VREF
300
DVOUT (mV)
DVOUT (mV)
DIGITAL FEEDTHROUGH = 0.1nV*s
400
VDD = 5V
4
VOUT_
1.65mV/div
500
MAX5816 toc27
MAX5816 toc26
VDD = 5V
VREF = 5V (EXTERNAL)
DAC AT MIDSCALE
OUTPUT CURRENT LIMITING
OUTPUT LOAD REGULATION
10
MAX5816 toc28
TRIGGER PULSE
10V/div
TRANSITIONING
DAC
1V/div
NO LOAD
VDD = 5V, VREF = 4.096V
(INTERNAL)
300
MIDSCALE UNLOADED
VP-P = 12µV
VDD = 5V, VREF = 2.5V
(INTERNAL)
250
VDD = 5V, VREF = 2.048V
(INTERNAL)
200
2µV/div
150
100
50
VDD = 5V, VREF = 4.5V
(EXTERNAL)
0
0
1
2
3
4
5
6
IOUT (mA)
7
8
9
10
100
1k
10k
100k
4s/div
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 11
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.5V)
MAX5816 toc32
MAX5816 toc33
MIDSCALE UNLOADED
VP-P = 13µV
MIDSCALE UNLOADED
VP-P = 15µV
2µV/div
2µV/div
4s/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
8
MIDSCALE UNLOADED
VP-P = 16µV
MAX5816 toc35
VREF DRIFT vs. TEMPERATURE
MAX5816 toc34
VDD = 2.7V
VREF = 2.5V
BOX METHOD
7
2µV/div
DEVICE COUNT
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10 11 12
4s/div
TEMPERATURE COEFFICIENT (ppm/°C)
-0.4
-0.6
VREF = 2.048V, 2.5V, AND 4.096V
-0.8
VDD = 5V
(RAMP UP)
1000
SUPPLY CURRENT (µA)
DVREF (mV)
-0.2
MAX5816 toc36
VDD = 5V
INTERNAL REFERENCE
1200
800
VDD = 5V
(RAMP DOWN)
600
VDD = 3V
(RAMP UP)
400
200
-1.0
0
50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
MAX5816 toc37
SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE
REFERENCE LOAD REGULATION
0
VDD = 3V
(RAMP DOWN)
0
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
���������������������������������������������������������������� Maxim Integrated Products 12
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Pin Configuration
TOP VIEW
1
OUTB
2
GND
3
OUTC
4
OUTD
5
10 REF
+
OUTA
MAX5816
*EP
9
VDD
8
SDA
7
SCL
6
ADDR
TDFN
Pin Description
PIN
NAME
FUNCTION
1
OUTA
Buffered Channel A DAC Output
2
OUTB
Buffered Channel B DAC Output
3
GND
Ground
4
OUTC
Buffered Channel C DAC Output
5
OUTD
Buffered Channel D DAC Output
6
ADDR
I2C Address Selection Input
7
SCL
Supply Voltage Input. I2C Interface Clock Input
8
SDA
I2C Bidirectional Serial Data
9
VDD
Digital Interface Power-Supply Input. Bypass with a 0.1μF capacitor to GND.
10
REF
Reference Voltage Input/Output
—
EP
Exposed Pad. Connect the exposed pad to ground.
��������������������������������������������������������������� Maxim Integrated Products 13
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Detailed Description
commands or can upload the current contents of the
CODE register using LOAD commands.
The MAX5816 is a 4-channel, low-power, 12-bit buffered voltage-output DAC. The 2.7V to 5.5V wide supply
voltage range and low-power consumption accommodates most low-power and low-voltage applications. The
device presents a 100kI load to the external reference.
The internal output buffers allow rail-to-rail operation.
An internal voltage reference is available with software
selectable options of 2.048V, 2.5V, or 4.096V. The device
features a fast 400kHz I2C-compatible interface. The
MAX5816 includes a serial-in/parallel-out shift register,
internal CODE and DAC registers, a power-on-reset
(POR) circuit to initialize the DAC outputs to code zero,
and control logic.
The contents of both CODE and DAC registers are maintained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register contents. SW_CLEAR and SW_RESET commands
(both clear and reset modes) reset the contents of all
CODE and DAC registers to their zero-scale defaults.
DAC Outputs (OUT_)
The MAX5816 includes internal buffers on all DAC outputs. The internal output buffers provide improved load
regulation for the DAC outputs. The output buffers slew
at 1V/Fs (typ) and drive up to 2kI in parallel with 500pF.
Under no-load conditions, the output buffers drive from
GND to VDD, subject to offset and gain errors. With a 2kω
load to GND, the output buffers drive from GND to within
200mV of VDD. With a 2kω load to VDD, the output buffers
drive to within 200mV of GND and VDD.
The DAC ideal output voltage is defined by:
D
VOUT
= VREF ×
2N
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user commands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
Internal Reference
The MAX5816 includes an internal precision voltage reference that is software selectable to be 2.048V, 2.500V,
or 4.096V. When an internal reference is selected, that
voltage is available on the REF pin for other external circuitry (see Figure 9) and can drive a 25kI load.
External Reference
The external reference input has a typical input impedance of 100kI and accepts an input voltage from +1.24V
to VDD. Connect an external voltage supply between REF
and GND to apply an external reference. The MAX5816
powers up and resets to external reference mode. Visit
www.maxim-ic.com/products/references for a list of
available external voltage-reference devices.
I2C Serial Interface
The MAX5816 features an I2C-/SMBusK-compatible,
2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL enable
communication between the MAX5816 and the master
at clock rates up to 400kHz. Figure 1 shows the 2-wire
interface timing diagram. The master generates SCL
and initiates data transfer on the bus. The master device
writes data to the MAX5816 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5816 is 8
bits long and is followed by an acknowledge clock pulse.
A master reading data from the MAX5816 must transmit
the proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5816
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or Repeated START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and
��������������������������������������������������������������� Maxim Integrated Products 14
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
an open-drain output. A pullup resistor, typically 4.7kI is
required on SDA. SCL operates only as an input. A pullup
resistor, typically 4.7kI, is required on SCL if there are
multiple masters on the bus, or if the single master has
an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5816
from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. The
MAX5816 can accommodate bus voltages higher than
VDD up to a limit of 5.5V; bus voltages lower than VDD
are not recommended and may result in significantly
increased interface currents.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX5816. The master terminates transmission
and frees the bus, by issuing a STOP condition. The bus
remains active if a Repeated START condition is generated instead of a STOP condition.
I2C Early STOP and
Repeated START Conditions
The MAX5816 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Transmissions ending in an early STOP condition will not
impact the internal device settings. If the STOP occurs
during a readback byte, the transmission is terminated
and a later read mode request will begin transfer of the
requested register data from the beginning (this applies
to combined format I2C read mode transfers only,
interface verification mode transfers will be corrupted).
See Figure 2.
I2C Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the R/W bit. See
Figure 4. The five most significant bits are 00011 with the
2 LSBs determined by ADDR as shown in Table 1. Setting
the R/W bit to 1 configures the MAX5816 for read mode.
S
Sr
P
SCL
SDA
VALID START, REPEATED START, AND STOP PULSES
P
S
S
P
P
S
P
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
Setting the R/W bit to 0 configures the MAX5816 for write
mode. The slave address is the first byte of information
sent to the MAX5816 after the START condition.
The MAX5816 has the ability to detect an unconnected
state on the ADDR input for additional address flexibility;
if leaving the ADDR input unconnected, be certain to
minimize all loading on the pin (i.e. provide a landing for
the pin, but do not allow any board traces).
Table 1. I2C Slave Address LSBs for
TDFN Package
ADDR
A1
A0
VDD
0
0
N.C.
1
0
GND
1
1
��������������������������������������������������������������� Maxim Integrated Products 15
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5816 devices on a
given I2C bus. All MAX5816 devices acknowledge and
respond to the broadcast device address 00010000. The
devices will respond to the broadcast address, regardless of the state of the address pins. The broadcast mode
is intended for use in write mode only (as indicated by
R/W = 0 in the address given).
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked
9th bit that the MAX5816 uses to handshake receipt of
each byte of data as shown in Figure 3. The MAX5816
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master will
retry communication.
In read mode, the master pulls down SDA during the 9th
clock cycle to acknowledge receipt of data when the
MAX5816 is in read mode. An acknowledge is sent by the
master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads
the final byte of data from the MAX5816, followed by a
STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
the ACK periods between bytes. This avoids any glitching or digital feedthrough to the DACs while the interface
is active.
I2C Write Operations (Standard Protocol)
A master device communicates with the MAX5816
by transmitting the proper slave address followed by
command and data words. Each transmit sequence
is framed by a START or Repeated START condition and a STOP condition as described above. Each
word is 8 bits long and is always followed by an
acknowledge clock (ACK) pulse as shown in the
Figure 4 and Figure 5. The first byte contains the
address of the MAX5816 with R/W = 0 to indicate a
write. The second byte contains the command (or
register) to be written and the third and fourth bytes
contain the data to be written. By repeating the command plus data byte pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can execute multiple
command writes using a single I2C write sequence.
There is no limit as to how many commands the user can
execute with a single write sequence. The MAX5816 supports this capability for all user-accessible write mode
commands.
CLOCK PULSE
FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 3. I2C Acknowledge
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
SDA
SCL
STOP
0
0 0
1 1 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
COMMAND EXECUTED
A ACK. GENERATED BY MAX5816
Figure 4. I2C Single Register Write Sequence
��������������������������������������������������������������� Maxim Integrated Products 16
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Readback of individual DAC registers is supported for
all user LOAD and CODE_LOAD commands. For these
commands, which support a DAC address, the requested DAC register content will be returned. If all DACs are
selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command. The power status of each DAC
is reported in locations B[3:0], with a 1 indicating the
DAC is powered down and a zero indicating the DAC is
operational (see Table 2).
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status device ID and revision
information in the format is shown in Table 2.
I2C Write Operation (Multibyte Operation)
The MAX5816 supports a multibyte transfer protocol for
some commands. In multibyte mode, once a command
is issued (with multibyte bit = 1), that command is continuously executed based on two byte data blocks for
the duration I2C operation. Essentially, bytes 1 to 4 are
processed normally, but for every two bytes of data provided after byte 4, the originally requested command is
executed again with the latest byte pair provided as input
data. Multibyte protocol is enforced until a STOP condition (or repeated START) is encountered, this provides a
higher speed transfer mode that is useful in servo DAC
applications.
Combined Format I2C Readback
Operations
Interface Verification I2C
Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5816 with R/W = 0 to indicate a
write. The second byte contains the register that is to be
read back. There is a Repeated START condition, followed by the device address with R/W = 1 to indicate a
read and an acknowledge clock. The master has control
of the SCL line but the MAX5816 takes over the SDA line.
The final two bytes in the frame contain the register data
readback followed by a STOP condition. If additional
bytes beyond those required to readback the requested
data are provided, the MAX5816 will continue to readback ones.
While the MAX5816 supports standard I2C readback of
selected registers, it is also capable of functioning in an
interface verification mode. This mode is accessed any
time a readback operation follows an executed write
mode command. In this mode, the last executed threebyte command is read back in its entirety. This behavior
allows verification of the interface.
Sample command sequences are shown in Figure 7. The
first command transfer is given in write mode with R/W =
0 and must be run to completion to qualify for interface
verification readback. There is now a STOP/START pair
or Repeated START condition required, followed by the
readback transfer with R/W = 1 to indicate a read and an
acknowledge clock from the MAX5816. The master still
has control of the SCL line but the MAX5816 takes over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5816 will continue
to read back ones.
Readback of individual CODE registers is supported for
all the user CODE commands. For these commands,
which support a DAC address, the requested channel
CODE register content will be returned; if all DACs are
selected, CODE A content will be returned.
Table 2. Standard I2C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
READBACK DATA LOW BYTE
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B3
B2
B1
B0
0
X
0
0
0
A2
A1
A0
CODEn[11:4]
CODEn[3:0]
B6
B5
0
0
0
0
0
X
0
0
1
A2
A1
A0
DACn[11:4]
DACn[3:0]
0
0
0
0
0
X
0
1
0
A2
A1
A0
DACn[11:4]
DACn[3:0]
0
0
0
0
0
X
0
1
1
A2
A1
A0
DACn[11:4]
DACn[3:0]
0
0
0
0
0
X
1
0
0
X
X
X
0
X
1
0
1
X
X
X
0
X
1
1
0
X
X
X
0
X
1
1
1
X
X
X
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
B4
0
PWD PWC PWB PWA
REV_ID
[2:0]
(010)
REF
MODE
[1:0]
��������������������������������������������������������������� Maxim Integrated Products 17
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0 0 0 1
SDA
SCL
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
1 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
COMMAND1
EXECUTED
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4
STOP
3 2 1 0 A
COMMANDn
EXECUTED
A ACK. GENERATED BY MAX5816
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
WRITE ADDRESS
BYTE #1: DEVICE ADDRESS
START
WRITE REGISTER NO.
BYTE #2: FIRST REG# = N
WRITE DATA
BYTE #3: REG(N)[15:8] DATA
WRITE DATA
BYTE #4: REG(N)[7:0] DATA
0 0 0 1 1 A1 A0 W A 0 1 N N N N N N A D D D D D D D D A D D D D D D D D A
SDA
SCL
REG N UPDATED
ADDITIONAL DATA BYTE PAIRS
(2 BYTE BLOCKS)
WRITE DATA
BYTE #X-1: REG(N)[15:8] DATA
WRITE DATA
BYTE #X: REG(N)[7:0] DATA
STOP
D D D D D D D D A D D D D D D D D A
REG N UPDATED
A ACK. GENERATED BY I2C MASTER
A ACK. GENERATED BY MAX5816
Figure 6. I2C Multibyte Register Write Sequence (Multibyte Protocol)
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS
START
SDA
SCL
0
0
0 1
WRITE COMMAND 1
BYTE #2: COMMAND 1
BYTE
1 A1 A0 W A 0 0 N N N N N N A
A ACK. GENERATED BY MAX5816
READ ADDRESS
BYTE #3: I2C SLAVE
ADDRESS
REPEATED
START
0
0
0 1
READ DATA
BYTE #4: DATA 1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA 1 LOW
BYTE (B[7:0])
STOP
1 A1 A0 R A D D D D D D D D A D D D D D D D D ~A
A ACK. GENERATED BY I2C MASTER
Figure 7. Standard I2C Register Read Sequence
��������������������������������������������������������������� Maxim Integrated Products 18
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
SDA
0 0
1
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
1 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0 A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
START
SDA
0 0
1
0 0
1
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
1 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
1 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
6
5
4
3
2
1
STOP
0 ~A
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
REPEATED
START
0
A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
0 0
1
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
1 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
A ACK. GENERATED BY MAX5816
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0 ~A
A ACK. GENERATED BY I2C MASTER
Figure 8. Interface Verification I2C Register Read Sequences
��������������������������������������������������������������� Maxim Integrated Products 19
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involving
other devices do not impact the MAX5816 readback mode.
Toggling between readback modes is based on the length
of the preceding write mode transfer. Combined format I2C
readback operation is resumed if a write command greater
than two bytes but less than four bytes is supplied. For
commands written using multiple register write sequences,
only the last command executed is read back. For each
command written, the readback sequence can only be
completed one time; partial and/or multiple attempts to
readback executed in succession will not yield usable data.
µC
SDA
SCL
MAX5816
SCL
SDA
ADDR
I2C Compatibility
The MAX5816 is fully compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has
an open drain which pulls the data line low to transmit
data or ACK pulses. Figure 9 shows a typical I2C application.
I2C User-Command Register Map
MAX5816
+5V
SCL
SDA
ADDR
This section lists the user accessible commands and
registers for the MAX5816.
Table 3 provides detailed information about the Command
Registers.
Figure 9. Typical I2C Application Circuit
��������������������������������������������������������������� Maxim Integrated Products 20
LOADn
CODEn_
ALL
LOAD_
CODEn_
LOADn
CODEn
0
0
0
0
DAC COMMANDS
0
0
0
0
0
0
0
0
1
1
0
0
COMMAND B23 B22 B21 B20
1
0
1
0
B19
X
X
ADDRESS
DATA [11:4]
CODE REGISTER
DATA [11:4]
DAC
CODE REGISTER
X
DAC
X
ADDRESS
ADDRESS
DAC
DATA [11:4]
X
B10
ADDRESS
B11
CODE REGISTER
B12
DAC
X
B18 B17 B16 B15 B14 B13
Table 3. I2C Commands Summary
X
B9
X
B8
B5
X
X
DATA [3:0]
X
B4
DATA [3:0]
CODE REGISTER
[3:0]
CODE REGISTER DATA
X
B6
CODE REGISTER
B7
X
X
X
X
B3
X
X
X
X
B2
X
X
X
X
B1
X
X
X
X
B0
Simultaneously
writes data to
the selected
CODE
register(s)
while updating
selected DAC
register(s).
Simultaneously
writes data to
the selected
CODE
register(s)
while updating
all DAC
registers.
Transfers
data from
the selected
CODE
registers to the
selected DAC
register(s).
Writes data
to the selected
CODE
register(s).
DESCRIPTION
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
��������������������������������������������������������������� Maxim Integrated Products 21
0
0
REF
0
0
CONFIG
CLEAR
SW_
RESET or
SW_
POWER
X
X
X
X
1
1
1
1
1
1
0
0
CONFIGURATION COMMANDS
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B17 B16 B15 B14 B13
X
X
X
X
B12
X
X
X
X
B11
X
X
X
X
B10
X
X
X
X
B9
X
X
X
X
B8
X
X
X
X
B7
X
X
X
X
B6
B4
X
X
X
Hi-Z
X
X
X
11 = PD
100kI
10 = PD
1kI
01 = PD
Normal
00 =
Mode
Power
B5
B3
B2
B1
0=
X
RST
1=
REF Mode
CLR
X
X
B0
X
DAC D
DAC D
DAC C
DAC C
REF Pow-er Mode
B18
DAC B
DAC B
COMMAND B23 B22 B21 B20 B19
DAC A
11 = 4.1V
10 = 2.0V
01 = 2.5V
00 = EXT
DAC A
Table 3. I2C Commands Summary (continued)
Sets the
reference
operating mode.
REF Power (B2):
0 = Internal
reference is only
powered if at
least one DAC is
powered
1 = Internal
reference is
always powered.
Sets the
DAC Latch
Mode of the
corresponding
DAC: 0 = DAC
latch is LOAD
controlled
1 = DAC latch is
transparent.
Executes a
software reset
(all registers
returned to their
default values)
or clear (all
CODE and DAC
registers cleared
to their default
values).
Sets the Power
Mode of the
selected DACs
(DACs selected
with a 1 in the
corresponding
DACn bit are
updated, DACs
with a 0 in the
corresponding
DACn bit are
not impacted).
DESCRIPTION
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
��������������������������������������������������������������� Maxim Integrated Products 22
Multibyte
LOADn
CODEn_
Multibyte
ALL
LOAD_
CODEn_
Multibyte
LOADn
Multibyte
CODEn
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
MULTIBYTE DAC COMMANDS
COMMAND B23 B22 B21 B20
1
0
1
0
B19
X
DATA[11:4]
CODE REGISTER
X
DATA[11:4]
X
DATA[11:4]
CODE REGISTER
X
X
B10
DAC
X
B11
CODE REGISTER
B12
ADDRESS
ADDRESS
DAC
ADDRESS
DAC
ADDRESS
DAC
B18 B17 B16 B15 B14 B13
Table 3. I2C Commands Summary (continued)
X
B9
X
B8
B6
B5
X
X
DATA[3:0]
CODE REGISTER
DATA[3:0]
CODE REGISTER
X
DATA[3:0]
X
B4
CODE REGISTER
B7
X
X
X
X
B3
X
X
X
X
B2
X
X
X
X
B1
X
X
X
X
B0
Simultaneously
writes data to
the selected
CODE
register(s)
while updating
selected DAC
register(s)
(multibyte
variant).
Simultaneously
writes data to
the selected
CODE
register(s) while
updating all
DAC registers
(multibyte
variant).
Transfers
data from
the selected
CODE
registers to the
selected DAC
register(s)
(multibyte
variant).
Writes data to
the selected
CODE
register(s)
(multibyte
variant).
DESCRIPTION
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
��������������������������������������������������������������� Maxim Integrated Products 23
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Table 4. DAC Selection
B18
B17
B16
0
0
0
DAC A
DAC SELECTED
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
X
X
ALL DACs
CODEn Command
The CODEn command updates the CODE register contents for the selected DAC(s). Changes to the CODE register
content based on this command will not affect DAC outputs directly unless the latch has been configured to be transparent (see the CONFIG command). In order to update CODE register content of all DACs, use the CODEn command
with DAC selection = 1XX = all DACs. The CODEn command supports the multibyte protocol. See Table 3 and Table 5.
Table 5. CODEn (000) Command Format
0
M
Reserved
Multibyte
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
0
0
CODEn
Command
A2
A1
A0 D11 D10 D9
Dac Address
D7
D6
D5
B8
B7
B6
B5
B4
B3
B2
B1
B0
D4
D3
D2
D1
D0
X
X
X
X
Code Register Data
[3:0]
Code Register Data [11:4]
0
Data Default Value ➝
Command Byte
D8
0
0
0
0
0
0
0
0
0
Data High Byte
0
0
Don’t Care
X
X
X
X
Data Low Byte
LOADn Command
The LOADn command (B[23:20] = 0001) updates the DAC register content for the selected DAC(s) by uploading the
current contents of the CODE register. The LOADn command can be used with DAC SELECTION = 1XX = ALL DACs
to issue a software load for all DACs, which does not alter the existing content of any CODE register (unlike CODEn_
LOAD_ALL command). See Table 3 and Table 6. The LOADn command supports the multibyte protocol.
Table 6. LOADn (001) Command Format
0
M
Reserved
Multibyte
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
0
LOADn
Command
1
A2
A1
A0
DAC Address
Command Byte
X
X
X
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
Don’t Care
Don’t Care
Data High Byte
Data Low Byte
��������������������������������������������������������������� Maxim Integrated Products 24
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
CODEn_LOAD_ALL Command
The CODEn_LOAD_ALL command updates the CODE register contents for the selected DAC(s) as well as the DAC
register content of all DACs. Channels for which the CODE register content has not been modified since the last load
to DAC register will not be updated to reduce digital crosstalk. The CODEn_LOAD_ALL command by definition will
modify at least one CODE register. To avoid this, use the LOADn command with DAC SELECTION = ALL DACs. The
CODEn_LOAD_ALL command supports the multibyte protocol. See Table 3 and Table 7.
Table 7. CODEn_LOAD_ALL (010) Command Format
0
M
Reserved
Multibyte
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
A2
A1
A0 D11 D10 D9
CODEn_ LOAD_
DAC Address
ALL Command
D7
D6
D5
B8
B7
B6
B5
B4
B3
B2
B1
B0
D4
D3
D2
D1
D0
X
X
X
X
Code Register Data
[3:0]
Code Register Data[11:4]
0
Data Default Value ➝
Command Byte
D8
0
0
0
0
0
0
0
0
0
0
Data High Byte
0
Don’t Care
X
X
X
X
Data Low Byte
CODEn_LOADn Command
The CODEn_LOADn command updates the CODE register contents for the selected DAC(s) as well as the DAC register
content of the selected DAC(s). Channels for which the CODE register content have not been modified since the last
load to DAC register will not be updated to reduce digital crosstalk. See Table 3 and Table 8.
Table 8. CODEn_LOADn (011) Command Format
0
M
Reserved
Multibyte
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
CODEn_LOADn
Command
A2
A1
A0 D11 D10 D9
DAC Address
Data Default Value ➝
Command Byte
D8
D7
D6
D5
B8
B7
B6
B5
B4
B3
B2
B1
B0
D4
D3
D2
D1
D0
X
X
X
X
Code Register Data
[3:0]
Code Register Data [11:4]
0
0
0
0
0
Data High Byte
0
0
0
0
0
0
0
Don’t Care
X
X
X
X
Data Low Byte
��������������������������������������������������������������� Maxim Integrated Products 25
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
POWER Command
internal resistors or set to high impedance. See Table 9
for the selectable internal resistor values in power-down
mode. In STANDBY mode, the DAC register retains its
value so that the output is restored when the device powers up. The serial interface remains active in power-down
mode.
The MAX5816 features a software-controlled powermode (POWER) command. The POWER command
updates the power-mode settings of the selected DACs
while the power settings of the remaining of the DACs
remain unchanged. The new power setting is determined
by bits B[5:4] while the affected DAC(s) are selected by
bits B[3:0]. If all DACs are powered down, the device
enters a STANDBY mode.
In powered down mode, the internal reference can be
powered down or it can be set to remain powered-on
for external use in STANDBY mode, parts using external
reference do not load the REF. See Table 9.
In power-down, the output is disconnected from the
buffer and is grounded when one of the two selectable
Table 9. POWER (100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
X
Don’t Care
Reserved
0
1
0
0
X
POWER
Command
X
X
X
X
X
X
Don’t Care
X
X
X
B8
B7
B6
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Data High Byte
SW_RESET and SW_CLEAR Command
The SW_RESET and SW_CLEAR commands provide
a means of issuing a software reset or software clear
operation. Set B0 = 0 to issue a software clear operation
B4
B3
B2
B1
B0
D
C
B
A
Power
Mode:
00 =
Normal
Don’t Care mode
01 = 1kI
10 =
100kI
11 = Hi-Z
Don’t Care
Data Default Value ➝
Command Byte
B5
PD1 PD0
DAC Selection
0
1
1
1
1
Data Low Byte
to return all CODE and DAC registers to the zero-scale
value. Set B0 = 1 to reset all CODE, DAC, and configuration registers to their default values. See Table 10.
Table 10. SW_RESET (101) Command Format
X
Don’t Care
1
0
1
SW_RESET or
SW_CLEAR
Command
X
X
X
X
X
X
Don’t Care
Data Default Value ➝
Command Byte
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
R0
X
X
Don’t Care
X
X
X
X
X
Data High Byte
0 = Clear
1= Reset
0
Reserved
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
Don’t Care
X
X
X
X
X
X
X
X
1
Data Low Byte
��������������������������������������������������������������� Maxim Integrated Products 26
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
CONFIG Command
The CONFIG command allows independent configurations of the DAC. In normal mode (0), the DAC latch is operational
and responds to LOAD commands. In transparent mode (1), the DAC latch is transparent and CODE register contents
are supplied directly to the DAC outputs. See Table 11.
Table 11. CONFIG Command Format
0
X
Reserved
Don’t Care
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
1
1
0
X
CONFIG
Command
X
X
X
X
X
Don’t Care
Data Default Value ➝
X
D
C
B
B8
B7
B6
B5
B4
B3
B2
B1
B0
A
X
X
X
X
D
C
B
A
Don’t Care
X
X
X
Command Byte
X
DAC Latch Mode
0 = Operational
1 = Transparent
Don’t Care
X
X
X
X
X
X
X
Data High Byte
X
0
0
0
0
Data Low Byte
REF Command
The REF command updates the global reference setting used for all DAC channels. Set B[1:0] = 00 to use an external
reference for the DACs or set B[1:0] to 01, 10, or 11 to select either the 2.500V, 2.048V, or 4.096V internal reference,
respectively.
If RF2 (B2 = 0) is set to zero (default) in the REF command, the reference will be powered down any time all DAC channels are powered down (in STANDBY mode). If RF2 is set to one, the reference will remain powered even if all DAC
channels are powered down, allowing continued operation of external circuitry. In this mode the 1µA shutdown state is
not available. See Table 12.
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
X
Don’t Care
Reserved
0
1
1
1
X
REF Command
X
X
X
X
Don’t Care
Data Default Value ➝
Command Byte
X
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
X
X
X
X
X
X
RF2
RF1 RF0
0 = Default
1 = Always On
Table 12. REF Command Format
REF
Mode:
00 = Ext
01 =
2.500V
10 =
2.048V
11 =
4.096V
Don’t Care
X
X
X
X
X
Data High Byte
Don’t Care
X
X
X
X
X
X
X
X
0
0
B0
0
Data Low Byte
��������������������������������������������������������������� Maxim Integrated Products 27
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Applications Information
Power-On Reset (POR)
When power is applied to VDD, the DAC output is set to
zero scale. To optimize DAC linearity, wait until the supplies have settled and the internal setup and calibration
sequence completes (200Fs, typ). Note all commands
issued during the period will be ignored.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height
and the ideal value of 1 LSB. If the magnitude of the
DNL P 1 LSB, the DAC guarantees no missing codes and
is monotonic. If the magnitude of the DNL R 1 LSB, the
DAC output may still be monotonic.
Offset Error
Power Supplies and
Bypassing Considerations
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified
is at or near the zero-scale point of the transfer function.
Layout Considerations
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve, after
nullifying the offset error. This error alters the slope of the
transfer function and corresponds to the same percentage
error in each step.
Bypass VDD with high-quality ceramic capacitors to
a low-impedance ground as close as possible to the
device. Minimize lead lengths to reduce lead inductance.
Connect the GND to the analog ground plane.
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for the
DAC system. Refer remote DAC loads to this system ground
for the best possible performance. Use proper grounding
techniques, such as a multilayer board with a low-inductance
ground plane, or star connect all ground return paths back
to the MAX5816 GND. Carefully layout the traces between
channels to reduce AC cross-coupling. Do not use wirewrapped boards and sockets. Use shielding to minimize
noise immunity. Do not run analog and digital signals parallel
to one another, especially clock signals. Avoid routing digital
lines underneath the MAX5816 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Gain Error
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
��������������������������������������������������������������� Maxim Integrated Products 28
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Detailed Functional Diagram
VDD
REF
100kI RIN
MAX5816
INTERNAL / EXTERNAL REFERENCE (USER OPTION)
CODE
REGISTER
A
CODE
CLEAR/
RESET
DAC
LATCH
A
OUTA
BUFFER A
CLEAR /
RESET
LOAD
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
CODE
REGISTER
B
12-BIT
DAC A
DAC
LATCH
B
12-BIT
DAC B
OUTB
BUFFER B
SCL
SDA
CODE
CLEAR/
RESET
CLEAR /
RESET
LOAD
1kI
POWER-DOWN
DAC CONTROL LOGIC
ADDR
100kI
I2C SERIAL
INTERFACE
CODE
REGISTER
C
CODE
CLEAR/
RESET
DAC
LATCH
C
12-BIT
DAC C
CLEAR /
RESET
LOAD
OUTC
BUFFER C
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
POR
CODE
REGISTER
D
CODE
CLEAR/
RESET
DAC
LATCH
D
LOAD
DAC CONTROL LOGIC
12-BIT
DAC D
OUTD
BUFFER D
CLEAR /
RESET
100kI
1kI
POWER-DOWN
GND
��������������������������������������������������������������� Maxim Integrated Products 29
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
POWER SUPPLY
(2.7V TO 5.5V)
100nF
100µF
4.7µF
RPU =
5kI
VDD
OUT
DAC
SDA
MICROCONTROLLER
SCL
ADDR
MAX5816
REF
R1
R2
R1 = R2
GND
Figure 10. Bipolar Operating Circuit
Typical Operating Circuit
100nF
4.7µF
RPU = 5kI
RPU = 5kI
100µF
VDD
OUT_
DAC
SDA
MICROCONTROLLER
SCL
ADDR
MAX5816
REF
GND
NOTE: UNIPOLAR OPERATION (ONE CHANNEL SHOWN)
��������������������������������������������������������������� Maxim Integrated Products 30
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Ordering Information
PART
MAX5816ATB+T
PIN-PACKAGE
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
10 TDFN-EP*
12
10 (typical)
Note: The device is specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)–free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
T1033+1
21-0137
90-0003
��������������������������������������������������������������� Maxim Integrated Products 31
MAX5816
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012
Maxim Integrated Products 32
Maxim is a registered trademark of Maxim Integrated Products, Inc.