Freescale Semiconductor, Inc. HYBRID MCU/DSP 56858 120 MIPS Hybrid Processor TARGET APPLICATIONS Freescale Semiconductor, Inc... • • • • • • • Full duplex feature phones IP phones Client-side IP applications IADs Voice and audio processing Voice recognition and command General purpose devices BENEFITS • Supports multiple processor connections • Flexible 6-Channel Direct Memory Access (DMA) allows both internal and external memory transfers with almost no CPU interruption • 16-bit quad timer module (with four external pins) that allows capture/compare functionality, and can be cascaded • Serial peripheral interface with master and slave mode supporting connection to other processors or serial memory devices • Quad timer module can also be used for simple digital-to-analog conversion functionality • Two enhanced synchronous serial interfaces with three transmitters per module provide support for 5.1 channel surround sound for audio applications • Easy to program with flexible application development tools • Enhanced synchronous serial interface with enhanced network and audio modes The 56858 offers a rich feature set and on-chip memory interface. It includes external memory expansion with up to 2M words of program or up to 8M words of data addressing space, and is available in both 144 LQFP and 144 MBGA packages. The 56858 includes 40K words of on-chip program SRAM and 24K words of on-chip data SRAM. With two enhanced serial synchronous serial interfaces (ESSIs), this device can provide outputs for 5.1-channel surround sound. The 56858 is ideal for client-side telecom/datacom applications requiring up to four channels, including IP phones. This device can be designed into multi-processor systems to provide internet audio and speech processing functionalities and can provide a stand-alone device for internet audio. COP/Watchdog • 120 MIPS at 120MHz • Serial Peripheral Interface (SPI) • 40K x 16-bit Program SRAM • 8-bit parallel Host Interface • 24K x 16-bit Data SRAM • General purpose 16-bit Quad Timer • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or up to 8M data memory • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Chip Select Logic for glueless interface to ROM and SRAM • Computer Operating Properly (COP)/Watchdog Timer • Six independent channels of DMA • Time of Day (TOD) • Two Enhanced Synchronous Serial Interfaces (ESSI) • 144-pin LQFP and 144 MAPBGA packages • Two Serial Communication Interfaces (SCI) • Up to 47 GPIO • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs RAM 40K x 16 SPI 6-channel DMA Boot ROM 1K x 16 (2) SCI (2) ESSI Up to 48 GPIO 16-Bit Quad Timer 56858 16-BIT DIGITAL SIGNAL PROCESSORS ENERGY INFORMATION Program Memory Ext Memory IF Prog Chip Selects • Time of Day for applications requiring clock display 56800E Core 120 MIPS Time of Day Data Memory PLL RAM 24K x 16 JTAG/EOnCE 8-Bit Host For More Information On This Product, Go to: www.freescale.com • Wait and Stop modes available Freescale Semiconductor, Inc. 56800E CORE FEATURES HYBRID MCU/DSP The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers, enabling rapid development of optimized control applications. Features of the 56800E core include: 56858 PRODUCT DOCUMENTATION DSP56800E Reference Manual Freescale Semiconductor, Inc... DSP5685x User’s Manual DSP56858 Technical Data Sheet Detailed description of the 56800E architecture, 16-bit DSP core processor and the instruction set • Efficient 16-bit hybrid controller engine with dual Harvard architecture • Four internal data buses and one external data bus Order Number: DSP56800ERM/D • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Instruction set supports both DSP and controller functions Detailed description of memory, peripherals, and interfaces of the 56853, 56854, 56855, 56857, and 56858 • Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) • Four hardware interrupt levels Order Number: DSP5685xUM/D • Four 36-bit accumulators, including extension bits • Controller-style addressing modes and instructions for compact code • 16-bit bidirectional shifter • Efficient C compiler and local variable support Electrical and timing specifications, pin descriptions, and package descriptions • Hardware DO and REP loops • Software subroutine and interrupt stack with depth limited only by memory Summary description and block diagram of the core, memory, peripherals and interfaces • Three internal address buses and one external address bus • JTAG/Enhanced OnCE debug programming interface Order Number: DSP56858PB/D 56858 MEMORY FEATURES Order Number: DSP56858/D DSP56858 Product Brief • Parallel instruction set with unique addressing modes • Five software interrupt levels • Harvard architecture permits up to three simultaneous accesses to program and data memory “BEST IN CLASS” DEVELOPMENT ENVIRONMENT • On-Chip Memory – 40K x 16-bit Program RAM • The Software Development Kit (SDK) provides fully debugged peripheral drivers, libraries and interfaces that allow a programmer to create his own unique C application code independent of component architecture. • The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. – 24K x 16-bit Data RAM • Off-Chip Memory Expansion (EMI) – Access up to 2M words of program or up to 8M data memory (using chip selects) – Chip Select Logic for glueless interface to ROM and SRAM – 1K x 16-bit Boot ROM 56858 PERIPHERAL CIRCUIT FEATURES • General Purpose 16-bit Quad Timer* • Six independent channels of DMA • Two Serial Communication Interfaces (SCI)* • 8-bit parallel Host Interface* • Serial Peripheral Interface (SPI) Port* • 144-pin LQFP and 144 MBGA packages • Two Enhanced Synchronous Serial Interface (ESSI) modules* • Up to 47 GPIO • Computer Operating Properly (COP)/Watchdog Timer * Each peripheral I/O can be used alternately as a General Purpose I/O • Time of Day (TOD) • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging ORDERING INFORMATION PART SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER DSP56858 DSP56858 1.8V, 3.3V 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) MAP Ball Grid Array (MAPBGA) 144 144 120 120 DSP56858FV120 DSP56858VF120 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56858PB/D REV 4 For More Information On This Product, Go to: www.freescale.com