LMC835 Digital Controlled Graphic Equalizer General Description Features The LMC835 is a monolithic, digitally-controlled graphic equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists of a Logic section and a Signal Path section made of analog switches and thin-film silicon-chromium resistor networks. The LMC835 is used with external resonator circuits to make a stereo equalizer with seven bands, g 12 dB or g 6 dB gain range and 25 steps each. Only three digital inputs are needed to control the equalization. The LMC835 makes it easy to build a mP-controlled equalizer. The signal path is designed for very low noise and distortion, resulting in very high performance, compatible with PCM audio. Y Y Y Y Y Y No volume controls required Three-wire interface 14 bands, 25 steps each g 12 dB or g 6 dB gain ranges Low noise and distortion TTL, CMOS logic compatible Applications Y Y Y Y Y Y Y Hi-Fi equalizer Receiver Car stereo Musical instrument Tape equalization Mixer Volume controller Connection Diagrams Molded Chip Carrier Package Dual-In-Line Package TL/H/6753 – 26 Top View Order Number LMC835V See NS Package V28A TL/H/6753 – 1 Top View Order Number LMC835N See NS Package N28B C1995 National Semiconductor Corporation TL/H/6753 RRD-B30M75/Printed in U. S. A. LMC835 Digital Controlled Graphic Equalizer February 1995 TL/H/6753 – 2 Block Diagram 2 Absolute Maximum Ratings Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Digital Ground (Pin 13) VSS to VDD Digital Input (Pins 14, 15, 16) Analog Input (Pins 1, 2, 3, 4, 25, 26, 27) (Note 1) VSS to VDD Supply Voltage, VDDbVSS Supply Voltage, VDDbVSS 18V Allowable Input Voltage (Note 1) VSSb0.3V to VDD a 0.3V b 60§ C to a 150§ C Storage Temperature, Tstg a 260§ C Lead Temperature (Soldering, 10 sec), N Pkg Lead Temperature, V Pkg a 215§ C Vapor Phase (60 sec) a 220§ C Infrared (15 sec) 5V to 16V VSS to VDD Operating Temperature, Topr b 40§ C to a 85§ C Electrical Characteristics (Note 2) VDD e 7.5V, VSS eb7.5V, A.GND e 0V LOGIC SECTION Symbol Parameter Test Conditions Typ Tested Limit (Note 3) Design Limit (Note 4) Unit (Limit) 0.01 0.01 1.3 0.9 0.5 0.5 5 5 0.5 0.5 5 5 mA (Max) mA (Max) mA (Max) mA (Max) IDDL ISSL IDDH ISSH Supply Current Pins 14, 15, 16 are 0V Pins 14, 15, 16 are 0V Pins 14, 15, 16 are 5V Pins 14, 15, 16 are 5V VIH High-Level Input Voltage @ Pins 14, 15, 16 1.8 2.3 2.5 V (Min) VIL Low-Level Input Voltage @ Pins 14, 15, 16 0.9 0.6 0.4 V (Max) fo Clock Frequency @ Pin 14 2000 500 500 kHz (Max) tw(STB) Width of STB Input See Figure 1 0.25 1 1 ms (Min) tsetup Data Setup Time See Figure 1 0.25 1 1 ms (Min) thold Data Hold Time See Figure 1 0.25 1 1 ms (Min) tcs Delay from Rising Edge of CLOCK to STB See Figure 1 0.25 1 1 ms (Min) IIN Input Current @ Pins 14, 15, 16 0VkVINk5V g 0.01 g1 CIN Input Capacitance @ Pins 14, 15, 16 f e 1 MHz 5 mA (Max) pF Note 1: Pins 2, 3 and 26 have a maximum input voltage range of g 22V for the typical application shown in Figure 7 . Note 2: Bold numbers apply at temperature extremes. All other numbers apply at TA e 25§ C, VDD e 7.5V, VSS eb 7.5V,D.GND e A.GND e 0V as shown in the test circuit, Figures 3 and 4 . Note 3: Guaranteed and 100% production tested. Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels. Timing Diagram TL/H/6753 – 3 Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time. FIGURE 1 3 Electrical Characteristics (Note 2) VDD e 7.5V, VSS eb7.5V, D.GND e A.GND e 0V SIGNAL PATH SECTION Symbol EA THD Parameter Gain Error Total Harmonic Distortion Test Conditions AV e 0 dB @ g 12 dB Range AV e 0 dB @ g 6 dB Range AV e g 1 dB @ g dB Range (R5b or R5c is ON) AV e g 2 dB @ g 12 dB Range (R4b or R4c is ON) AV e g 3 dB @ g 12 dB Range (R3b or R3c is ON) AV e g 4 dB @ g 12 dB Range (R2b or R2c is ON) AV e g 5 dB @ g 12 dB Range (R1b or R1c is ON) AV e g 9 dB @ g 12 dB Range (R0b or R0c is ON) AV e 0 dB @ g 12 dB Range VIN e 4Vrms, f e 1 kHz AV e 12 dB @ g 12 dB Range VIN e 1Vrms, f e 1 kHz VIN e 1Vrms, f e 20 kHz AV eb12 dB @ g 12 dB Range VIN e 4Vrms, f e 1 kHz VIN e 4Vrms, f e 20 kHz Typ Tested Limit (Note 3) Design Limit (Note 4) Unit (Limit) 0.1 0.1 0.1 0.5 1 0.5 0.5 1 0.6 dB (Max) dB (Max) dB (Max) 0.1 0.5 0.6 dB (Max) 0.1 0.5 0.6 dB (Max) 0.1 0.5 0.7 dB (Max) 0.1 0.5 0.7 dB (Max) 0.2 1 1.3 dB (Max) 0.0015 % 0.01 0.1 0.1 0.5 % (Max) % (Max) 0.01 0.1 0.1 0.5 % (Max) % (Max) 5.1 VO Max Maximum Output Voltage AV e 0 dB @ g 12 dB Range THD k1%, f e 1 kHz 5.5 S/N Signal to Noise Ratio AV e 0 dB @ g 12 dB Range Vref e 1 Vrms AV e 12 dB @ g 12 dB Range Vref e 1Vrms AV eb12 dB @ g 12 dB Range Vref e 1Vrms 114 dB 106 dB 116 dB ILEAK Leakage Current AV e 0 dB @ g 12 dB Range (All internal switches are OFF) Pin 2 a 3, Pin 26 Pin 5 E Pin 11, Pin 18 E Pin 24 500 50 5 Vrms (Min) nA (Max) nA (Max) Note 2; Boldface numbers apply at temperature extremes. All other numbers apply at TA e 25§ C, VDD e 7.5V, VSS eb 7.5V, D.GND e A.GND e 0V as shown in the test circuit, Figures 3 and 4 . Note 3: Guaranteed and 100% production tested. Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels. Timing Diagrams TL/H/6753 – 4 Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time. FIGURE 2 4 Truth Tables DATA I (Band Selection) D7 D6 D5 D4 D3 D2 D1 D0 H H H H H H H H H H H H H H H H X X X X X X X X X X X X X X X X L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H H X L H Valid Binary Input H X H L Valid Binary Input H X H H Valid Binary Input u u u u j k l m w x Band Code (Ch A: Band 1 E 7, Ch B: Band 8 E 14) Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch A A A A A A A A A A A A A A A A g 12 dB Range, Ch B g 12 dB Range, No Band Selection g 12 dB Range, Ch B g 12 dB Range, Band 1 g 12 dB Range, Ch B g 12 dB Range, Band 2 g 12 dB Range, Ch B g 12 dB Range, Band 3 g 12 dB Range, Ch B g 12 dB Range, Band 4 g 12 dB Range, Ch B g 12 dB Range, Band 5 g 12 dB Range, Ch B g 12 dB Range, Band 6 g 12 dB Range, Ch B g 12 dB Range, Band 7 g 12 dB Range, Ch B g 12 dB Range, Band 8 g 12 dB Range, Ch B g 12 dB Range, Band 9 g 12 dB Range, Ch B g 12 dB Range, Band 10 g 12 dB Range, Ch B g 12 dB Range, Band 11 g 12 dB Range, Ch B g 12 dB Range, Band 12 g 12 dB Range, Ch B g 12 dB Range, Band 13 g 12 dB Range, Ch B g 12 dB Range, Band 14 g 12 dB Range, Ch B g 12 dB Range, No Band Selection Ch A g 12 dB Range, Ch B g 6 dB Range, Band 1 E 14 Ch A g 6 dB Range, Ch B g 12 dB Range, Band 1 E 14 Ch A g 6 dB Range, Ch B g 6 dB Range, Band 1 E 14 j DATA 1 k Don’t Care l Ch A g 6 dB/ g 12 dB Range m Ch B g 6 dB/ g 12 dB Range DATA II (Gain Selection) Flat This is the gain if the g 12 dB range is selected by DATA I. If the g 6 dB range is selected, then the values shown must be approximately halved. See the characteristics curves for more exact data. $ 1 dB Boost 2 dB Boost 3 dB Boost 4 dB Boost 5 dB Boost 6 dB Boost 7 dB Boost 8 dB Boost 9 dB Boost 10 dB Boost 11 dB Boost 12 dB Boost 1 dB E 12 dB Cut n DATA II o Boost/Cut 5 D7 D6 D5 D4 D3 D2 D1 D0 L L L L L L L L L L L L L L X H H H H H H H H H H H H L L H L L L L L H L L H H H L L H L L L H L H L L L L L L L H L L L H L L H H H L L L L H L L L H L L H H L L L L L H H H H L L L H L L L L L L L L L H H H H u u n o Valid Above Input w Gain Code x Test Circuits TL/H/6753 – 5 FIGURE 3. Test Circuit for AC Measurement TL/H/6753 – 6 FIGURE 4. Test Circuit for Leakage Current Measurement 6 Test Circuits (Continued) TL/H/6753 – 7 FIGURE 5. I to V Converter TL/H/6753 – 8 FIGURE 6. Simple Word Generator Typical Performance Characteristics Supply Current vs Supply Voltage Supply Current vs Temperature Input Capacitance vs Input Voltage TL/H/6753 – 9 7 Typical Performance Characteristics (Continued) Maximum Output Voltage vs Supply Voltage Maximum Output Voltage vs Temperature Nominal Resistor vs Temperature Distortion vs Frequency @ g 12 dB Range Distortion vs Frequency @ g 6 dB Range Distortion vs Output Voltage @ g 12 dB Range Distortion vs Output Voltage @ g 6 dB Range Gain vs Frequency @ g 12 dB Range (Boost) Gain vs Frequency @ g 12 dB Range (Cut) Gain vs Frequency @ g 6 dB Range (Boost) Gain vs Frequency @ g 6 dB Range (Cut) Gain vs Temperature TL/H/6753 – 10 8 Typical Applications TL/H/6753 – 11 FIGURE 7. Stereo 7-Band Equalizer TABLE I: Tuned Circuit Elements Q0 e 3.5, Q12dB e 1.05 L0 e CL RL R0 Z1 fo (Hz) CO (F) CL (F) RL (X) RO (X) Z1 Z2 Z3 Z4 Z5 Z6 Z7 63 160 400 1k 2.5k 6.3k 16k 1m 0.47m 0.15m 0.068m 0.022m 0.01m 0.0047m 0.1m 0.033m 0.015m 0.0068m 0.0033m 0.0015m 680p 100k 100k 100k 82k 82k 62k 47k 680 680 680 680 680 680 680 f0 e 1 2q0L0C0 Q0 e 0C R L0 2 0 0 R0 Q 0 Q12 dB e R0 a 1590 TL/H/6753 – 12 FIGURE 8. Tuned Circuit for Stereo 7-Band Equalizer (Figure 7 ) 9 Typical Applications (Continued) Performance Characteristics (Circuit of Figure 7 ) LMC835 Gain vs Frequency LMC835 Gain vs Frequency @ g 12 dB Range @ g 12 dB Range (All Boost or Cut) (1 kHz Boost or Cut) LMC835 Gain vs Frequency @ g 6 dB Range (1 kHz Boost or Cut) LMC835 Gain vs Frequency @ g 6 dB Range (All Boost or Cut) TL/H/6753 – 13 TL/H/6753 – 14 FIGURE 9. 12-Band Equalizer 10 Typical Applications (Continued) TABLE II. Tuned Circuit Elements Q0 e 4.7, Q12 dB e 1.4 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 fo (Hz) Co (F) CL (F) RL (X) Ro (X) 16 31.5 63 125 250 500 1k 2k 4k 8k 16k 32k 3.3m 15m 1m 0.39m 0.22m 0.1m 0.047m 0.022m 0.01m 0.0068m 0.0033m 0.0015m 0.47m 0.22m 0.1m 0.068m 0.033m 0.015m 0.01m 0.0047m 0.0022m 0.001m 680p 470p 100k 110k 100k 91k 82k 100k 82k 91k 110k 82k 62k 68k 680 680 680 680 680 680 680 680 680 680 680 510 L 0 e C L RL R0 f0 e 1 2q0L0C0 Q0 e 0C R L0 2 0 0 R 0Q 0 Q12 dB e R0 a 1590 TL/H/6753 – 15 FIGURE 10. Tuned Circuit for 12-Band Equalizer (Figure 9 ) Performance Characteristics (Circuit of Figure 9) 12 Band Equalizer Application LMC835 Gain vs Frequency @ g 6 dB Range (All Boost or Cut) LMC835 12 Band E.Q. Application Gain vs Frequency @ g 12 dB Range (1 kHz Boost or Cut) 12 Band Equalizer Application LMC835 Gain vs Frequency @ g 12 dB Range (All Boost or Cut) LMC835 12 Band E.Q. Application Gain vs Frequency @ g 6dB Range (1 kHz Boost or Cut) TL/H/6753 – 16 11 Typical Applications (Continued) Lo e CL, RL, RO Fo e 1 2q0LOCO QO e 0CORO2 Q12 dB e ROQO RO a 15§ C TL/H/6753 – 25 TL/H/6753 – 17 Va The output is used to bias the gyrators 2 FIGURE 11. Single Supply Stereo Equalizer 12 Typical Applications (Continued) TL/H/6753 – 18 TL/H/6753 – 19 FIGURE 12. Stereo 7-Input/1-Output Mixers (THD is not as low as equalizer circuit) FIGURE 13. Stereo Volume Control, Very Low THD TL/H/6753 – 20 FIGURE 14. LMC835-COP404L CPU Interface 13 Typical Applications (Continued) Sample Subroutine Program for Figure 14 , LMC835-COP404L CPU Interface HEX CODE 3F 05 22 335F 4F 05 07 05 4F 05 07 32 4F 335D 335B LABEL LMC835: SEND 4E 43 48 80 3C 3D 3E 3F MNEMONICS LBI 3F LD SC OGI XAS LD XDS LD XAS LD XDS RC XAS OGJ 13 OGI 11 CBA AISC RET JP RAM ADDRESS DATA DATA DATA DATA 3 COMMENTS ;POINT TO RAMADDRESS 3F ;RAMDATA TO A ; SET CARRY ;SET PORT G4 1111, OPEN THE AND GATES ;SWAP A AND SIO, CLOCK START ;RAMDATA TO A, MAKE SURE A 4 DATA ;SWAP A AND RAMDATA, RAMADDRESS4RAMADDRESS11 ;RAMDATA TO A ;SWAP A AND SIO ;RAMDATA TO A, MAKE SURE A4NEWDATA ;SWAP A AND RAMDATA, RAMADDRESS4RAMADDRESS11 ;RESET CARRY ;SWAP A AND SIO, CLOCK STOP ;SET PORT G41101, MAKE STROBE LOW ;SET PORT G41011, MAKE STROBE HIGH, CLOSE THE GATES ;BD TO A ;RAMADDRESSk3C THEN RETURN SEND COMMENTS ;GAIN DATA D41D7 ;GAIN DATA D01D3 ;BAND DATA D41D7 ;BAND DATA D01D3 Application Hints SIMPLE WORD GENERATOR (Figure 6) Circuit operation revolves around an MM74HC165 parallelin/serial-out shift register. Data bits D0 through D7 are applied to the parallel of the MM74HC165 from 8 toggle switches. The bits are shifted out to the DATA input of the LMC835 in sync with the clock. When all data bits have been loaded, CLOCK is inhibited and a STROBE pulse is generated: this sequence is initiated by a START pulse. SWITCHING NOISE The LMC835 uses CMOS analog switches that have small leakages (less than 50 nA). When a band is selected for flat gain, all the switches in that band are open and the resonator circuit is not connected to the LMC835 resistor network. It is only in the flat mode that the small leakage currents can cause problems. The input to the resonator circuit is usually a capacitor and the leakage currents will slowly charge up this capacitor to a large voltage if there is no resistive path to limit it. When the band is set to any value other than flat, the charge on the capacitor will be discharged by the resistor network and there will be a transient at the output. To limit the size of this transient, RLEAK is necessary. LMC835-COP404L CPU INTERFACE (Refer to Figure 14 ) The diagram shows AND gates between the COP and the LMC835. These permit G2 to inhibit the CLOCK and DATA lines (SK and SO) during a STROBE (G1) pulse. This function may also be implemented in software. As shown in Figure 2 , the data groups are shifted in D0 first. Data is loaded on positive clock edges. HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE CURRENT (Refer to Figures 7 and 8 ) To avoid switching noise due to leakage currents when changing the gain, it is recommended to put RLEAK e 100 kX between Pin 3 and Pin 5Ð11 each, Pin 26 and Pin 12Ð 24 each. The resistor limits the voltage that the capacitor can charge to, with minimal effects on the equalization. The frequency response change due to RLEAK are shown in Figure 15 . The gain error is only 0.2 dB and Q error is only 5% at 12 dB boost or cut. POWER SUPPLIES These applications show LM317/337 regulators for the g 7.5V supplies for the LMC835. Since the latter draws only 5 mA max., 1k series dropping resistors from the g 15V op amp supply and a pair of 7.5V zeners and bypass caps will also suffice. 14 Application Hints (Continued) MODEL RESULT TL/H/6753 – 21 TL/H/6753 – 22 FIGURE 15. Effect of RLEAK REDUCING EXTERNAL COMPONENTS The typical application shown in Figure 7 is switching noise free. The DC-coupled circuit in Figure 16 is also switching noise free, except at 12 dB/6 dB switch turn ON/OFF. This switching noise is caused by the Ibias and Voffset of the op amps. Selecting a low Ibias and Voffset op amp can minimize the switching noise due to the 12 dB/6 dB switch. The DCcoupled application can also eliminate the RF e 100k resistors with only a 0.5 dB gain error at 12 dB boost or cut. AC COUPLING DC COUPLING TL/H/6753 – 24 TL/H/6753 – 23 FIGURE 16. Reducing External Components 15 16 Physical Dimensions inches (millimeters) Order Number LMC835N NS Package N28B 17 LMC835 Digital Controlled Graphic Equalizer Physical Dimensions inches (millimeters) (Continued) Order Number LMC835V NS Package V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.