FSYE33A0D, FSYE33A0R TM Data Sheet Radiation Hardened, SEGR Resistant N-Channel Power MOSFETs The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100 krads of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. September 2000 • 5A, 400V, rDS(ON) = 1.2Ω • Total Dose - Meets Pre-RAD Specifications to 100 krad(Si) • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias • Dose Rate - Typically Survives 3E9 rad (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM • Photo Current - 6nA Per-rad(Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 3E12 Neutrons/cm2 - Usable to 3E13 Neutrons/cm2 Symbol D G SCREENING LEVEL Packaging PART NUMBER/BRAND 10K Commercial FSYE33A0D1 100K TXV FSYE33A0R3 100K Space FSYE33A0R4 1 S SMD.5 Ordering Information RAD LEVEL 4908 Features Reliability screening is available as either commercial, TXV equivalent of MIL-PRF-19500, or Space equivalent of MIL-PRF-19500. Contact Intersil for any desired deviations from the data sheet. Formerly available as type TA17699W. File Number CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 FSYE33A0D, FSYE33A0R Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSYE33A0D, FSYE33A0R UNITS 400 400 V V 5 3 15 ±20 A A A V 75 30 0.60 15 5 15 -55 to 150 300 W W W/ oC A A A oC oC Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL Drain to Source Breakdown Voltage Gate Threshold Voltage BVDSS VGS(TH) Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current IGSS Drain to Source On-State Voltage Drain to Source On Resistance VDS(ON) rDS(ON)12 Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA VDS = 320V, VGS = 0V VGS = ±20V TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC VGS = 12V, ID = 5A ID = 3A, VGS = 12V TC = 25oC TC = 125oC VDD = 200V, ID = 5A, RL = 40Ω, VGS = 12V, RGS = 7.5Ω td(OFF) Fall Time tf Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 12V Qg(12) VGS = 0V to 12V Threshold Gate Charge Qg(TH) VGS = 0V to 2V VDD = 200V, ID = 5A MIN TYP MAX UNITS 400 - - V - - 5.0 V 1.5 - 4.0 V 0.5 - - V - - 25 µA - - 250 µA - - 100 nA - - 200 nA - - 6.6 V - 1.0 1.2 Ω - - 2.4 Ω - - 20 ns - - 25 ns - - 55 ns - - 25 ns - 55 - nC - 33 36 nC - 2 - nC Gate Charge Source Qgs - 5 7 nC Gate Charge Drain Qgd - 15 18 nC ID = 5A, VDS = 15V - 6 - V VDS = 25V, VGS = 0V, f = 1MHz - 750 - pF - 105 - pF - 26 - pF 1.67 oC/W Plateau Voltage V(PLATEAU) Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Case 2 RθJC - - FSYE33A0D, FSYE33A0R Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage TEST CONDITIONS VSD Reverse Recovery Time MIN TYP MAX UNITS 0.6 - 1.8 V - - 520 ns ISD = 5A trr ISD = 5A, dISD/dt = 100A/µs Electrical Specifications up to 100 krad TC = 25oC, Unless Otherwise Specified MIN MAX Drain to Source Breakdown Volts PARAMETER (Note 3) SYMBOL BVDSS VGS = 0, ID = 1mA TEST CONDITIONS 400 - UNITS V Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA 1.5 4.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±20V, VDS = 0V - 100 nA IDSS µA Zero Gate Leakage (Note 3) VGS = 0, VDS = 320V - 25 Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 12V, ID = 5A - 6.6 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = 12V, ID = 3A - 1.2 Ω NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) Note 4 ENVIRONMENT (NOTE 5) TEST SYMBOL Single Event Effects Safe Operating Area SEESOA ION SPECIES TYPICAL LET (MeV/mg/cm) APPLIED VGS BIAS (V) TYPICAL RANGE (µ) (NOTE 6) MAXIMUM VDS BIAS (V) Ni 26 43 -15 400 Ni 26 43 -20 360 Br 37 36 -5 400 Br 37 36 -10 320 Br 37 36 -15 200 Br 37 36 -20 80 NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43µ LET = 37MeV/mg/cm2, RANGE = 36µ 500 1E-3 LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) VDS (V) 400 300 200 100 TEMP = 25oC -5 ILM = 10A 30A 1E-5 100A 300A 1E-6 1E-7 0 0 1E-4 -10 -15 VGS (V) -20 -25 FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA 3 10 30 100 300 1000 DRAIN SUPPLY (V) FIGURE 2. TYPICAL DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS FSYE33A0D, FSYE33A0R Performance Curves Unless Otherwise Specified (Continued) 7 100 TC = 25oC ID , DRAIN CURRENT (A) 6 ID , DRAIN (A) 5 4 3 2 10 100µs 1 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 0 -50 0 50 0.1 150 100 1 TC , CASE TEMPERATURE (oC) 10ms 10 100 1000 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 PULSE DURATION = 250ms, VGS = 12V, ID = 3A 12V NORMALIZED rDS(ON) 2.0 QG QGS QGD 1.5 1.0 0.5 VG 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) CHARGE FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. TYPICAL NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE NORMALIZED THERMAL RESPONSE (ZθJC) 10 1 0.5 0.1 0.01 0.2 0.1 0.05 0.02 0.01 PDM SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 0.001 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE 4 t1 t2 100 101 FSYE33A0D, FSYE33A0R Performance Curves Unless Otherwise Specified (Continued) IAS , AVALANCHE CURRENT (A) 100 10 STARTING TJ = 25oC STARTING TJ = 150oC 1 IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 0.01 0.1 1 10 tAV , TIME IN AVALANCHE (ms) FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS VDD 50V-150V DUT tP VDD + 50Ω VGS ≤ 20V 0V VDS IAS 50Ω tAV FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS VGS = 12V 10% DUT 10% 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT 5 FIGURE 12. RESISTIVE SWITCHING WAVEFORMS FSYE33A0D, FSYE33A0R Screening Information Screening is performed in accordance with the latest revision in effect of MIL-PRF-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 7) µA Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID ±20% (Note 8) Ω Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANTXV EQUIVALENT JANS EQUIVALENT Unclamped Inductive Switching VGS(PEAK) = 15V, L = 0.1mH; Limit = 15A VGS(PEAK) = 15V, L = 0.1mH; Limit = 15A Thermal Response tH = 10ms; VH = 25V; IH = 1A; LIMIT = 74mV tH = 10ms; VH = 25V; IH = 1A; LIMIT = 74mV Gate Stress VGS = 30V, t = 250µs VGS = 30V, t = 250µs Pind Optional Required Pre Burn-In Tests (Note 9) MIL-PRF-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-PRF-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-PRF-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours MIL-PRF-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-PRF-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours MIL-PRF-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 10% 5% Final Electrical Tests (Note 9) MIL-PRF-19500, Group A, Subgroup 2 MIL-PRF-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Tests PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Safe Operating Area SOA VDS = 200V, t = 10ms 0.43 A Thermal Impedance ∆VSD tH = 100ms; VH = 25V; IH = 1A 165 mV 6 FSYE33A0D, FSYE33A0R Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent Class S - Equivalents 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance A. Certificate of Compliance B. Assembly Flow Chart B. Serialization Records C. Preconditioning - Attributes Data Sheet C. Assembly Flow Chart D. Group A - Attributes Data Sheet D. SEM Photos and Report E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) G. Group D - Attributes Data Sheet - Pre and Post RAD Read and Record Data F. Group A G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Subgroups C1, C2, C3 and C6 Data I. Group D 7 - Attributes Data Sheet - Attributes Data Sheet - Pre and Post Radiation Data FSYE33A0D, FSYE33A0R SMD.5 3 PAD CERAMIC LEADLESS CHIP CARRIER INCHES E SYMBOL D MIN MAX MILLIMETERS MIN MAX NOTES A 0.112 0.124 2.84 3.15 3 b 0.090 0.100 2.28 2.54 - D 0.291 0.301 7.39 7.64 - D1 0.281 0.291 7.13 7.39 - D2 0.070 0.080 1.78 2.03 - E 0.395 0.405 10.03 10.28 - E1 0.220 0.230 5.58 5.84 - E2 0.115 0.125 2.92 3.17 - NOTES: 1. No current JEDEC outline for this package. A 2. Controlling dimension: Inch. 3. Measurement prior to pre-solder coating the mounting pads. 4. Revision 4dated 5-00. E1 E2 2 D2 3 D1 1 b 1 - GATE 2 - SOURCE 3 - DRAIN All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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