ETC NB100LVEP56/D

NB100LVEP56
2.5V / 3.3V / 5VECL Dual
Differential 2:1 Multiplexer
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both ECL and CMOS input voltage levels. Multiple VBB pins are
provided.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input operation, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
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MARKING
DIAGRAMS*
20
20
1
N100
LP56
ALYW
TSSOP-20
DT SUFFIX
CASE 948E
1
• Maximum Input Clock Frequency > 2.5 GHz Typical
• Maximum Input Data Rate > 2.5 Gb/s Typical
24
• 525 ps Typical Propagation Delays
• Low Profile QFN Package
• PECL Mode Operating Range: VCC = 2.375 V to 5.5 V
1
24
N100
LP56
ALYW
1
24 PIN QFN
MN SUFFIX
CASE 485L
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
A
L
Y
W
with VEE = -2.375 V to -5.5 V
• Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
• Q Output Will Default LOW with Inputs Open or at VEE
• Multiple VBB Outputs
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP56DT
Package
Shipping
TSSOP-20
75 Units/Rail
NB100LVEP56DTR2 TSSOP-20 2500 Tape & Reel
NB100LVEP56MN
QFN-24
NB100LVEP56MNR2 QFN-24
 Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 3
1
92 Units/Rail
3000 Tape & Reel
Publication Order Number:
NB100LVEP56/D
NB100LVEP56
Table 1. PIN DESCRIPTION
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
Pin No.
TSSOP
QFN
Name
I/O
Default
State
14,20
3,9,18,19,
20
VCC
-
-
Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation.
11
15,24
VEE
-
-
Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation.
3,8
6,12
VBB0,
VBB1
-
-
ECL Reference Voltage Output
1
4
D0a
ECL Input
Low
Noninverted Differential Data a Input to MUX 0. Internal 75 k to
VEE.
2
5
D0a
ECL Input
High
Inverted Differential Data a Input to MUX 0. Internal 75 k to VEE
and 37 k to VCC.
4
7
D0b
ECL Input
Low
Noninverted Differential Data b Input to MUX 0. Internal 75 k to
VEE.
5
8
D0b
ECL Input
High
Inverted Differential Data b Input to MUX 0. Internal 75 k to VEE
and 37 k to VCC.
6
10
D1a
ECL Input
Low
Noninverted Differential Data a Input to MUX 1. Internal 75 k to
VEE.
7
11
D1a
ECL Input
High
Inverted Differential Data a Input to MUX 1. Internal 75 k to VEE
and 37 k to VCC.
9
13
D1b
ECL Input
Low
Noninverted Differential Data b Input to MUX 1. Internal 75 k to
VEE.
10
14
D1b
ECL Input
High
Inverted Differential Data b Input to MUX 1. Internal 75 k to VEE
and 37 k to VCC.
19
2
Q0
ECL Output
-
Noninverted Differential Output MUX 0. Typically Terminated with
50 to VTT = VCC - 2 V.
18
1
Q0
ECL Output
-
Inverted Differential Output MUX 0. Typically Terminated with
50 to VTT = VCC - 2 V.
13
17
Q1
ECL Output
-
Noninverted Differential Output MUX 1. Typically Terminated with
50 to VTT = VCC - 2 V.
12
16
Q1
ECL Output
-
Inverted Differential Output MUX 1. Typically Terminated with
50 to VTT = VCC - 2 V.
17
23
SEL0
ECL, CMOS
Input
Low
Noninverted Differential Select Input to MUX 0. Internal 75 to
VEE.
16
22
COM_SEL
ECL, CMOS
Input
Low
Noninverted Differential Common Select Input to Both MUX. Internal 75 to VEE.
15
21
SEL1
ECL, CMOS
Input
Low
Noninverted Differential Select Input to MUX 1. Internal 75 to
VEE.
N/A
-
EP
-
Description
Exposed Pad. (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit.
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2
NB100LVEP56
D0a
R1
D0a
R1
1
R2
Q0
Q0
D0b
R1
0
Table 2. TRUTH TABLE
SEL0
R2
R1
D0b
R1
SEL0
SEL1
COM_SEL
Q0, Q0
Q1, Q1
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
COM_SEL
R1
D1a
R1
D1a
R1
SEL1
R1
1
R2
Q1
Q1
D1b
R1
0
VCC
VEE
R2
D1b
R1
COM
VEE SEL0 SEL SEL1 VCC VCC
VCC
Q0
Q0
SEL0
COM_SEL
SEL1
VCC
Q1
Q1
VEE
Figure 1. Logic Diagram
20
19
18
17
16
15
14
13
12
11
24
23
22
21
20
Exposed Pad
(EP)
19
Q0
1
18
VCC
Q0
2
17
Q1
VCC
3
16
Q1
NB100LVEP56
1
2
3
4
5
6
7
8
9
10
D0a
D0a
VBBO
D0b
D0b
D1a
D1a
VBB1
D1b
D1b
NB100LVEP56
D0a
4
15
VEE
D0a
5
14
D1b
VBB0
6
13
D1b
7
8
9
10
11
12
D0b D0b VCC D1a D1a VBB1
Figure 1. TSSOP-20 Lead Pinout (Top View)
Figure 2. QFN-24 Lead Pinout (Top View)
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
(R1)
75 k
Internal Input Pullup Resistor
(R2)
37 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 150 V
> 2 kV
Level 1
UL 94 V-0 @ 0.125 in
354 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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3
NB100LVEP56
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Mode Power Supply
VEE = 0 V
6
V
VEE
Negative Mode Power Supply
VCC = 0 V
-6
V
VI
Positive Mode Input Voltage
Negative Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
JEDEC 51-3 (1S - Single Layer Test Board)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
50
°C/W
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
JEDEC 51-6 (2S2P-Multi Layer Test Board) with Filled Thermal
Vias
0 LFPM
500 LFPM
24 QFN
24 QFN
37
32
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
Standard Board
20 TSSOP
24 QFN
23 to 41
11
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
Table 5. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Min
Characteristic
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
35
45
55
35
45
55
35
48
58
mA
VOH
Output HIGH Voltage (Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 4)
555
775
900
555
775
900
555
775
900
mV
VIH
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs) (Note 5)
1335
1335
VCC
1620
1335
1335
VCC
1620
1275
1275
VCC
1620
mV
VIL
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs) (Note 5)
VEE
555
875
875
VEE
555
875
875
VEE
555
875
875
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 6)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current (@VIH)
150
A
IIL
Input LOW Current (@VIL)
150
D
D
SEL
0.5
-150
-150
150
0.5
-150
-150
0.5
-150
-150
A
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.
4. All loading with 50 to VCC-2.0 V.
5. Do not use VBB at VCC < 3.0 V.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB100LVEP56
Table 6. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
45
55
35
45
55
35
48
58
mA
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 8)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 8)
1355
1575
1700
1355
1575
1700
1355
1575
1700
mV
VIH
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
2135
2135
VCC
2420
2135
2135
VCC
2420
2135
2135
VCC
2420
mV
VIL
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
VEE
1355
1675
1675
VEE
1355
1675
1675
VEE
1355
1675
1675
mV
VBB
Output Reference Voltage (Note 9)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 10)
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current (@VIH)
150
A
IIL
Input LOW Current (@VIL)
1875
1.2
1875
150
D
D
SEL
0.5
-150
-150
1875
150
0.5
-150
-150
A
0.5
-150
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
8. All loading with 50 to VCC-2.0 V.
9. Single-Ended input operation is limited to VCC 3.0 V in PECL mode.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 7. DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
40
50
60
40
50
60
45
55
65
mA
VOH
Output HIGH Voltage (Note 12)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 12)
3055
3275
3400
3055
3275
3400
3055
3275
3400
mV
VIH
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
3775
3775
VCC
4120
3775
3775
VCC
4120
3775
3775
VCC
4120
mV
VIL
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
VEE
3055
3375
3375
VEE
3055
3375
3375
VEE
3055
3375
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 13)
5.0
1.2
5.0
1.2
5.0
V
IIH
Input HIGH Current (@VIH)
150
A
IIL
Input LOW Current (@VIL)
Symbol
Characteristic
3575
1.2
150
D
D
SEL
0.5
-150
-150
3575
150
0.5
-150
-150
0.5
-150
-150
3575
A
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
12. All loading with 50 ohms to VCC-2.0 V.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB100LVEP56
Table 8. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 14)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
35
45
55
35
45
55
35
48
58
mA
VOH
Output HIGH Voltage (Note 15)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 15)
-1945
-1725
-1600
-1945
-1725
-1600
-1945
-1725
-1600
mV
VIH
Input HIGH Voltage
(SEL0, SEL1, COM_SEL)
Input HIGH Voltage
(D Inputs)
-1 165
VCC
-1 165
VCC
-1 165
VCC
-1 165
-880
-1 165
-880
-1 165
-880
Symbol
VIL
Characteristic
mV
Input LOW Voltage
(SEL0, SEL1, COM_SEL)
Input LOW Voltage
(D Inputs)
VEE
-1600
VEE
-1600
VEE
-1600
mV
-1945
-1600
-1945
-1600
-1945
-1600
VBB
Output Reference Voltage (Note 16)
-1525
-1325
-1525
-1325
-1525
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
IIH
Input HIGH Current (@VIH)
IIL
Input LOW Current (@VIL)
-1425
VEE+1.2
0.0
-1425
VEE+1.2
150
D
D
SEL
0.5
-150
-150
0.0
-1425
VEE+1.2
150
0.5
-150
-150
-1325
mV
0.0
V
150
A
A
0.5
-150
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC.
15. All loading with 50 to VCC-2.0 V.
16. Single-Ended input operation is limited to VEE from -3.0 V to -5.5 V in NECL mode.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 9. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -5.5 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
50
60
40
50
60
45
55
65
mA
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1725
-1600
-1945
-1725
-1600
-1945
-1725
-1600
mV
VIH
Input HIGH Voltage
(SEL0, SEL1, COM_SEL)
Input HIGH Voltage
(D Inputs)
-1 165
VCC
-1 165
VCC
-1 165
VCC
-1 165
-880
-1 165
-880
-1 165
-880
VIL
mV
Input LOW Voltage
(SEL0, SEL1, COM_SEL)
Input LOW Voltage
(D Inputs)
VEE
-1600
VEE
-1600
VEE
-1600
mV
-1945
-1625
-1945
-1625
-1945
-1625
VBB
Output Reference Voltage (Note 20)
-1525
-1325
-1525
-1325
-1525
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 21)
IIH
Input HIGH Current (@VIH)
IIL
Input LOW Current (@VIL)
-1425
VEE+1.2
0.0
150
D
D
SEL
0.5
-150
-150
-1425
VEE+1.2
0.0
150
0.5
-150
-150
-1425
VEE+1.2
0.5
-150
-150
-1325
mV
0.0
V
150
A
A
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 V.
20. Single-Ended input operation is limited to VEE from -3.0 V to -5.5 V in NECL mode.
21. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB100LVEP56
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 V to -3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 22)
-40 °C
Symbol
25°C
Min
Typ
fin 1 GHz
fin = 2 GHz
fin = 2.5 GHz
525
500
400
700
600
500
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
375
575
550
500
775
750
625
975
950
10
5
15
50
50
30
50
200
Characteristic
VOUTPP
Output Voltage Amplitude
(See Figure 2)
tPLH,
tPHL
Propagation Delay to Output Differential
tSkew
Pulse Skew (Note 23)
Within Device Input Skew (Note 24)
Within Device Output Skew (Note 25)
Device-to-Device Skew (Note 26)
tJITTER
RMS Random Clock Jitter
(Note 27)
Peak-to-Peak Data Dependent Jitter
(Note 28)
Max
Min
Typ
550
500
350
700
600
450
400
625
600
525
825
800
85°C
Max
Min
Typ
Max
500
400
200
700
500
300
450
700
700
575
900
900
700
1100
1100
10
5
15
50
50
30
50
200
ps
1
ps
mV
Unit
mV
ps
fin = 2.5 GHz
VINPP
Input Voltage Swing (Differential Configuration)
(Note 29)
tr
tf
Output Rise/Fall Times @ 50 MHz
(20% - 80%)
10
5
15
50
1
fin =1.5 Gb/s
fin = 2.5 Gb/s
650
1025
1000
1
5
15
10
25
10
25
150
800
1200
150
800
1200
150
800
1200
60
110
150
60
120
170
90
140
230
Q, Q
ps
22. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. Input edge rates 150 ps (20% - 80%).
23. Pulse Skew |tPLH - tPHL|
24. Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.
25. Worst case difference between Q0 and Q1 outputs.
26. Skew is measured between outputs under identical transitions.
27. Additive RMS jitter with 50% Duty Cycle Clock Signal at fin = 2.5 GHz.
28. Additive Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at fin = 2.5 Gb/s.
29. Input voltage swing is a single-ended measurement operating in differential mode.
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = -4.2 V to -5.5 V or VCC = 4.2 V to 5.5 V; VEE = 0 V (Note 30)
-40 °C
Symbol
25°C
Min
Typ
fin 1 GHz
fin = 2 GHz
fin = 2.5 GHz
600
550
400
750
650
550
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
375
575
550
500
775
750
625
975
950
5
15
20
50
50
30
50
200
Characteristic
VOUTPP
Output Voltage Amplitude
(See Figure 3)
tPLH,
tPHL
Propagation Delay to Output Differential
tSkew
Pulse Skew (Note 31)
Within Device Input Skew (Note 32)
Within Device Output Skew (Note 33)
Device-to-Device Skew (Note 34)
tJITTER
RMS Random Clock Jitter
(Note 35)
Peak-to-Peak Data Dependent Jitter
(Note 36)
Max
85°C
Min
Typ
Max
600
500
350
750
600
450
400
625
600
525
825
800
650
1025
1000
5
15
20
50
50
30
50
200
Min
Typ
Max
600
400
200
750
500
300
450
700
700
575
900
900
700
1100
1100
5
15
20
50
50
30
50
200
ps
1
ps
mV
Unit
mV
ps
fin = 2.5 GHz
1
fin =1.5 Gb/s
fin = 2.5 Gb/s
VINPP
Input Voltage Swing (Differential Configuration)
(Note 37)
tr
tf
Output Rise/Fall Times @ 50 MHz
(20% - 80%)
1
5
15
10
25
10
20
150
800
1200
150
800
1200
150
800
1200
60
110
150
60
120
170
90
140
230
Q, Q
ps
30. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. Input edge rates 150 ps (20% - 80%).
31. Pulse Skew |tPLH - tPHL|
32. Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.
33. Worst case difference between Q0 and Q1 outputs.
34. Skew is measured between outputs under identical transitions.
35. Additive RMS jitter with 50% Duty Cycle Clock Signal at fin = 2.5 GHz.
36. Additive Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at fin = 2.5 Gb/s.
37. Input voltage swing is a single-ended measurement operating in differential mode.
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7
NB100LVEP56
10.0
9.0
Q AMP (mV)
750
7.0
6.0
550
5.0
4.0
450
3.0
RMS JITTER (ps)
8.0
650
2.0
350
JITTER (ps)
1.0
0.0
250
0.5
1.0
1.5
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 2.5 V, 25C
850
10.0
9.0
Q AMP (mV)
750
8.0
7.0
650
6.0
550
5.0
4.0
450
3.0
2.0
350
1.0
JITTER (ps)
250
0.5
0.0
1.0
1.5
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 5.0 V, 25C
D
VINPP = VIH(D) - VIL(D)
D
Q
VOUTPP = VOH(Q) - VOL(Q)
Q
tPHL
tPLH
Figure 4. AC Reference Measurement
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8
RMS JITTER (ps)
OUTPUT VOLTAGE AMPLITUDE (mV)
OUTPUT VOLTAGE AMPLITUDE (mV)
850
NB100LVEP56
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
-
ECLinPS Circuit Performance at Non-Standard VIH Levels
AN1405
-
ECL Clock Distribution Techniques
AN1406
-
Designing with PECL (ECL at +5.0 V)
AN1504
-
Metastability and the ECLinPS Family
AN1568
-
Interfacing Between LVDS and ECL
AN1672
-
The ECL Translator Guide
AND8002
-
Marking and Date Codes
AND8009
-
ECLinPS Plus Spice I/O Model Kit
AND8020
-
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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9
NB100LVEP56
PACKAGE DIMENSIONS
20X
0.15 (0.006) T U
2X
TSSOP-20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E-02
ISSUE A
K REF
0.10 (0.004)
S
20
L/2
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
11
B
L
J J1
-U-
PIN 1
IDENT
SECTION N-N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. ICONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
S
M
A
-VN
F
DETAIL E
-W-
C
D
G
H
DETAIL E
0.100 (0.004)
-T-
SEATING
PLANE
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10
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
NB100LVEP56
PACKAGE DIMENSIONS
D
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L-01
ISSUE O
A
B
PIN 1
IDENTIFICATION
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
L
2X
0.15 C
0.15 C
2X
A2
0.10 C
A
0.08 C
A3
A1
SEATING
PLANE
REF
C
D2
e
L
7
12
6
13
E2
24X
b
1
0.10 C A B
18
24
19
e
0.05 C
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11
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.23
0.28
4.00 BSC
2.70
2.90
4.00 BSC
2.70
2.90
0.50 BSC
0.35
0.45
NB100LVEP56
ON Semiconductor and
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12
NB100LVEP56/D