NB100LVEP17 2.5V / 3.3V / 5VECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. • • • • • • Maximum Input Clock Frequency > 2.5 GHz Typical Maximum Input Data Rate > 2.5 Gb/s Typical http://onsemi.com MARKING DIAGRAMS* 20 20 1 N100 LP17 ALYW TSSOP-20 DT SUFFIX CASE 948E 1 250 ps Typical Propagation Delay 24 1 Low Profile QFN Package 24 PECL Mode Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -5.5 V Q Output Will Default LOW with Inputs Open or at VEE N100 LP17 ALYW 1 24 PIN QFN MN SUFFIX CASE 485L • • VBB Output A L Y W = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device NB100LVEP17DT Package Shipping TSSOP-20 75 Units/Rail NB100LVEP17DTR2 TSSOP-20 2500/Tape & Reel Semiconductor Components Industries, LLC, 2003 April, 2003 - Rev. 4 1 NB100LVEP17MN QFN-24 92 Units/Rail NB100LVEP17MNR2 QFN-24 3000/Tape & Reel Publication Order Number: NB100LVEP17/D NB100LVEP17 D0 R1 Q0 R2 D0 R1 Q0 D1 R1 Q1 R2 D1 R1 Q1 D2 R1 Q2 R2 Q2 D2 R1 VCC VEE D3 R1 Q3 R2 D3 R1 Q3 VBB Figure 1. Logic Diagram PIN DESCRIPTION ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Pin TSSOP QFN Name I/O Default State 1,20 13,18,21, 22,23 VCC - - Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. 11 10 VEE - - Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. 10 9 VBB - - ECL Reference Voltage Output. 2,4,6,8 1,3,5,7 D[0:3] ECL Input Low Noninverted Differential Inputs [0:3]. Internal 75 k to VEE. 3,5,7,9 2,4,6,8 D[0:3] ECL Input High Inverted Differential Inputs [0:3]. Internal 75 k to VEE and 37 k to VCC. 19,17,15,13 12,15,17,2 0 Q[0:3] ECL Output - Noninverted Differential Outputs [0:3]. Typically Terminated with 50 to VTT = VCC - 2 V. 18,16,14,12 11,14,16,1 9 Q[0:3] ECL Output - Inverted Differential Outputs [0:3]. Typically Terminated with 50 to VTT = VCC - 2 V. N/A 24 NC - - No Connect. The NC Pin is Electrically Connected to the Die and “MUST BE” Left Open. N/A - EP - Description Exposed Pad. (Note 1) 1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad on the package bottom (see case drawing) must be attached to a heat-sinking conduit. http://onsemi.com 2 NB100LVEP17 NC VCC VCC VCC Q0 24 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 18 17 15 14 13 12 19 16 11 23 22 21 20 1 2 3 4 5 6 7 8 9 VCC D0 D0 D1 D1 D2 D2 D3 D3 VBB 10 19 D0 1 18 VCC D0 2 17 Q1 D1 3 16 Q1 D1 4 15 Q2 D2 5 14 Q2 D2 6 13 VCC 7 8 D3 D3 9 10 VBB VEE 11 12 Q3 Q3 Figure 3. QFN-24 Lead Pinout (Top View) Figure 2. TSSOP-20 Lead Pinout (Top View) Table 1. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (R1) 75 k Internal Input Pullup Resistor (R2) 37 k Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Exposed Pad (EP) NB100LVEP17 NB100LVEP17 ESD Protection Q0 Oxygen Index: 28 to 34 Transistor Count > 2 kV > 150 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 274 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NB100LVEP17 Table 2. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units VCC Positive Mode Power Supply VEE = 0 V 6 V VEE Negative Mode Power Supply VCC = 0 V -6 V VI Positive Mode Input Voltage Negative Mode Input Voltage VEE = 0 V VCC = 0 V 6 -6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source 0.5 mA TA Operating Temperature Range -40 to +85 °C Tstg Storage Temperature Range -65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) JEDEC 51-3 (1S - Single Layer Test Board) 0 LFPM 500 LFPM 20 TSSOP 20 TSSOP 140 50 °C/W °C/W JA Thermal Resistance (Junction-to-Ambient) JEDEC 51-6 (2S2P Multilayer Test Board) with Filled Thermal Vias 0 LFPM 500 LFPM 24 QFN 24 QFN 37 32 °C/W °C/W JC Thermal Resistance (Junction-to-Case) Standard Board 20 TSSOP 24 QFN 23 to 41 11 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VI VCC VI VEE 2. Maximum Ratings are those values beyond which device damage may occur. Table 3. DC CHARACTERISTICS, PECL VCC = 2.5 V; VEE = 0 V (Note 3) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 40 50 30 40 50 30 40 55 mA 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV 775 775 775 IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 4) VOL Output LOW Voltage (Note 4) 555 900 555 900 555 900 mV VIH Input HIGH Voltage (Single-Ended) (Note 5) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single-Ended) (Note 5) 555 875 555 875 555 875 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) 150 D D 0.5 -150 NOTE: 3. 4. 5. 6. 150 0.5 -150 0.5 -150 A 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V. All loading with 50 to VEE = VCC - 2.0 V. Do not use VBB at VCC < 3.0 V. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB100LVEP17 Table 4. DC CHARACTERISTICS, PECL VCC = 3.3 V; VEE = 0 V (Note 7) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 40 50 30 40 50 30 40 55 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 8) 1355 1575 1700 1355 1575 1700 1355 1575 1700 mV VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV VBB ECL Output Reference Voltage (Note 9) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) 1875 1.2 1875 150 D D 0.5 -150 1875 150 0.5 -150 A 0.5 -150 NOTE: 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V. 8. All loading with 50 to VCC - 2.0 V. 9. Single ended input operation is limited VCC ≥ 3.0 V in PECL mode. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 5. DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 30 40 50 30 40 55 30 40 55 mA VOH Output HIGH Voltage (Note 12) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 12) 3055 3275 3400 3055 3275 3400 3055 3275 3400 mV VIH Input HIGH Voltage 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage 3055 3375 3055 3375 3055 3375 mV VBB ECL Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 5.0 1.2 5.0 1.2 5.0 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) 3575 1.2 150 D D 0.5 -150 3575 150 0.5 -150 0.5 -150 3575 A NOTE: 100LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 12. All loading with 50 ohms to VCC-2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB100LVEP17 Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 14) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 30 40 50 30 40 50 30 40 55 mA VOH Output HIGH Voltage (Note 15) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mV VOL Output LOW Voltage (Note 15) -1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600 mV VIH Input HIGH Voltage (Single-Ended) -1 165 -880 -1 165 -880 -1 165 -880 mV VIL Input LOW Voltage (Single-Ended) -1945 -1600 -1945 -1600 -1945 -1600 mV VBB ECL Output Reference Voltage (Note 16) -1525 -1325 -1525 -1325 -1525 -1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 17) 0.0 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) -1425 VEE + 1.2 0.0 -1425 VEE + 1.2 150 D D 0.5 -150 0.0 -1425 VEE + 1.2 150 0.5 -150 A 0.5 -150 NOTE: 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 14. Input and output parameters vary 1:1 with VCC. 15. All loading with 50 to VCC - 2.0 V. 16. Single ended input operation is limited VEE ≤ -3.0V in NECL mode. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -5.5 V (Note 18) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 30 40 50 30 40 55 30 40 55 mA VOH Output HIGH Voltage (Note 19) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mV VOL Output LOW Voltage (Note 19) -1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600 mV VIH Input HIGH Voltage -1 165 -880 -1 165 -880 -1 165 -880 mV VIL Input LOW Voltage -1945 -1625 -1945 -1625 -1945 -1625 mV VBB ECL Output Reference Voltage (Note 20) -1525 -1325 -1525 -1325 -1525 -1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 21) 0.0 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) -1425 VEE+1.2 0.0 VEE+1.2 150 D D 0.5 -150 -1425 0.0 VEE+1.2 150 0.5 -150 -1425 0.5 -150 A NOTE: 100LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 to VCC-2.0 V. 20. Single-Ended input operation is limited to VEE from -3.0 V to -5.5 V in NECL mode. 21. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 NB100LVEP17 Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 V to -3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 22) -40 °C Symbol 25°C Min Typ fin < 1 GHz fin = 2 GHz fin = 2.5 GHz 600 400 300 700 500 400 D to Q, Q 200 250 325 5 5 25 Characteristic VOUTPP Output Voltage Amplitude (See Figures 4, 5) tPLH, tPHL Propagation Delay to Output Differential tSkew Pulse Skew (Note 23) Within Device Skew (Note 25) Device-to-Device Skew (Note 25) tJITTER RMS Random Clock Jitter (Note 26) Peak-to Peak Data Dependent Jitter (Note 27) VINPP Input Voltage Swing (Differential Configuration) (Note 28) tr tf Output Rise/Fall Times @ 50 MHz (20% - 80%) Max 85°C Min Typ Max Min Typ 600 325 250 700 500 400 200 250 325 25 25 100 5 5 25 0.5 5 5 1 15 15 150 800 1200 125 175 225 Max 550 300 200 700 500 400 225 300 350 25 25 100 5 5 25 25 25 100 ps 0.5 5 5 1 15 15 0.5 5 5 1 15 15 ps 150 800 1200 150 800 1200 mV 140 190 240 150 200 250 Unit mV ps fin = 2.5 GHz fin = 1.5 Gb/s fin = 2.5 Gb/s Q, Q ps 22. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. Input edge rates 150 ps (20% - 80%). 23. Pulse Skew = |tPLH - tPHL| 24. Worst case difference between Q0 and Q1 outputs. 25. Skew is measured between outputs under identical transitions. 26. Additive RMS jitter with 50% Duty Cycle Clock Signal at 2.5 GHz. 27. Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at 2.5 Gb/s with all inputs active. 28. Input voltage swing is a single-ended measurement operating in differential mode, with minimum propagation change of 50 ps. Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = -4.2 V to -5.5 V or VCC = 4.2 V to 5.5 V; VEE = 0 V (Note 29) -40 °C Symbol Typ fin < 1 GHz fin = 2 GHz fin = 2.5 GHz 650 450 350 750 550 450 D to Q, Q 200 250 325 5 5 25 fin = 2.5 GHz fin =1.5 Gb/s fin = 2.5 Gb/s Characteristic VOUTPP Output Voltage Amplitude (See Figure 6) tPLH, tPHL Propagation Delay to Output Differential tSkew Pulse Skew (Note 30) Within Device Skew (Note 31) Device-to-Device Skew (Note 32) tJITTER RMS Random Clock Jitter (Note 33) Peak-to-Peak Data Dependent Jitter (Note 34) 25°C Min Max 85°C Min Typ Max Min Typ 650 425 300 750 525 400 200 250 325 25 25 100 5 5 25 0.5 1 5 10 15 20 150 800 1200 125 175 225 Max 650 350 250 750 450 350 225 300 350 25 25 100 5 5 25 25 25 100 ps 0.5 1 0.5 1 ps 5 10 15 20 5 15 15 50 150 800 1200 150 800 1200 140 190 240 150 200 250 Unit mV ps VINPP Input Voltage Swing (Differential Configuration) (Note 35) tr tf Output Rise/Fall Times @ 50 MHz (20% - 80%) Q, Q mV ps 29. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. Input edge rates 150 ps (20% - 80%). 30. Pulse Skew |tPLH - tPHL| 31. Worst case difference between Q0 and Q1 outputs. 32. Skew is measured between outputs under identical transitions. 33. Additive RMS jitter with 50% Duty Cycle Clock Signal at 2.5 GHz. 34. Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at 2.5 Gb/s. 35. Input voltage swing is a single-ended measurement operating in differential mode, with minimum propagation change of 50 ps. http://onsemi.com 7 NB100LVEP17 10 9.0 750 8.0 Q AMP (mV) 7.0 650 6.0 5.0 550 4.0 450 3.0 RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) 850 2.0 350 RMS JITTER (ps) 1.0 0 250 0.5 1.0 1.5 2.0 2.5 INPUT FREQUENCY (GHz) 850 10 9.0 750 8.0 Q AMP (mV) 7.0 650 6.0 5.0 550 4.0 450 3.0 RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 2.5 V, Ambient Temperature 2.0 350 RMS JITTER (ps) 1.0 0 250 0.5 1.0 1.5 2.0 2.5 INPUT FREQUENCY (GHz) Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 3.3 V, Ambient Temperature 9.0 Q AMP (mV) 8.0 750 7.0 650 6.0 5.0 550 4.0 450 3.0 RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) 850 2.0 350 RMS JITTER (ps) 1.0 250 0.5 1.0 1.5 2.0 0 2.5 INPUT FREQUENCY (GHz) Figure 6. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 5.0 V, Ambient Temperature http://onsemi.com 8 NB100LVEP17 D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH Figure 7. AC Reference Measurement Q D Receiver Device Driver Device Q D 50 50 V TT V TT = V CC - 2.0 V Figure 8. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 - ECLinPS Circuit Performance at Non-Standard VIH Levels AN1405 - ECL Clock Distribution Techniques AN1406 - Designing with PECL (ECL at +5.0 V) AN1504 - Metastability and the ECLinPS Family AN1568 - Interfacing Between LVDS and ECL AN1650 - Using Wire-OR Ties in ECLinPS Designs AN1672 - The ECL Translator Guide AND8001 - Odd Number Counters Design AND8002 - Marking and Date Codes AND8009 - ECLinPS Plus Spice I/O Model Kit AND8020 - Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 9 NB100LVEP17 PACKAGE DIMENSIONS TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A 20X 0.15 (0.006) T U 2X S 20 L/2 M T U S V S K K1 11 B L J J1 -U- PIN 1 IDENT ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SECTION N-N 1 10 0.25 (0.010) N 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. ICONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K REF 0.10 (0.004) S M A -VN F DETAIL E -W- C D G H DETAIL E 0.100 (0.004) -T- SEATING PLANE http://onsemi.com 10 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 NB100LVEP17 PACKAGE DIMENSIONS QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L-01 ISSUE O D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN 1 IDENTIFICATION E DIM A A1 A2 A3 b D D2 E E2 e L 2X 0.15 C 0.15 C 2X A2 0.10 C A 0.08 C A3 A1 SEATING PLANE REF C D2 e L 7 12 6 13 E2 24X b 1 0.10 C A B 18 24 19 e 0.05 C http://onsemi.com 11 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45 NB100LVEP17 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 12 NB100LVEP17/D