GM71C16160C GM71CS16160CL 1,048,576 W O R D S x 1 6 B I T CMOS DYNAMIC RAM Description F eatur es T h e G M 7 1 C ( S ) 1 6 1 6 0 C /C L i s t h e n e w generation dynamic RAM organized 1,048,576 x 1 6 b i t . G M 7 1 C ( S ) 1 6 1 6 0 C /CL has realized higher density, higher performance and various * * * * functions by utilizing advanced CMOS process technology. The GM71C(S)16160C/CL offers 1 ,048,576 Words x 16 Bit Organization Fast Page Mode Capability S ingle Power Supply (5V+/-10%) Fast Access Time & Cycle Time (Unit: ns) tR C tP C Fast Page Mode as a high speed access mode. G M 7 1 C ( S ) 1 6 1 6 0 C /C L - 5 50 13 90 35 Multiplexed address inputs permit the G M 7 1 C ( S ) 1 6 1 6 0 C /C L t o b e p a c k a g e d i n G M 7 1 C ( S ) 1 6 1 6 0 C /C L - 6 60 15 110 40 G M 7 1 C ( S ) 1 6 1 6 0 C /C L - 7 70 18 130 45 standard 400 mil 42 pin plastic SOJ , and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. tR A C tC A C * Low Power Active : 605/550/4 9 5 m W ( M A X ) S tandby : 11mW (CMOS level : MAX ) 0.83mW (L-version : MAX ) * R A S O nly Refresh, CAS before RAS Refresh, Hidden Refresh Capability * * * * * * P in Configur a t ion All inputs and outputs TTL Compatible 4096 Refresh Cycles/64ms 4096 Refresh Cycles/128ms (L-version) Self Refresh Operation (L-version) B attery B ack Up Operation (L-version) 2 CAS byte Control 4 2 SOJ 44(50) T S O P I I V CC 1 50 V SS I/O 0 2 49 I/O 1 5 I/O 1 3 48 I/O 1 4 I/O 2 4 47 I/O 1 3 I/O 3 5 46 I/O 1 2 V CC 6 45 V SS I/O 4 7 44 I/O 1 1 I/O 1 1 I/O 5 8 43 I/O 1 0 35 I/O 1 0 I/O 6 9 42 I/O 9 9 34 I/O 9 I/O 7 10 41 I/O 8 I/O 7 10 33 I/O 8 NC 11 40 NC NC 11 32 NC V CC 1 42 V SS I/O 0 2 41 I/O 1 5 I/O 1 3 40 I/O 1 4 I/O 2 4 39 I/O 1 3 I/O 3 5 38 I/O 1 2 V CC 6 37 V SS I/O 4 7 36 I/O 5 8 I/O 6 NC 12 31 LCAS NC 15 36 NC WE 13 30 UCAS NC 16 35 LCAS RAS 14 29 OE WE 17 34 UCAS OE A11 15 28 A9 RAS 18 33 A10 16 27 A8 A11 19 32 A9 A0 17 26 A7 A10 20 31 A8 A1 18 25 A6 A0 21 30 A7 A1 29 A2 A6 19 24 A5 22 A2 23 28 A5 A3 20 23 A4 A3 24 27 A4 V CC 21 22 V SS V CC 25 26 (Top View) Rev 0.1 / Apr’01 V SS GM71C16160C GM71CS16160CL P in Descr iption P in F unction P in Address Inputs WE Read/W rite Enable Refresh Address Inputs OE Output Enable Data Input/ Data Output RAS UCAS, LCAS F unction CC Power (+5V) Row Address Strobe V SS Ground Column Address Strobe NC No Connection O r d e r ing Infor m a t ion T ype No. Access Time Package G M 7 1 C ( S ) 1 6 1 6 0 C J /C L J - 5 G M 7 1 C ( S ) 1 6 1 6 0 C J /C L J - 6 G M 7 1 C ( S ) 1 6 1 6 0 C J /C L J - 7 5 0 ns 60ns 70ns 4 0 0 Mil 42 Pin Plastic SOJ G M 7 1 C ( S ) 1 6 1 6 0 C T /C L T - 5 G M 7 1 C ( S ) 1 6 1 6 0 C T /C L T - 6 G M 7 1 C ( S ) 1 6 1 6 0 C T /C L T - 7 5 0 ns 60ns 70ns 4 0 0 Mil 44(50) Pin Plastic TSOP II Absolute Maximum Ratings* Symbol Parameter Rating Unit 0 ~ +7 0 C -55 ~ +1 2 5 C TA Ambient Temperature under B ias T STG S torage Temperature (Plastic) V IN/O U T Voltage on any Pin Relative to V S S -1.0 ~ + 7 . 0 V V V CC Voltage on V C C Relative to V S S -1.0 ~ + 7 . 0 V V IOUT Short Circuit Output Current 50 mA PD Power Dissipation 1.0 W Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Rev 0.1 / Apr’01 GM71C16160C GM71CS16160CL R ecommended DC Operating Conditions (T A = 0 ~ + 70C) Symbol Parameter M in T yp Max Unit V CC S upply Voltage 4.5 5.0 5.5 V V IH Input High Voltage 2.4 - 6.0 V V IL Input Low Voltage -1.0 - 0.8 V Note: All voltage referred to V ss. T he supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. T r uth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open L L H H L Valid Lower byte L H L H L Valid Upper byte L L L H L Valid Word L L H L D Open Lower byte L H L L D Open Upper byte L L L L D Open Word L L H L H Undefined Lower byte L H L L H Undefined Upper byte L L L L H Undefined Word L L H H to L L to H Valid Lower byte L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word H to L H L D D Open Word H to L L H D D Open Word H to L L L D D Open Word L H H D D Open Word L L L H H Open S tandby 1,3 Read cycle 1,3 Early write cycle 1,2,3 Delayed Write cycle 1,2,3 Read-modify -write cycle 1,3 C B R R e f resh or Self Refresh (L-series) 1,3 RAS-only Refresh cycle 1,3 Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tW C S >= 0ns Early write cycle tW C S <= 0ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS,LCAS. ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Rev 0.1 / Apr’01 Notes 1,3 GM71C16160C GM71CS16160CL CC Symbol = 5V+/-10%, V ss A Parameter = 0 ~ 70C) M in Max Unit V OH Output Level Output "H" Level Voltage (I O U T = - 5 m A ) 2.4 V CC V V OL Output Level Output "L" Level Voltage (I O U T = 4. 2m A ) 0 0.4 V ICC1 Operating Current ( R A S , U C A S o r L C A S C y c l i n g : tR C = tR C min) ICC2 ICC3 ICC4 ICC6 110 ns 100 70 S tandby Current (TTL) Power Supply Standby Current ( R A S , U C A S , L C A S = V I H , D O U T = High-Z) - 90 - 2 RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (t R C = tR C min) 5 0 ns 110 ns 100 Fast Page Mode Current 5 0 ns 115 ns 105 - 70 Fast Page Mode ( P C = tP C min) ICC5 5 0 ns 70 S tandby Current (CMOS) Power Supply Standby Current ( R A S , U C A S o r L C A S > = V C C - 0 . 2 V , D O U T = High-Z) CAS-before-RAS Refresh Current (t R C = tR C min) ns 70 (Standby with CBR Refresh) ( =31.3us , <= 0.3 OUT= ICC8 95 - 1 - 150 mA 2 mA mA 5 110 mA - 90 - 500 - UCAS, LCAS = V uA mA D OUT ICC9 (RAS, UCAS or LCAS<=0.2V IL(I) Input Leakage Current Any Input (0V <= V I N <= 6 V ) IL(O) Output Leakage Current OUT = ( D O U T is Disabled, 0V <= V O U T <= 6 V ) Note: 1. I C C depends on output load condition when the device is selected. (max) is specified at the output open condition. 2. Address can be changed once or less while RAS = V I L 3. Address can be changed once or less while LCAS and UCAS = V I H . 5. L-version. Rev 0.1 / Apr 01 1, 2 90 - 5 0 ns mA Note - 300 uA -10 10 uA -10 10 uA 1 GM71C16160C GM71CS16160CL C a p a c itance ( V C C = 5V+/-10%, T A = 25C) Symbol Parameter M in Max Unit Note C I1 Input Capacitance (Address) - 5 pF 1 C I2 Input Capacitance (Clocks) - 7 pF 1 C I/O Output Capacitance (Data-In/Out) - 7 pF 1, 2 Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method. 2 . U C A S a n d L C A S = V I H to disable D O U T . A C C h a r a c t e r istics ( V C C = 5V+/-10%, T A = 0 ~ + 70C, Vss = 0V, Note 1, 2, 3, 19) Test Conditions Input rise and fall times : 5 ns Input timing reference levels : 0.8V , 2 . 4 V Output timing reference levels : 0.4V, 2.4V Output load : 2TTL gate + C L ( 1 0 0 pF) (Including scope and jig) R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles (Common Parameters) Symbol Parameter GM71C(S)16160 C/CL-5 Min M a x GM71C(S)16160 GM71C(S)16160 C/CL-6 C/CL-7 Min Max Unit Note Min M a x tR C Random Read or Write Cycle Time 90 - 110 - 130 - ns tR P R A S Precharge Time 30 - 40 - 50 - ns tC P C A S Precharge Time 7 - 10 - 10 - ns tR A S RAS Pulse Width 50 10,000 60 10,000 70 10,000 ns tC A S CAS Pulse Width 13 10,000 15 10,000 18 10,000 ns tA S R Row Address Set up Time 0 - 0 - 0 - ns tR A H Row Address Hold Time - 10 - 10 - ns tA S C Column Address Set-up Time - 0 - 0 - ns 22 tC A H Column Address Hold Time - 10 - 15 - ns 22 tR C D RAS to CAS Delay Time 17 45 20 45 20 52 ns 4 tR A D RAS to Column Address Delay Time 12 30 15 30 15 35 ns 5 tR S H RAS Hold Time 13 - 15 - 18 - ns tC S H CAS Hold Time 50 - 60 - 70 - ns tC R P C A S t o R A S Precharge T i m e 5 - 5 - 5 - ns 23 tO D D O E t o D I N Delay Time 13 - 15 - 18 - ns 6 tD Z O OE Delay Time from D I N 0 - 0 - 0 - ns 7 tD Z C CAS Delay Time from D I N 0 - 0 - 0 - ns 7 tT T ransition Time (Rise and Fall) 3 50 3 50 3 50 ns 8 Rev 0.1 / Apr’01 7 0 7 25 GM71C16160C GM71CS16160CL R ead Cycle Symbol Parameter GM71C(S)16160 GM71C(S)16160 GM71C(S)16160 C/CL-5 C/CL-6 Min M a x C/CL-7 Min M a x Unit Note Min M a x tR A C Access Time from RAS - 50 - 60 - 70 ns 9,10 tC A C Access Time from CAS - 13 - 15 - 18 ns 10,11,18 tA A Access Time from Address - 25 - 30 - 35 ns 10,11,18 tO A C Access Time from OE - 13 - 15 - 18 ns 10,26 tR C S Read Command Setup Time 0 - 0 - 0 - ns tR C H Read Command Hold Time to CAS 0 - 0 - 0 - ns 13,23 tR R H Read Command Hold Time to RAS 5 - 5 - 5 - ns 13 tR A L Column Address to RAS Lead Time 25 - 30 - 35 - ns tC A L Column Address to CAS Lead Time 25 - 30 - 35 - ns tC L Z CAS to Output in Low-Z 0 - 0 - 0 - ns tO H Output Data Hold Time 3 - 3 - 3 - ns tO H O Output Data Hold Time from OE 3 - 3 - 3 - ns tO F F Output B uffer Turn-off Time - 13 - 15 - 15 ns 14 tO E Z Output B uffer Turn-off Time to OE - 13 - 15 - 15 ns 14 tC D D C A S t o D I N Delay Time 13 - 15 - 18 - ns 6 Unit Note W r ite Cycle Symbol Parameter GM71C(S)16160 C/CL-5 Min M a x GM71C(S)16160 C/CL-6 Min Max GM71C(S)16160 C/CL-7 Min M a x tW C S Write Command Setup Time 0 - 0 - 0 - ns 15,22 tW C H Write Command Hold Time 7 - 10 - 15 - ns 22 tW P Write Command Pulse Width 7 - 10 - 10 - ns tR W L Write Command to RAS Lead Time 13 - 15 - 18 - ns tC W L Write Command to CAS Lead Time 13 - 15 - 18 - ns 24 tD S Data-in Setup Time 0 - 0 - 0 - ns 16,24 tD Data-in Hold Time 7 - 10 - 15 - ns 16,24 H Rev 0.1 / Apr’01 GM71C16160C GM71CS16160CL R ead- Modify-W r ite Cycle Symbol Parameter GM71C(S)16160 GM71C(S)16160 GM71C(S)16160 C/CL-5 C/CL-6 C/CL-7 Unit Min M a x Min Max 131 - 155 - 181 - ns Note Min M a x tR W C Read-Modify-Write Cycle Time tR W D RAS to WE Delay Time 73 - 85 - 98 - ns 15 tC W D CAS to WE Delay Time 36 - 40 - 46 - ns 15 tA W D Column Address to WE Delay Time 48 - 55 - 63 - ns 15 tO E H OE Hold Time from WE 13 - 15 - 18 - ns R efresh Cycle Symbol Parameter GM71C(S)16160 C/CL-5 Min GM71C(S)16160 C/CL-6 M a x Min GM71C(S)16160 C/CL-7 Max Min Max Unit Note tC S R CAS Setup Time (CAS-before-RAS Refresh Cycle) 5 - 5 - 5 - ns 22 tC H R CAS Hold Time (CAS-before-RAS Refresh Cycle) 7 - 10 - 10 - ns 23 tR P C R A S Precharge to CAS Hold Time 5 - 5 - 5 - ns 22 Unit Note F a st Page Mode Cycle Symbol Parameter GM71C(S)16160 GM71C(S)16160 GM71C(S)16160 C/CL-5 C/CL-6 C/CL-7 M a x Min M a x Min Max Min 35 - 40 - 45 - ns tP C Fast Page Mode Cycle Time tR A S P Fast Page Mode RAS Pulse Width - 100,000 - 100,000 - 100,000 ns 17 tA C P Access Time from CAS Precharge - 30 - 35 - 40 ns 10,18,23 tR H C P RAS Hold Time from CAS Precharge 30 - 35 - 40 - ns Rev 0.1 / Apr’01 GM71C16160C GM71CS16160CL F a st Page Mode Read-Modify-W r ite Cycle Symbol Parameter GM71C(S)16160 GM71C(S)16160 GM71C(S)16160 C/CL-5 C/CL-6 Min M a x tP R W C tC P W Unit 85 - 96 - ns WE Delay Time from CAS Precharge 53 - 60 - 68 - ns Parameter RAS Pulse Width(Self-Refresh) R A S Precharge Time(Self-Refresh) CAS Hold Time(Self-Refresh) Note Min M a x - GM71CS16160 GM71CS16160 GM71CS16160 CL-5 CL-6 CL-7 Min M a x Min M a x Min M a x tC H S Max 76 Symbol tR P S Min Fast Page Mode Read-Modify-Write Cycle Time Self R e fr esh Mode tR A S S C/CL-7 Unit 100 - 100 - 100 - us 90 - 110 - 130 - ns -50 - -50 - -50 - ns 15,23 Note 27 Notes: 1. AC measurements assume tT = 5ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Only row address is indispensable on address A8, A9, A10, A11. 4. Operation with the tR C D (max)limit insures that tR A C (max)can be met, tR C D (max)is specified as a reference point only; if tR C D >= tR A D (max) + tA A (max) - tC A C (max), then access time is controlled exclusively by tC A C . 5. Operation with the tR A D (max) limit insures that tR A C (max)can be met, tR A D (max)is specified as a reference point only; if tR A D is greater than the specified tR A D (max)limit, then access time is controlled exclusively by tAA. 6. Either tO D D or tC D D must be satisfied. 7. Either tD Z O or tD Z C must be satisfied. 8. V IH (min) and V I L (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and V I L (max). 9. Assumes that tR C D <= tR C D (max) and tR A D <= tR A D (max). If tR C D or tR A D is greater than the maximum recommended value shown in this table, tR A C exceeds the value shown. 10. Measured with a load circuit equivalent to 2 TTL load and 100pF. 11. Assumes that tR C D >= tR C D (max) and tR C D + tC A C (max) >= tR A D + tA A (max). 12. Assumes that tR A D >= tR A D (max) and tR C D + tC A C (max) <= tR A D + tA A (max). Rev 0.1 / Apr’01 GM71C16160C GM71CS16160CL Either tR C H or tR R H must be satisfied for a read cycles. 14. tO F F (max) and tO E Z (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. WCS , ,t t are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t >= tW C S (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle ; if tR W D >= tR W D (min), tC W D >= t tA W D t >= tA W D (min), or tC W D tC W D t tC P W contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of data out (at access time)is indeterminate. WE leading edge in delayed write or read-modify-write cycles. 17. tR A S P 18. Access time is determined by the longest among A A t ,and tA C P 19. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tO E H >= tC W L , the I/O pin will remain open circuit (high impedance); if tO E H < tC W L , invalid data will be out at each I/O. 20. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 21. All the V C C and V S S pins shall be supplied with the same voltages. 22. tA S C , tC A H , tR C S , tW C S , tW C H , tC S R and tR P C are determined by the earlier falling edge of UCAS or LCAS. 23. tC R P , tC H R , tR C H , tA C P and tC P W are determined by the later rising edge of UCAS or LCAS. 24. tC W L , tDH , tD S and tC S H should be satisfied by both UCAS and LCAS. 25. tC P is determined by that time the both UCAS and LCAS are high. 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. W hen output buffer is turned on and off within a very short time, generally it causes large V C C /V S S line noise, which causes to degrade V IH min/V I L max level. 27. Please do not use tR A S S timing, 10us <= t transition state from normal operation mode to self refresh mode. If RASS >=1 0 0 us, then R A S precharge time should use tR P S instead of tR P . 28. If you use distributed CB R refresh within 15.6us interval in normal read/write cycle, CB R refresh should be executed within 15.6us immediately after exiting from and before entering into self refresh mode. 29. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024 cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or 16ms immediately after exiting from and before entering into the self refresh mode. 30. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 31. H or L (H: V IH (min) <= V IH IL <= V IN <= V I L (max)) Rev 0.1 / Apr 01 GM71C16160C GM71CS16160CL Package Dimension Unit: Inches (mm) 42 SOJ 0.025(0.64) 0.360(9.15) MIN 0.380(9.65) MAX 0.435(11.06) MIN 0.445(11.30) MAX 0.395(10.03) MIN 0.405(10.29) MAX MIN 0.093(2.38) 1.058(26.89) MAX MIN 1.072(27.23) MAX 0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) 0.026(0.66) MIN 0.032(0.81) MAX TYP 0.015(0.38) MIN 0.020(0.50) MAX 44(50) TSOP I 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX Rev 0.1 / Apr’01 0.016(0.40) MIN 0.024(0.60) MAX 0.004(0.12) MIN 0.008(0.21) MAX 0.820(20.82) MIN 0.830(21.08) MAX 0.012(0.30) MIN 0.017(0.45) MAX £ 0.471(11.96) MAX 0.455(11.56) MIN 0.405(10.29) MAX 0.394(10.03) MIN 0 ~ 5¡ 0.031(0.80) TYP 0.002(0.05) MIN 0.006(0.15) MAX