NSBMC292 TM -16/-25/-33 Burst Memory Controller General Description The NSBMC292 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an Am29030TM or Am29035 Processor. The NSBMC292 is functionally equivalent to the V292BMC TM . The on-chip I-cache of these processors serves to partially decouple throughput from the performance of main memory, however, a sophisticated memory design is still required for optimum performance. Static RAM offers a simple solution. Unfortunately, this solution is relatively expensive and space consumptive because of low bit density per device and high cost per bit. From a cost and density point of view, Dynamic RAM is an attractive alternative. The drawbacks are relatively slow access times and the complexity of the control circuitry required to operate them. The access time problem is solved if the DRAM is used in page mode. In this mode, access times rival that of static RAM. The control circuit problem is resolved by the NSBMC292. The function that the NSBMC292 performs is to optimally translate the burst access protocol of the Am29030/35 to the page mode access protocol supported by dynamic RAMs. One or two-way interleaved arrangements of DRAMs are supported. During burst access, data is accessed at the rate of one word per two cycles for non-interleaved, per cycle for two-way interleaved. The NSBMC292 has been designed to allow maximum flexibility in its application. The full range of processor speeds is supported for a wide range of DRAM speeds, sizes and organizations. Because the bus interface is customized to the Am29030/35, no glue logic is required. Integration is further enhanced by providing on-chip, a 24-bit timer and a 5-bit bus time-out monitor. The NSBMC292 is packaged as a 132-pin PQFP with a footprint of only 1.3 square inches. It reduces design complexity, space requirements and is fully derated for loading, temperature and voltage. Features Y Y Y Y Y Y Y Y Y Y Interfaces directly to the Am29030/35 Manages page mode dynamic memory devices Supports DRAMs from 256 kbits to 64 MB Non-interleaved or two way interleaved operation Software-configured operational parameters Integrated page cache management On-Chip memory address multiplexer/drivers 24-Bit counter/timer 5-Bit bus watch timer High-speed/low power CMOS technology Block Diagram TL/V/11806 – 1 Typical System Configuration This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corp. This information is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corp. reserves the right to change and improve the specifications of this product without notice. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. NSBMC292TM and WATCHDOGTM are trademarks of National Semiconductor Corporation. Am29030TM is a trademark of Advanced Micro Devices, Sunnyvale, California, U.S.A. V292BMCTM is a trademark of V3 Corporation. C1995 National Semiconductor Corporation TL/V/11806 RRD-B30M115/Printed in U. S. A. NSBMC292-16/-25/-33 Burst Memory Controller August 1993 Logic and Connection Diagrams TL/V/11806 – 2 TL/V/11806 – 3 Order Number NSBMC292VF See Package Number VF132A 2 Pin Descriptions TABLE I Pin Ý Signal Name Pin Ý Signal Name Pin Ý Signal Name 1 2 3 4 5 6 A14 A15 A16 VCC A17 A19 44 45 46 47 48 53 LEB TXA TXB VCC VSS AA0 91 92 93 94 95 96 VCC VSS AB4 AB5 AB6 AB7 7 8 9 10 11 12 A20 A18 A21 A24 A22 A23 54 55 56 57 58 59 AA1 AA2 AA3 VCC VSS AA4 97 98 99 100 101 102 VCC VSS AB8 AB9 AB10 AB11 13 14 15 19 20 21 A26 A25 A27 A31 A28 A29 60 61 62 63 64 65 AA5 AA6 AA7 VCC VSS AA8 103 104 105 106 107 108 VCC VSS CASB0 CASB1 CASB2 CASB3 22 23 24 25 26 27 A30 I/D SUP/USR MEMCLK INT ERR 66 67 68 69 70 71 AA9 AA10 AA11 VCC VSS CASA0 109 110 111 112 113 114 VCC VSS RASB0 RASB1 RASB2 RASB3 28 29 30 31 32 33 R/W BWE0 PRDY BURST BWE1 VSS 72 73 74 75 76 77 CASA1 CASA2 CASA3 VCC VSS RASA0 115 118 119 120 121 122 VCC MWEB VSS RESET A2 A3 34 35 36 37 38 39 REQ BWE2 BWE3 VSS READY ID0 78 79 80 81 82 86 RASA1 RASA2 RASA3 VCC MWEA VSS 123 124 125 126 127 128 A4 A5 A6 A7 A8 A9 40 41 42 43 ID1 ID2 REFRESH LEA 87 88 89 90 AB0 AB1 AB2 AB3 129 130 131 132 A10 A11 A12 A13 Note: In order for the switching characteristics of this device to be guaranteed, it is necessary to connect all of the power pins (VCC, VSS) to the appropriate power levels. The use of low impedance wiring to the power pins is required. In systems using the Am29030 with its attendant high switching rates, multi-layer printed circuit boards with buried power and ground planes are required. 3 Pin Descriptions (Continued) named pins on the Am29030/35 and the NSBMC292 are to be wired together. All 3-State outputs are to be weakly pulled up to VCC. A 10 kX resistor is sufficient. Am29030/35 INTERFACE The following pins are functionally equivalent to those on the Am29030/35 from which their names are taken. Like Pin Description A2 – 31 Address Bus (Input): This system bus is a word address which determines the location at which an access is required. REQ Address Strobe (Input; Active Low): This input is used to indicate that a valid access cycle is in progress. I/*D Data/*Code (Input): This input qualifies an access as being for data (Low) or instruction (High). BURST Burst Last (Input; Active Low): Processor output that indicates that the data can be continuously transferred in a sequential burst. PRDY Processor Ready (Input; Active Low): The RDY signal directly at the processor is monitored by the Bus time-out monitor to detect an incomplete bus access. See Bus Monitor Control (p8). RDY Data Ready (Output; 3-State; Active Low): The RDY output is used to signal the processor that data on the Bus is valid (Read), or that data has been accepted for Write. RESET Reset (Input; Active Low): Assertion of this input sets the NSBMC292 to its initial state. Following initialization, the NSBMC292 must be configured before any memory access is possible. BWE0 – 3 Byte Write Enable (Input; Active Low): These inputs are used to determine which byte(s) within the addressed word are to be written. R/*W WRITE /*READ (Input): This input indicates the direction which data is to be transferred to/from on the data bus. SUP/*USR Supervisor (Input; Active Low): Indicates that the processor is operating in supervisor mode. Required for access to configuration registers. MEMCLK Memory System Clock (Input): Processor output clock required to operate and synchronize NSBMC292 internal functions. ERR Bus Error (Output; Active Low): When enabled, this signal is generated by the Bus Monitor Circuit to prevent processor lock-up on access to a region that is not responding. INT Interrupt (Output; 12 mA; Active Low): This signal is asserted when the 24-bit counter reaches terminal count, and interrupt out is enabled. May be programmed for pulse or handshake operation. ID0 – 2 Chip ID (Input): These inputs select the address offset of the NSBMC292 configuration registers. Each NSBMC292 in a system must have a unique address for proper operation. 4 Pin Descriptions (Continued) drivers in order to minimize propagation delay due to memory input impedance and trace capacitance. External array drivers are not required. The address and control signals, however, should be externally terminated. MEMORY INTERFACE The NSBMC292 is designed to drive a memory array organized as 2 leaves each of 32 bits. The address and control signals for the memory array are output through high current Pin Description A(A,B)0 – 11 Multiplexed Address Bus (Output; 24 mA): These two buses transfer the multiplexed row and column addresses to the memory array leaves A and B. Note that when non-interleaved operation is selected, only address bus A should be used. RAS(A,B)0–3 Row Address Strobes (Output; 12 mA Active Low): These strobes indicate the presence of a valid row address on busses A(A,B)0–11. These signals are to be connected one to each leaf of memory. Four banks of interleaved memory may be attached to a NSBMC292. CAS(A,B)0–3 Column Address Strobe (Output; 12 mA, Active Low): These strobes latch a column address from A(A,B)0 – 11. They are assigned one to each byte in a leaf. MWE(A,B) Memory Write Enable (Output; 24 mA, Active Low): These are the write strobes for the DRAMs. One is supplied for each leaf to minimize signal loading. REFRESH Refresh in progress (Output; 12 mA, Active Low): This output gives notice that a refresh cycle is to be executed. The timing leads refresh RAS by one cycle. BUFFER CONTROLS Buffer control signals are provided to simplify the control of the interface between the DRAM and Am29030/35 data bus. Multiple operating modes facilitate choice of buffer type. Simple bus buffers (‘‘245’’s), bus latches (‘‘543’’s) and bus registers (‘‘646’’s) are all supported. Pin Description TX(A,B) Data Bus Transmit A and B (Output; Active Low): These outputs are multi-function signals. The signal names, as they appear on the logic symbol, are the default signal names (Mode e 0). The function of these outputs is to control buffers output enables during data read transactions and, in effect, control the multiplexing of data from each memory leaf onto the AM29030/35 data bus. LE(A,B) Data Bus Latch Enable A and B (Output; Active Low): The function of these outputs is mode independent although the timing of the signals change for different operational modes. These signals control transparent latches that hold data transmitted during a write transaction. In modes 0 and 1, the latch controls follow the timing of CAS for each leaf, while in modes 2 and 3 the timing of LEA and LEB is shortened to (/2 clock. 5 Functional Description lowed. If interleaved mode is selected, burst access is zerowait-state; if memory is non-interleaved, 1-wait-state burst access results. The NSBMC292 allows for flexibility in the control of data buffers to the memory array. Propagation delay is minimized by providing these controls directly, and design flexibility maximized by allowing the control strategy to be programmable. Buffers as diverse as 74FCT245, 74FCT543, 74FCT646, 74FCT853 and 74FCT861 may be used without additional glue logic. OVERVIEW The NSBMC292 couples the Am29030/35 interface to DRAM access protocols, generates bus buffer and data multiplexor controls and incorporates system and bus monitor timing resources. These functional elements are shown in Figure 1 . A maximum of 8 controllers may be included in a system, each managing up to 4 banks of memory. The NSBMC292 directly drives an array of fast page mode DRAMs. This array may be organized as 1 or 2 leaves of 32 bits each. Standard memory sizes from 256 kbit to 64 Mbit are supported and 8-, 16-, and 32-bit access are al- TL/V/11806 – 4 FIGURE 1. Functional Block Diagram 6 Functional Description (Continued) ed by the contents of the byte data field. Bits [1,0] are reserved and must be ‘‘0’’. The base address is fixed at 0x1f0f0000 while the BMC select field must match the value programmed at the ID[2..0] pins. In order to protect against accidental programming, the configuration registers can only be modified when the processor is in supervisor mode. CONFIGURATION AND CONTROL The NSBMC292 contains 64 bits of configuration data that controls it’s operational mode. The configuration is programmed by sending data on the address bus. Figure 2 shows the format of a configuration access. The byte select field determines which byte of the 64-bit field will be updat- TL/V/11806 – 5 FIGURE 2. Address Bus Fields Used to Access Configuration Data control bits. The block address, however, is constrained to start on a boundary that is an integer multiple of the block size. For example, if 1 Mb x 1 DRAMs are used, the memory block size is 8 MB and must start on an 8 MB boundary. BLOCK ADDRESS FIELD Once configured, a NSBMC292 responds to access requests within the programmed block address range. The programmed value sets the starting address of the block, while the size of the block is determined by the DRAM size TL/V/11806 – 6 FIGURE 3. Configuration Register Control Fields 7 Functional Description (Continued) TABLE II. Interpretation of the Buffer Control Signals for Various Control Modes CYCLE EXTEND In order to maximize the choice of memory device speeds that may be used for various system clock rates, the Row Address Strobe (RAS) period for a basic access may be programmed for either 3 or 4 clock cycles. When cleared to ‘‘0’’, configuration bit 20 indicates that 3 clock cycles (2 wait states) are to be used, when set to ‘‘1’’, 4 clock cycles or 3 wait states are required. Setting bit 20 to ‘‘1’’ also has the effect of increasing the RAS pre-charge time by 1 clock cycle. Calculation of the number of cycles required per access type is detailed in the NSBMC292 Application Guide. ROW ADDRESS HOLD Bit 18 of the configuration register controls the time at which the memory address switches from row to column address. This allows the designer to control the address hold time relative to RAS so that the slowest memory can be used for a range of clock speeds. Setting Bit 18 to ‘‘1’’ yields the maximum row address hold time, clearing it shortens the row address hold in favor of additional column address setup. INTERLEAVE DISABLE In cost sensitive applications, it is sometimes desirable for a system to operate with a single bank of memory so as to reduce the minimum memory required. In this case the interleave mode bit is programmed to ‘‘1’’. If a second bank of memory is added, this bit can be programmed to ‘‘0’’ to enable interleave operation and peak performance. In noninterleave mode a burst access is completed in 3 clock cycles for the initial accrss and two cycles thereafter (bit 20 e 0), or four cycles for the initial access and 3 cycles thereafter with bit 20 e 1. Systems that are configured for non-interleave operation should be designed so that only the leaf A signals are used. The NSBMC292 does not explicitly support 16-bit memory systems, however, if the simple expedient of re-arranging the address input signals is done, 16-bit support is easily achieved. Configurations such as 16-Bit interleaved memory systems are possible, however, since the device count for this configuration is identical to 32-Bit non-interleaved, but the performance is better for the 32-Bit system, it is recommended that the 32-Bit configuration be used in this case. BUFFER CONTROL MODE FIELD The transfer of Data from the memory subsystem to the AM29030/35 bus occurs through buffers controlled by the NSBMC292. Two of the signals (LEA, LEB) provide transparent latch controls for use during write cycles. LEA and LEB have variable timing but fixed interpretation. The other two signals, TXA and TXB, change in both timing and function according to programmed mode. Table II presents these signals using names that are function derived. Signals containing TX are transmit controls for buffers that have output enables (transmit from the memory system). Buffers such as ‘‘245’’s or ‘‘646’’s, which have direction and enable pins, are controlled by CE (chip enable) in modes 1 and 3. Signals ending with A or B are specific to one or the other of the two leaves of memory controlled by the NSBMC292. Signals without suffixes apply to both leaves. The signal LeafB/*A, required in some configurations, indicates which memory leaf will be selected on the next clock cycle. Mode Signal 1 Signal 2 0 1 2 3 TXA CEA TX CE TXB CEB LeafB/*A LeafB/*A Table III presents some of the possible configurations with the corresponding mode settings. For a comprehensive discussion of the selection of a buffer strategy, refer to the NSBMC292 Application Guide. TABLE III. Possible NSBMC292 Memory/Buffer Configurations Buffer Type DRAM Type Buffer Mode 74FCT646 Am29C983 74FCT543 Nibble Bit Bit Mode 3 Mode 2 Mode 0 For the memory/buffer combinations presented in Table III, RDY is returned after two cycles (1 wait state) for a simple write and after 3 cycles (2 wait states) for an initial simple read. Subsequent access in a burst occur at the rate of one per clock cycle. DRAM SIZE FIELD This three bit field, bits 12 – 14, selects the DRAM device address size, and consequently, memory block size. Note that the memory in both leaves of a bank are required to be of the same size and organization for correct operation. Table IV lists the size codes and the corresponding device sizes. TABLE IV. Size Code Settings, DRAM Density and Address Range Size Memory Size Code Memory Block Size Max Banks Memory Types 000 001 010 011 2 MB 8 MB 32 MB 128 MB 1 1 1 1 256 kb x 1 1 Mb x 1 4 Mb x 1 16 Mb x 1 100 101 110 111 2 MB 8 MB 32 MB 128 MB 4* 4* 4* 4* 64 kb x 4 256 kb x 4 1 Mb x 4 4 Mb x 4 *Note that banks are sequentially addressed within a block. REFRESH RATE FIELD The system clock frequency is used to derive the period of DRAM refresh cycles. The refresh rate is calculated as (PCLK clock frequency) / (16 x (programmed value a 1)). If, for example, the system clock is 25 MHz and the programmed value is 24, the NSBMC292 will execute the 256 refresh cycles for a 256k DRAM in 4.096 ms. The algorithm employed by the NSBMC292 guarantees the time for complete device refresh, however, individual row refresh may be delayed so as not to pre-empt bursts in 8 Functional Description (Continued) The bus monitor operates by monitoring the state of the PRDY signal. Should it be asserted for longer than the programmed Bus Time Out value in configuration register 7, BERR is asserted if configuration bit 62 is set. The ERR signal is timed in similar fashion to the RDY signal. The PRDY signal is to be connected directly to the RDY input of the processor. This signal is pinned-out separately from the RDY signal so that the bus monitor operates correctly even if RDY to the processor is driven from multiple sources combined through a logic gate. If the RDY signal is generated through a ‘‘wire-OR’’ then PRDY is physically identical to the RDY output from the NSBMC292. OPERATION CONTROL FIELD Byte 0 of the configuration register contains three fields. The first field (from LSB) is reserved for test purposes and must be zero for proper in-circuit operation. The second field is the operation control field which is used to control the state of the page cache, timer, interrupts and bus error signal. The third field is the low two bits of the refresh rate. The NSBMC292 has been designed such that if any of the bits in the operation control field is written with a ‘‘1’’, access to the other two fields is disabled and the previous value is retained. If all bits in the operation control field are ‘‘0’’, the reserved and refresh rate fields are updated from the current input. Since the control register is accessed as a byte, automatic masking of the non-control field bits simplifies programming of the control parameters. All parameters in this field may be modified on-the-fly, and all functions are disabled by reset. The operational controls have been encoded such that any access to the register will only modify one parameter. progress. Since the maximum burst is 258 clock cycles in length, this delay in no way endangers data integrity. Access to devices other than NSBMC292 controlled memory are not delayed by refresh, access to memory while refresh is in progress are completed once the refresh cycle is complete. TIMER CONTROL FIELD The 24-bit timer is a counter which scales PCLK by a programmable amount and automatically reloads when terminal count is reached. The contents of the timer cannot be read directly, however, the counter will generate an interrupt when terminal count is reached. The timer is disabled following a RESET and the Timer Count Value (Configuration Bytes 4 – 6) must be programmed before the timer is enabled. The interrupt output is asserted low when terminal count is reached and interrupt will remain asserted until the Acknowledge Timer Interrupt op-code is written to configuration byte 0. This timer is intended to be used either as a system heart beat or part of a system WATCHDOGTM . This frees the internal timer to be used for real-time critical tasks. BUS MONITOR CONTROL FIELD The NSBMC292 contains circuitry that monitors all bus access requests regardless of the target address. Access made to a region configured for external ready can hang the processor if for some reason READY is not returned to terminate the access. The NSBMC292 can detect such a condition and if the bus watch feature is enabled, will return ERR. 7 6 5 Bit 4 3 2 1 0 D X X X X X X X D X X X X X X X 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 0 D X X X X X X X D X X X X X X X 0 0 1 0 1 0 1 0 Control Function Update Bits 0,1, 6 and 7 with data D Data Access Page Cache Disable (Default) Data Access Page Cache Enable Instruction Access Page Cache Disable (Default) Instruction Access Page Cache Enable Acknowledge Timer Interrupt Enable Timer Interrupt Output Disable Timer Interrupt (Default) 9 Functional Description (Continued) For systems in which Instruction and data spaces are controlled by independent NSBMC292s, the page cache management can be used to greater effect as data and instruction ‘‘run length’’ ceases to be a factor in determining performance. In this type of configuration cache efficiency is simply a function of locality of reference and a control strategy for the page cache mechanism is much simpler to derive and implement. PCache management is independently controlled for instruction and data access. A recommended starting strategy for improving performance of mixed instruction/data systems is to rely on the burst mechanism and the internal cache for instruction fetching, and enable PCache for Data access only. This general rule of thumb can be improved on, once program behavior is benchmarked. PAGE CACHE MANAGEMENT The Page Cache management implemented by the NSBMC292 incorporates a mechanism whereby advantage can be taken of the page access mode of DRAMs, not only for burst access, but also for non-sequential data and instruction access. The mechanism relies on the fact that as long as RAS is asserted, access to the selected row can be gained by simply asserting a column address and the CAS strobe. The resulting access is slower than a burst only by the amount of time required to ensure that the desired address is in the same row as was previously selected. The benefits of this type of access are obvious, however, there can be drawbacks. If the required address does not reside in the same page as that selected, the currently selected row must be released and the new row selected before the access can proceed. The process of de-selecting a row and selecting a new one requires that the RAS precharge time be allowed to expire before the selection of a new row can begin. This pre-charge time can require up to two additional cycles over a standard access startup. The efficiency of this type cache (PCache) is related to a large extent on the locality of reference of the datum being accessed. For systems that have mixed Instruction and Data memory systems, PCache efficiency is very dependant on the behavior of the program being executed as related to the ‘‘run-length’’ of data and instruction access, the processor internal cache utilization, and the locality of data and instruction references. Since throughput is lowered by cache misses, the page cache can be dynamically enabled/ disabled for instruction and/or data access. In this manner the programmer can apply the mechanism judiciously in order to maximize throughput. Typical Application System Clock: Refresh Rate: Memory Size: Buffer Mode: 25 MHz 16 ms per row (0 c 18) 256k x 4 (Size e 5) Signal 1 e TX, Signal 2 e Leaf B/*A (Mode 2) Interleave: Enabled Row Address Hold: (/2 clock cycle (Row Address Hold e 0) Extended Access: Base Address: BMC ID: Disabled (3 clock RAS derived from tRSHL of NSBMC292, RAS access time of DRAM, buffer delay of 74FCT16543 and setup time of the processor’s data inputs) 8MB (0b00000000100) 0 Required Configuration for startup 00000000 10000001 01010110 00000000 (0x00815600) Configuration Setup 0x1F0F0000 (0x10F0000, 0); /* Config. bits 7..0 e 0 */ /* Config. bits 15..8 e 0 */ 0x1F0F00558 (0x1F0F0400 a (0x56 m 2), 0); /* Config. bits 23..16 e 0 */ 0x1F0F00A24 (0x1F0F0800 a (0x89 m 2), 0); 0x1F0F00C00 (0x1F0F0C00, 0); /* Config. bits 31..24 e 0 */ 10 Typical Application (Continued) they can be connected directly to the appropriate inputs of the processor and requires only a small pull-up resistor to keep them de-asserted when in the high impedance state. The ease with which the NSBMC292 may be integrated into a system design is illustrated in the diagram in Figure 4 . The system shown supports an Am29030/35 with between 2 MB and 128 MB of memory, depending on the devices selected, managed by a singIe NSBMC292. This specific example accommodates 256 kb x 4, 1 Mb x 4 or 4 Mb x 4 devices. Connection of the NSBMC292 to the Am29030/35 processor is accomplished simpIy by wiring together pins with the same names. The only exceptions RDY and ERR. If the NSBMC292 is the only device that generates these signals, If multiple processor peripherals are connected to RDY or ERR, 3-state drivers shouId be used in such a manner that the signals are actively de-asserted prior to the driver being placed in its’ high impedance state. If this rule is followed, a simple ‘‘wire or’’ can be used. Alternately, all sources of RDY and ERR can be combined using multiple input gates and the processor signals driven by the outputs. TL/V/11806 – 7 FIGURE 4. Possible System Interconnection Using NSBMC292 11 Absolute Maximum Ratings Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage (VIN) D.C. Input Current (IIN) Storage Temperature ( O STG) All Voltages Referenced to Ground Supply Voltage (VCC) Ambient Temperature Range ( O A) Plastic Package Ceramic Package b 0.3V to a 7V b 0.3V to VCC a 0.3V g 50 mA 4.5V to 5.5V b 0§ C to a 70§ C b 55§ C to a 85§ C b 65§ C to a 150§ C DC Electrical Characteristics Ý 1 Symbol VIL Description Conditions Low Level Input Voltage VCC e 4.75V Min Max Units 1.4 V 2 VIH High Level Input Voltage VCC e 5.25V 3 IIL Low Level Input Current VIN e VSS, VCC e 5.25V 4 IIH High Level Input Current VIN e VCC e 5.25V 10 mA 5 VOL Low Level Output Voltage VIN e VIL or VIH IOL e 24 mA 0.4 V 6 VOH High Level Output Voltage VIN e VIL or VIH IOL e 24 mA 3.7 V 7 IOZL Low Level TRI-STATEÉ Output Current VIN e VIL or VIH VO e VSS b 20 mA 8 IOZH Low Level TRI-STATE Output Current VIN e VIL or VIH VO e 5.25V 20 mA 9 ICCMax Maximum Supply Current Continuous Simple Access Continous Burst Access 100 30 mA 10 CIN Input Capacitance 20 pF 11 COUT Output Capacitance 20 pF 12 3.7 V b 10 mA Timing Parameters INTERFACE TIMING SIMPLE ACCESS TIMING The NSBMC292 interface to the Am29030/35 has been designed for direct interconnect. It is not necessary to place other logic devices between the processor and the NSBMC292, nor is their use encouraged. The introduction of intermediate address or control signal buffers can result in skews or delays that will require the system clock frequency to be derated for operation under worst case conditions. The timing diagrams presented in this section assume that all signals between the processor and the NSBMC292 are un-buffered. The NSBMC292 can return data to the processor in only 3 clock or 4 clock cycles for a basic access (2 or 3 wait states) depending on the mode chosen (Configuration Bit 20). If multiple access cycles are requested back to back then the BMC will pause for a minimum of 2 clocks between RAS cycles to insure that the RAS pre-charge time is met resulting in 5 or 6 clocks between successive simple cycles. Figure 6 shows the timing relationship between the system clock, processor control signals and NSBMC292 outputs. All NSBMC292 outputs are derived synchronously with the exception of tARA (processor address to row address delay). Two simple access cycles are shown in the diagram. The first is a read cycle that assumes that the NSBMC292 was idle prior to the start of the cycle, the second is backed onto the first to show the effect of RAS pre-charge imposed by NSBMC292. If bit 20 is set to ‘‘1’’, a wait state will be inserted after cycles T3 and T8. REFRESH TIMING Figure 5 details the timing of the RAS only refresh performed by the memory controller when there is a competing request from a bus master. A competing request is defined as any request that occurs between T0 and T5. For any request in this range, the timing is exactly as shown. As illustrated, the diagram represents the timing that results when bit 20 of the configuration register is cleared to zero. If bit 20 is set to ‘‘1’’, an additional cycle is inserted at T3 and T8. BURST ACCESS TIMING When a burst access is requested by the processor, the NSBMC292 generates the sequence in Figure 7 . If the burst is, for example 2 words long, the processor de-asserts BURST in T5 and the sequence terminates in T6. The first access of the burst sequence begins in the same manner as a simpIe access. Consequently the timing parameters from Figure 6 may be applied in Figure 7 . TL/V/11806 – 8 FIGURE 5. Refresh Timing 13 Timing Parameters (Continued) TL/V/11806 – 9 FIGURE 6. Basic Access Timing TL/V/11806 – 10 FIGURE 7. Burst Access Timing 14 Timing Parameters (Continued) TL/V/11806 – 11 FIGURE 8. Burst Access w/t PCache Hit Figures 8 and 9 show the sequence of events that can occur when PCache is enabled. The sequence in Figure 8 shows two back-to-back in the same page. This type of sequence yields the highest data transfer rate achievable with DRAM. Figure 9 shows the worst case scenario. This example shows two back-to-back simple access to different rows with PCache is enabled. This is an example of the slowest transfer sequence that may occur. TL/V/11806 – 12 FIGURE 9. Simple Access w/t PCache Miss 15 AC Timing Parameters (Unless otherwise stated VCC e 5.0V g 5%, 0§ C k TA k 70§ C.) Ý Symbol 16 MHz Description Min Max 25 MHz Min Max 33 MHz Min Units Max 1 tRQSU Request Input Setup Time 14 12 9 ns 2 tSU Synchronous Input Setup 14 12 9 ns 3 tH Synchronous Input Hold 4 tBSU Burst Input Setup 5 tBH Burst Input Hold 3 3 3 ns 6 tRZH RDY 3-State to Valid Delay Relative to *MEMCLK 29 24 19 ns 7 tRHL RDY Synchronous Assertion Delay 26 21 17 ns 8 tRLH RDY Synchronous De-assertion Delay 25 20 16 ns 9 tRHZ RDY Valid to TRI-STATE Delay Relative to *MEMCLK 27 22 17 ns 10 tARA Address Input to Row Address Output Delay (Note 1) 23 19 15 ns 11 tRAH *MEMCLK or MEMCLK to Row Address Hold 40 33 26 ns 12 tCAV *MEMCLK or MEMCLK to Column Address Valid (Note 1) 38 31 25 ns 13 tCAH MEMCLK to Column Address Hold 4 4 4 ns 14 tDRAH DRAM Row Address Hold (Note 2) tM-4 tM-4 tM-4 ns 15 tRSHL MEMCLK to RAS Asserted Delay (Note 1) 29 24 19 ns 16 tRSLH MEMCLK to RAS De-asserted Delay (Note 1) 26 21 17 ns 17 tCHL MEMCLK to CAS Asserted Delay (Note 1) 23 19 15 ns 18 tCLH MEMCLK to CAS De-asserted Delay (Note 1) 20 16 13 ns 19 tBHL MEMCLK to Buffer Control Asserted Delay (Note 1) 17 ns 20 tBLH MEMCLK to Buffer Control De-asserted Delay (Note 1) 21 tBSV MEMCLK to Bank Select Valid Time (Note 1) 22 tBSH MEMCLK to Bank Select Hold Time (Note 1) 23 tWEHL *MEMCLK to Write Enable Asserted Delay (Note 1) 31 25 20 ns 24 tWELH MEMCLK to Write Enable De-asserted Delay (Note 1) 28 22 18 ns 25 tCAH *MEMCLK to Column Address Hold Time (Burst) (Note 1) 26 tCAV *MEMCLK to Column Address Valid Delay (Burst) (Note 1) 29 23 19 ns 27 tLEHL *MEMCLK to Latch Enable Assertion 23 19 15 ns 28 tLELH MEMCLK to Latch Enable De-assertion 20 16 13 ns 29 tRFA MEMCLK to Row Address Valid (Refresh) 38 31 25 ns 30 tRFH MEMCLK to Row Address Hold (Refresh) 31 tRFHL REFRESH Synchronous Assertion Delay 20 16 13 ns 32 tRFLH REFRESH Synchronous De-assertion Delay 20 16 13 ns 3 14 12 26 4 23 4 Signal output delays are measured relative to MEMCLK (except as indicated) using a 50 pF load. Note 2: tM e MEMCLK High time when configuration bit 18 e 0. tM e MEMCLK cycle time e 1/(MEMCLK frequency) for configuration bit 18 e 1. Timing for Rev A silicon. 16 9 19 4 21 4 5 3 21 4 26 15 ns 17 ns ns 4 4 ns ns 4 5 4 Note 1: Derate the given delays by 0.06 ns per pF of load in excess of 50 pF. 3 ns 4 ns Errata for the V292BMC A full set of CUPL style PAL equations would be as follows: /*The ‘!‘ symbol on a pin indicates a physical low true signal*/ Pin !reg /*Request Signal Input from Am29030*/ Pin !rdy /*Ready Signal Input from Am29030*/ Pin !burst /*Burst Signal Input from Am29030*/ Pin !reg bmc /*Request Signal Output to V292BMC*/ Pin !reg enable /*Request Enable Signal Output for Internal Use*/ /*Equations for Low Speed Operation. The critical timing chain is *max CLOCK to RDY delay a max RDY to REQ BMC delay a max REQ BMC to clock setup TL/V/11806 – 13 */ req bmc 4 reg & !rdy; /*Equations for High Speed Operation. The critical timing chain is *max CLOCK to REQ delay a max REQ to REQ BMC delay a max REQ BMC to clock setup TL/V/11806 – 14 */ req enabled e !req # rdy & !burst; /*Input to D type flip-flop*/ e req & req enable; req bmc A second erratum for the V292BMC is When the V292BMC is programmed for extended timing mode operation, back to back memory read cycles or back to back memory write cycles will fail. The recommended fix would be as follows: req enabled e !reg # !rdy; /*Input to D type flip-flop*/ e req & req enable; req bmc This will cause a 1 cycle delay to be added from the end of one request (as indicated by !RDY) and the beginning of the next request. Ordering Information NS BMC National Semiconductor 292 VF - 33 Packaging VF Ð 132-Lead PQFP Mode Burst Mode Controller Frequency 16 MHZ 25 MHz 33 MHz Processor AMD 29030/35 17 NSBMC292-16/-25/-33 Burst Memory Controller Physical Dimensions inches (millimeters) LIFE SUPPORT POLICY 132-Pin Plastic Quad Flatpak (PQFP) Order Number NSBMC292VF NS Package Number VF132A NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.