HD-4702 CMOS Programmable Bit Rate Generator March 1997 Features Description • HD-4702 Provides 13 Commonly Used Bit Rates The HD-4702 Bit Rate Generator provides the necessary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using an on-chip crystal oscillator or an external input. For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be 2.4576MHz (i.e. 9600 Baud x 16 x 16, since there is an internal ÷ 16 prescaler). A lower input frequency will result in a proportionally lower output frequency. The HD-4702 can provide multi-channel operation with a minimum of external logic by having the clock frequency CO and the ÷ 8 prescaler outputs Q0, Q1, Q2 available externally. All signals have a 50% duty cycle except 1800 Baud, which has less than 0.39% distortion. The four rate select inputs (S0-S3) select which bit rate is at the output (Z). See Truth Table for Rate Select Inputs for select code and output bit rate. Two of the 16 select codes for the HD-4702 do not select an internally generated frequency, but select an input into which the user can feed either a different frequency, or a static level (High or Low) to generate “ZERO BAUD”. The bit rates most commonly used in modern data terminals (110, 150, 300, 1200, 2400 Baud) require that no more than one input be grounded for the HD-4702, which is easily achieved with a single 5-position switch. The HD-4702 has an initialization circuit which generates a master reset for the scan counter. This signal is derived from a digital differentiator that senses the first high level on the CP input after the ECP input goes low. When ECP is high, selecting the crystal input, CP must be low. A high level on CP would apply a continuous reset. See Clock Modes and Initialization below. • Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate) • Low Power Dissipation • Conforms to EIA RS-404 • One HD-4702 Controls up to Eight Transmission Channels • Initialization Circuit Facilitates Diagnostic Fault Isolation • On-Chip Input Pull-Up Circuit Ordering Information TEMP. RANGE (oC) PACKAGE PART NUMBER PKG. NO. PDIP -40 to +85 HD3-4702-9 E16.3 CERDIP -40 to +85 HD1-4702-9 F16.3 SMD# -55 to +125 5962-9051801MEA F16.3 Truth Table Pinout TRUTH TABLE FOR RATE SELECT INPUTS (Using 2.4576MHz Crystal) S3 S2 S1 S0 L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H HD-4702 (CERDIP, PDIP) TOP VIEW OUTPUT RATE (Z) MUX Input (IM) MUX Input (IM) 50 Baud 75 Baud 134.5 Baud 200 Baud 600 Baud 2400 Baud 9600 Baud 4800 Baud 1800 Baud 1200 Baud 2400 Baud 300 Baud 150 Baud 110 Baud Q0 1 16 VCC Q1 2 15 IM Q2 3 14 S0 ECP 4 13 S1 CP 5 12 S2 OX 6 11 S3 IX 7 GND 8 10 Z 9 CO NOTE: 19200 Baud by connecting Q2 to IM. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 5-1 File Number 2954.1 HD-4702 Pin Description PIN NUMBER TYPE SYMBOL DESCRIPTION 16 VCC VCC: Is the +5V power supply pin. A 0.1µF capacitor between pins 16 and 8 is recommended for decoupling. 8 GND GROUND 5 I CP EXTERNAL CLOCK INPUT 4 I ECP EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be generated from the CP input. 7 I IX CRYSTAL INPUT 6 O OX CRYSTAL DRIVE OUTPUT 15 I IM MULTIPLEXED INPUT 11, 12, 13, 14 I S0 - S3 9 O CO 1, 2, 3 O Q0 - Q2 10 O Z BAUD RATE SELECT INPUTS CLOCK OUTPUT SCAN COUNTER OUTPUTS BIT RATE OUTPUT CLOCK MODES AND INITIALIZATION IX ECP CP H L X L X H X L OPERATION Clocked from IX Clocked from CP H Continuous Reset Reset During 1st CP = High Time H = HIGH Level L = LOW Level X = Don’t Care = Clock Pulse = 1st HIGH Level Clock Pulse after ECP goes LOW NOTE: Actual output frequency is 16 times the indicated Output Rate, assuming a clock frequency of 2.4576MHz. 5-2 IX 6 OX 4 ECP 5 CP CP MR ÷ 8 CP MR 15 14 13 12 11 IM S0 S1 S2 S3 9600 4800 2400 1200 600 300 150 75 7 MULTIPLEXER COUNTER NETWORK SCAN COUNTER Block Diagram (NOTE) OSCILLATOR CIRCUIT 0 CP CP D ÷ 4 ÷ 18 Q MR Q MR Q CP ÷ 6 Q MR 2 50 3 75 4 134.5 5 200 6 600 7 2400 8 9600 9 4800 MR INITIALIZATION CIRCUIT CP ÷ 16/3MRQ 10 1800 11 1200 12 2400 13 300 CO 14 150 Q0 Q1 Q2 CP 9 1 2 VDD = PIN 16 VSS = PIN 8 = PIN NUMBER NOTE: See Figure 4 in Design Information for Crystal Specifications. 3 ÷ 22 Q MR 15 110 10 D Q Z FF CP MR HD-4702 5-3 FF CP Q MR 1 HD-4702 Application Information Other bit rate combinations can be generated by changing the Scan Counter to Selector interconnection or by inserting logic gates into this path. Single Channel Bit Rate Generator Figure 1 shows the simplest application of the HD-4702. This circuit generates one of five possible bit rates as determined by the setting of a single pole, 5-position switch. The Bit Rate Output (Z) drives one standard TTL load or four low power Schottky loads over the full temperature range. The possible output frequencies correspond to 110, 150, 300, 1200, and 2400 Baud. For many low cost terminals, these five bit rates are adequate. 1 S0 S2 S2 S3 Q2 Z HD-4702 OX CO Q0 Q1 2.4576 MHz CRYSTAL 4 S1 S1 IX † 10M 56pF 5 3 S0 ECP 56pF SPST SWITCH 2 IM IM CP S3 CP Q1 Q2 Z 150 Q0 300 CO 2.4576 MHz CRYSTAL 2400 OX 1200 IX 1800 † 4800 10M 110 56pF A0 D E 93L34 A1 A2 CL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 HD-4702 9600 ECP 56pF † See Table 1. OUTPUT FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH EIGHT SIMULTANEOUS FREQUENCIES † See Table 1. 19200 Baud Operation SWITCH POSITION HD-4702 BIT RATE 1 110 Baud 2 150 Baud 3 300 Baud 4 1200 Baud 5 2400 Baud Though a 19200 Baud signal is not internally routed to the multiplexer, the HD-4702 can be used to generate this bit rate by connecting the Q2 output to IM input and applying select code. An additional 2-input NOR gate can be used to retain the “Zero Baud” feature on select code 1 for the HD-4702 (See Figure 3). FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR CONFIGURATION PROVIDING FIVE BIT RATES IM Simultaneous Generation of Several Bit Rates Figure 2 shows a simple scheme that generates eight bit rates on eight output lines, using one HD-4702 and one 93L34 Bit Addressable Latch. This and the following applications take advantage of the built-in scan counter (prescaler) outputs. As shown in the block diagram, these outputs (Q0 to Q2) go through a complete sequence of eight states for every halfperiod of the highest output frequency (9600 Baud). Feeding these Scan Counter Outputs back to the Select Inputs of the multiplexer causes the HD-4702 to interrogate sequentially eight different frequency signals. The 93L34 8-bit addressable Latch, addressed by the same Scan Counter Outputs, re-converts the multiplexed single Output (Z) of the HD-4702 into eight parallel output frequency signals. In the simple scheme of Figure 2, input S3 is left open (HIGH) and the following bit rates are generated: ECP 56pF 10M 56pF Q1: 9600 Baud Q2: 4800 Baud Q3: 1800 Baud Q4: 1200 Baud Q5: 2400 Baud Q6: 300 Baud Q7: 150 Baud S1 S2 S3 OX CO Q0 Q1 Q2 Z OUTPUT † See Table 1. FIGURE 3. 19200 BAUD OPERATION TABLE 1. CRYSTAL SPECIFICATIONS PARAMETERS Frequency Unwanted Modes 5-4 † HD-4702 IX 2.4576 MHz CRYSTAL Series Resistance (Max) Q0: 110 Baud S0 CP TYPICAL CRYSTAL SPEC 2.4576MHz “AT” Cut 250 -6.0dB (Min) Type of Operation Parallel Load Capacitance 32pF +0.5 HD-4702 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . . 1mA/MHz Increase in ICCOP Thermal Resistance (Typical) θJA θJC CERDIP Package . . . . . . . . . . . . . . 78oC/W 23oC/W PDIP Package . . . . . . . . . . . . . . . . . 90oC/W N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V DC Electrical Specifications Operating Temperature Range HD-4702-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC HD-4702-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8) LIMITS SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Input High Voltage VCC 70% - V VCC = 4.5V VIL Input Low Voltage - VCC 30% V VCC = 4.5V VOH1 Output High Voltage VCC -0.1 - V IOH ≤ -1µA, VCC = 4.5V, (Note 1) VOL1 Output Low Voltage - 0.1 V IOL ≤ +1µA, VCC = 4.5V, (Note 1) IIH Input High Current -1 +1 µA VIN = VCC, All 0ther Pins = 0V, VCC = 5.5V IILX Input Low Current (lX Input) -1 +1 µA VIN = 0V, All Other Pins = VCC, VCC = 5.5V IIL Input Low Current (All Other Inputs) - -100 µA VIN = 0V, All Other Pins = VCC, VCC = 5.5V (Note 2) IOHX Output High Current (OX) -0.1 - mA VOUT = VCC - 0.5, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOH1 Output High Current (All Other Outputs) -1.0 - mA VOUT = 2.5V, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOH2 Output High Current (All Other Outputs) -0.3 - mA VOUT = VCC -0.5, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOLX Output Low Current (OX) 0.1 - mA VOUT = 0.4V, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOL Output Low Current (All Other Outputs) 1.6 - mA VOUT = 0.4V, VCC = 4.5V Input, at 0V or VCC per Logic Function or Truth Table ICC Supply Current (Static) - 1500 µA ECP = VCC, CP = 0V, VCC = 5.5V, All Other Inputs = GND, (Note 2) - 1000 µA ECP = VCC, CP = 0V, VCC = 5.5V, All Other Inputs = VCC, (Note 2) NOTES: 1. Interchanging of force and sense conditions is permitted. 2. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs except IX. 5-5 HD-4702 AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8) LIMITS SYMBOL tPLH AC PARAMETER Propagation Delay, IX to CO tPHL tPLH Propagation Delay, CP to CO tPHL tPLH Propagation Delay, CO to Qn tPHL tPLH Propagation Delay, CO to Z tPHL tTLH Output Transition Time (Except OX) tTHL ts Set-Up Time, Select to CO th Hold Time, Select to CO ts Set-Up Time, IM to CO th Hold Time, IM to CO MIN MAX UNITS - 350 ns - 275 ns - 260 ns - 220 ns - (Note 2) ns - (Note 2) ns - 85 ns - 75 ns - 160 ns - 75 ns 350 - ns 0 - ns 350 - ns 0 - ns twCP(L) Minimum Clock Pulse Width, Low (Notes 3, 4) 120 - ns twCP(H) Minimum Clock Pulse Width, High (Notes 3, 4) 120 - ns twCP(L) Minimum IX Pulse Width, Low (Note 4) 160 - ns twCP(H) Minimum IX Pulse Width, High (Note 4) 160 - ns - 300 ns - 250 ns - 215 ns - 195 ns - (Note 2) ns - (Note 2) ns - 75 ns - 65 ns - 80 ns - 40 ns tPLH Propagation Delay IX to CO tPHL tPLH Propagation Delay CP to CO tPHL tPLH Propagation Delay CO to Qn tPHL tPLH Propagation Delay CO to Z tPHL tTLH Output Transition Time (Except OX) tTHL TEST CONDITIONS VCC = 4.5V CL ≤ 7pF on OX CL = 50pF (Note 1) VCC = 4.5V CL ≤ 7pF on OX CL = 15pF (Note 1) NOTES: 1. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Setup Times (ts), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance. 2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be ≤ 367ns. 3. The first High Level Clock Pulse after ECP goes Low must be at least 350ns long to guarantee reset of all Counters. 4. It is recommended that input rise and fall times to the clock inputs (CP, IX) be less than 15ns. 5-6 HD-4702 Capacitance TA = +25oC; Frequency = 1MHz SYMBOL CIN COUT PARAMETER TYPICAL UNITS Input Capacitance 7 pF Output Capacitance 15 pF CONDITIONS All measurements are referenced the device GND Switching Waveforms tW(H) tW(L) 50% 50% 50% CP/IX 50% CO ts IM/SN th 50% NOTE: 1. Setup and Hold times are shown as positive values but may be specified as negative values. AC Testing Input, Output Waveform INPUT OUTPUT VOH VIH 50% 50% VIL VOL NOTE: 1. AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 5-7 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029