ETC NTH4302/D

NTH4302
Product Preview
HD3e Quad N−Channel
The NTH4302 is the first integrated Quad FET in a single package.
It is the integration of 4 planar TMOS devices. It uses the latest HD3e
TMOS technology from ON Semiconductor, with very high cell
density and improved switching capability
The NTH4302 is a 16-pin leadless device packaged in the new
PInPAK from ON Semiconductor. The PInPAK is a new flexible
power package that uses the MAP process. The NTH4302 uses the
same MOSFET as the NTD60N02R. However, with the PInPAK
package, various other pairs of MOSFETs can be used to create
additional custom applications.
Features
• Ultra Low RDS(on) Provides Higher Efficiency
• Very Fast Switching due to Planar Technology and Leadless Package
• 200% Footprint Reduction Compared to Similar DPAK Solution for
•
•
•
the Same Power
Up to 80 Amp per FET
Very Low Vf (0.8 mV) Ideal for Synchronous Rectification
Specifically Designed for DC-DC Buck Converter in VRM9.1
Application (80 Amp Per Phase, 500 khz)
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QUAD TMOS POWER MOSFET
40 AMPERES
24 VOLTS
RDS(on) = 7.5 m
Ciss = 2050 pF
RJC = 1.3 C/W
MARKING
DIAGRAM
TBD
CASE TBD
PInPAK
Application
•
•
•
•
•
DC-DC Converter
Motherboard/Server Buck Converter
Telecom/Industrial Power Supply
Automotive Motor Drive
H-Bridge
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
PINOUT DIAGRAM
Application Note AND8086/D, “Board Mounting Notes for Quad Flat-Pack
No-Lead Package (QFN)”, is available on our web site www.onsemi.com.
TBD
ORDERING INFORMATION
Device
NTH4301
Package
Shipping
ONiPAK
TBD
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
 Semiconductor Components Industries, LLC, 2003
January, 2003 - Rev. 0
1
Publication Order Number:
NTH4301/D
NTH4302
VCCC
VCCC
VCC
D1
D2
D1
G2
G1
G1
S1
S2
S1
M
Out
D2
D4
D3
G4
G3
D2
S2
S4
S3
Figure 1.
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain-to-Source Voltage
VDSS
24
Vdc
Drain-to-Gate Voltage
VDGR
24
Vdc
VGS
±20
Vdc
TJ and Tstg
-55 to 150
°C
EAS
450
mJ
ID
ID
Adc
IDM
30
TBD
TBD
PD @ TA = 25°C
TBD
W
mW/°C
RθJC
RθJA
RθJA
1.5
30
TBD
°C/W
Rating
Gate-to-Source Voltage
Operating and Storage Temperature
Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25°C (Note 1)
(VDD = 25 Vdc, VGS = 5 Vdc, L = 0.1 mH, IL(pk) = 20 A, Rg = 1 K)
Drain Current
- Continuous @ TA = 25°C
- Continuous @ TA = 70°C
- Single Pulse (tp 10 s)
Total Power Dissipation, t 10 seconds
Linear Derating Factor
Thermal Resistance
- Junction-to-Case
- Junction-to-Ambient
- Junction-to-Ambient (Note 1)
1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2).
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2
NTH4302
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
24
-
25
-
-
-
1.0
10
-
-
±100
1.0
-
1.9
-3.8
3.0
-
-
0.0078
0.0078
0.010
0.010
0.010
0.013
gFS
-
20
-
Mhos
Ciss
-
2050
2400
pF
Coss
-
640
800
Crss
-
225
310
td(on)
-
11
20
OFF CHARACTERISTICS
V(BR)DSS
Drain-to-Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 A)
Positive Temperature Coefficient
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = 30 Vdc, TJ = 125°C)
IDSS
Gate-Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Negative Threshold Temperature Coefficient
Static Drain-to-Source On-Resistance
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 4.5 Vdc, ID = 5.0 Adc)
Vdc
RDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn-On Delay Time
Rise Time
Turn-Of f Delay Time
(VDD = 25 Vdc, ID = 1.0 Vdc,
VGS = 10 Adc, RG = 6.0 )
Fall Time
Turn-On Delay Time
Rise Time
Turn-Of f Delay Time
(VDD = 25 Vdc, ID = 1.0 Vdc,
VGS = 10 Adc, RG = 2.5 )
Fall Time
Turn-On Delay Time
Rise Time
Turn-Of f Delay Time
(VDD = 24 Vdc, ID = 20 Vdc,
VGS = 10 Adc, RG = 2.5 )
Fall Time
Gate Charge
g
(VDS = 24 Vdc,
Vd ID = 2.0
2 0 Adc,
Ad
VGS = 10 Vdc)
tr
-
15
25
td(off)
-
85
130
tf
-
55
90
td(on)
-
11
20
tr
-
13
20
td(off)
-
55
90
tf
-
40
75
td(on)
-
15
-
tr
-
25
-
td(off)
-
40
-
tf
-
58
-
QT
-
55
80
Qgs (Q1)
-
5.5
-
Qgd (Q2)
-
15
-
-
0.75
0
75
0.90
0.65
1.0
1
0
-
trr
-
30
65
ta
-
20
-
tb
-
19
-
Qrr
-
0.043
-
ns
ns
ns
nC
BODY-DRAIN DIODE RATINGS (Note 3)
ode Forward
o a d On-Voltage
O o age
Diode
(IS = 2.3
2 3 Adc,
Ad VGS = 0 Vd
Vdc))
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
Reverse Recovery
y Time
(IS = 2.3
2 3 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge
2. Switching characteristics are independent of operating junction temperature.
3. Indicates Pulse Test: Pulse Width 300 sec max, Duty Cycle 2%.
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3
Vdc
dc
ns
C
NTH4302
120
VGS = 10 V
80
VDS 10 V
VGS = 4.5 V
VGS = 8.0 V
VGS = 6.0 V
100
100
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
120
VGS = 4.0 V
VGS = 5.5 V
VGS = 5.0 V
60
VGS = 3.5 V
40
VGS = 3.0 V
20
80
60
40
TJ = 25°C
20
VGS = 2.5 V
0
0
2
4
6
8
TJ = 150°C
10
0
1
0.02
TJ = 150°C
0.012
TJ = 25°C
TJ = -55°C
0.004
10
20
30
40
50
60
70
80
90
100 110 120
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
0.024
6
5
0.028
VGS = 4.5 V
0.024
0.02
TJ = 150°C
TJ = 125°C
0.016
TJ = 25°C
0.012
TJ = -55°C
0.008
0.004
10
20
30
40
50
60
70
80
90 100 110 120
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 4. On-Resistance versus Drain Current
and Temperature
Figure 5. On-Resistance versus Drain Current
and Temperature
10000
1.8
1.6
ID = 30 A
VGS = 4.5 V and 10 V
TJ = 150°C
IDSS, LEAKAGE (nA)
RDS(on), DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
VGS = 10 V
TJ = 125°C
3
Figure 3. Transfer Characteristics
0.028
0.008
2
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 2. On-Region Characteristics
0.016
TJ = -55°C
0
1.4
1.2
1.0
1000
TJ = 125°C
100
TJ = 100°C
0.8
0.6
-50
10
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
0
5
10
15
20
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 6. On-Resistance Variation with
Temperature
Figure 7. Drain-to-Source Leakage Current
versus Voltage
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4
25
NTH4302
2000
10
VDS = 0 V
VGS = 0 V
TJ = 25°C
VGS, GATE-T O-SOURCE (V)
Ciss
C, CAPACITANCE (pF)
1600
1200
Ciss
Crss
800
Coss
400
Crss
0
-10
-5
VGS
0
VDS
5
10
15
VGS
6
QT
Q2
Q1
4
2
0
20
ID = 30 A
TJ = 25°C
0
4
8
12
16
Qg, TOTAL GATE CHARGE (nC)
GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE
(V)
Figure 9. Gate-to-Source and Drain-to-Source
Voltage versus Total Charge
Figure 8. Capacitance Variation
1000
60
IS, SOURCE CURRENT (A)
VDS = 10 V
ID = 30 A
VGS = 10 V
t, TIME (ns)
8
100
tr
td(off)
tf
10
td(on)
50
40
30
20
TJ = 150°C
10
TJ = 25°C
0
1
1
10
100
0
RG, GATE RESISTANCE ()
0.2
0.4
0.6
0.8
1
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
Figure 11. Diode Forward Voltage versus
Current
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5
NTH4302
PACKAGE DIMENSIONS
PInPAK
CASE TBD
ISSUE O
PInPAK is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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6
NTH4301/D