Agilent HDMP-3001 STS-3c/STM-1 Ethernet over SONET/SDH Mapper Product Brief Features • Single-chip frame processor with full-duplex mapping of Ethernet frames into SONET/SDH payload using the GFP or LAPS protocol Description The HDMP-3001 is an integrated device that provides full-duplex mapping of Ethernet frames into an STS-3c SONET/STM-1 SDH payload as well as complete SONET/SDH framing. Mapping of Ethernet frames is performed using either the LAPS or GFP protocol. On the system side, the HDMP-3001 can be connected to either an Ethernet PHY or an Ethernet MAC depending on system requirements. When connected to a MAC, it behaves like any other 100 Mb/s Ethernet PHY and can be connected to the same MDIO bus as regular PHY’s. When connected to a PHY, a connection to the Ethernet is achieved with a minimum of components. TOH Overhead Insert 8 bits at 19.44 MHz to transceiver TX Framer Parallel Interface to Line 8 bits at 19.44 MHz from transceiver • System-side Ethernet MII interface and line-side 8-bit parallel interface allows for easy hook-up to standard components • Availability of both generic microprocessor interface and Ethernet MDIO interface provides for configuration and status monitoring • Extensive set of performance counters HDMP-3001 Block Diagram E1, E2, F1 and DCC • Integrated SONET STS-3c/SDH STM-1 framer that terminates and generates SONET/SDH overhead limits the number of external devices required Ethernet Management Bus 8-bit Generic Microprocessor Bus Microprocessor Interface SPE/VC Generator TOH Monitor POH Monitor Rx Framer Pointer Processor MDIO Interface X43+1 Scrambler LAPS/GFP Frame Processor Standard 2-Wire EEPROM Bus LAPS/GFP Frame Processor 4 bits at 25 MHz TX FIFO Ethernet MII Interface to System Performance Monitor X43+1 De-scrambler • Configurable by an external EEPROM (useful in stand-alone applications) EEPROM Interface RX FIFO 4 bits at 25 MHz • Provides internal loop-back paths for diagnostics • Implemented in low-power 0.25 micron CMOS process with 1.8V core and 3.3V I/Os • 160 pin PQFP TOH Overhead Extract GPIO Register JTAG Test Access Port E1, E2, F1 and DCC 16 General Purpose Pins Test Data Benefits • Allows LANs to be interconnected over leased OC-3c lines, thereby extending a LAN to multiple sites Interfaces • System interface is a 25 MHz IEEE 802.3 full-duplex, 100 Mb/s Ethernet MII port that connects to either a PHY and or a MAC • Ethernet switches in each LAN can be connected together directly which reduces cost and complexity • Line side SERDES interface is 8-bit parallel operating at 19.44 MHz. SONET/SDH framer is compliant to specifications ANSI T1.105 and ITU G.707 • Enables Transparent LAN Services which, unlike POS solutions, does not require WAN access routers • Serial data channels for add and drop of SONET overhead bytes E1, E2, F1 and DCC • 1+1 redundancy private reliable Ethernet service in SDH/SONET ring • Generic 8-bit microprocessor interface allows direct connection to commonly used processors Applications • Multi-Service Ethernet Switches • Provides 16-bit General Purpose I/O (GPIO) register • Provides standard five-pin IEEE 1149.1 JTAG test port Data Processing • Complies to the GFP (Generic Framing Procedure) draft specification, revision 2, of ANSI T1X1.5 Implements both the null and linear header options • Complies to the LAPS (Link Access Procedure – SDH) specification X.86 of ITU-T • Optional self-synchronous X43+1 scrambling of the payload • IEEE 802.3 MDIO management interface • Enhanced Services SONET/SDH Add/Drop Multiplexers (ADMs) • Standard 2-wire EEPROM interface for optional boot-up configuration • DSU/CSUs Typical Usage Port on Ethernet Switch Line Card of SONET ADM Standalone DSU/CSU OC-48/12 SONET Ring Agilent Fiber Optics Microprocessor ADM Agilent HDMP-3001 Ethernet PHY Agilent Fiber Optics Ethernet Ports SONET SERDES with CDR Drop Side – 100 Mbit/s Full-Duplex Ethernet EEPROM Microprocessor MDIO Bus Ethernet PHYs SERDES with CDR OC-3c Port Agilent Fiber Optics SERDES with CDR Switch Fabric Agilent HDMP-3001 OC-3c Agilent HDMP-3001 Ethernet PHY 100 Mbit/s Full-Duplex Ethernet This product was jointly developed by Agilent Technologies and Wuhan Research Institute. www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. August 2, 2001 5988-3776EN