HM67S18258 Series 4M Synchronous Fast Static RAM (256k-words × 18-bits) ADE-203-661C (Z) Rev. 3 Jul. 27, 1998 Features • • • • • • • • • • 3.3V ± 5% Operation LVCMOS Compatible Input and Output Synchronous Operation Internal self-timed Late Write Asynchronous G Output Control Byte Write Control (2 byte write selects, one for each 9 bits) Power down mode is provided Differential PECL Clock Inputs Boundary Scan Protocol Single Clock Resister-Latch Mode Ordering Information Type Number Cycle Time Package HM67S18258BP-7 7.0 ns 119 Bump 1. 27 mm 14 mm × 22 mm BGA (BP-119A) All power supply and ground pins must be connected for proper operation of the device. This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HM67S18258 Series Pin Arrangement 1 2 3 4 5 6 7 A VDDQ SA17 SA14 NC SA11 SA8 VDDQ B NC NC SA13 NC SA12 NC NC NC SA16 SA15 VDD SA10 SA9 NC C D DQc0 NC VSS NC VSS DQa8 NC NC DQc1 VSS SS VSS G VSS DQa6 VDDQ E NC DQa7 F VDDQ NC VSS G NC DQc2 SWEc NC VSS NC DQa5 H DQc3 NC VSS NC VSS DQa4 NC VDDQ VDD NC VDD NC VDD VDDQ K VSS NC DQa3 J K NC DQc4 VSS L DQc5 NC VSS K SWEa DQa2 NC M VDDQ DQc6 VSS SWE VSS NC VDDQ N DQc7 NC VSS SA2 VSS DQa1 NC P NC DQc8 VSS SA5 VSS NC DQa0 NC SA1 M1 VDD M2 SA6 NC NC SA3 SA0 NC SA7 SA4 ZZ R T U VDDQ TMS TDI TCK TDO (Top view) 2 NC VDDQ HM67S18258 Series JTAG Register SS JTAG Register SWE JTAG Register SWE a,c, JTAG Register Address Register1 Address Register2 (L) (H) Multiplex SA0SA17 Comparator Block Diagram 18 9×2 Chip Enable Register Byte Write Driver 2 Global Write Register Decoder Memory Array 9×2 (262144words ×18bits) Byte 2 Write Register1 Byte Write Register2 18 Sense Amp. 18 Output Contorol Register 2 G JTAG Register DQa0-8 DQc0-8 (L) 18 Input Data Register (H) 18 Multiplex JTAG Register 18 Output 18 Data Register 18 ZZ JTAG Register JTAG Register I/O Bus Protocol Contorol Logic K,K JTAG Register M1,M2 TDi TCK TMS SAMPLE-Z JTAG Tap Controller TDO Note: The functional block diagram illustrates simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information. 3 HM67S18258 Series Pin Descriptions Name I/O Type Descriptions Note VDD Power Supply VSS Ground VDDQ Output Power Supply K Input Input Clock K Input Input Clock SS Input Synchronous Chip Select SWE Input Synchronous Write Enable SAn Input Synchronous Address n = 0, 1, 2, ... 17 SWEx Input Synchronous Byte Select x = a, c G Input Asynchronous Output Enables ZZ Input Power Down Mode Select DQxm I/O Synchronous Data Input/Output x = a, c m = 0, 1, 2, ... 8 M1, M2 Input Output Protocol Mode Select 1 TMS Input Boundary Scan Test Mode Select TCK Input Boundary Scan Test Clock TDI Input Boundary Scan Test Data In TDO Output Boundary Scan Test Data Out NC No Connection Notes: 1. There is 1 protocol with using mode pins. Mode control pins (M1, M2) are to be tied to either V DD or V SS . The state of the Mode control inputs must be set before power-up and must not change during device operation. Mode control inputs are not standard inputs and may not meet VIH or VIL specifications. M1 M2 Protocol VDD VSS Single Clock Register Latch 4 HM67S18258 Series Truth Table SS G SWE SWEa SWEc K K Operation DQa DQc H X X X X L-H H-L Dead (not selected) High-Z High-Z L H H X X L-H H-L Dead (Dummy read) High-Z High-Z L L H X X L-H H-L Read Dout Dout L X L L L L-H H-L Write Din Din L X L H L L-H H-L Write High-Z Din L X L L H L-H H-L Write Din High-Z Notes: 1. X means don’t care for synchronous inputs, and H or L for asynchronous inputs. 2. SWE, SS, SWEa, SWEc, SA are sampled at the rising edge of K clock. Absolute Maximum Ratings Parameter Symbol Value Unit Note Supply voltage VDD –0.5 to +4.6 V 1 Output Supply Voltage VDDQ –0.5 to VDD+0.5 V 1, 4 Voltage on any pin VIN –0.5 to VDD+0.5 V 1, 4 Operating Temperature Ta 0 to 70 (Tj max = 110) °C Storage Temperature Tstg (bias) –55 to 125 °C Input Latchup Current I LI ±200 mA Output Current per pin Iout ±25 mA Notes: 1. All voltage are referenced to VSS . 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These Bi-CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. Not exceed 4.6 V 5. Power Up Initialization The following supply voltage application sequence is recommended: V SS , VDD then VDDQ. Remember according to the Absolute Maximum Ratings table, VDDQ is not to exceed VDD + 0.5 V, whatever the instantaneous value of V DD. 5 HM67S18258 Series Recommended DC Operating Conditions (Ta = 0 to 70°C [Tj max = 110°C]) Parameter Symbol Min Typ Max Unit Notes Supply voltage VDD 3.135 3.3 3.465 V Output Supply voltage VDDQ 3.135 3.3 3.465 V 1 2.375 2.5 2.75 V 2 Input voltage Logic High Level VIH 2.0 — VDDQ + 0.3 V 1 Logic Low Level VIL –0.5 — 0.8 V 1 Logic High Level VIH 1.85 — VDDQ + 0.3 V 2 Logic Low Level VIL –0.5 — 1.15 V 2 PECL Logic High Level VIH(PECL) 2.135 — 2.420 V PECL Logic Low Level VIL(PECL) 1.490 — 1.825 V Note: 6 1. For VDDQ = 3.3 V supply. 2. For VDDQ = 2.5 V supply. HM67S18258 Series DC Characteristics (Ta = 0 to 70°C [Tj max 110°C], VDD = 3.3V± 5%) Parameter Symbol Min Typ Max Unit Note Input Leakage Current I LI –1 — 1 µA 1 Output Leakage Current I LO –1 — 1 µA 2 PECL Input Leakage Current Low I LI (PECL) — 50 µA PECL Input Leakage Current High I LI (PECL) — 150 µA VDD Operating Current excluding output I DD drivers — — 600 mA 3 Power Dissipation including output drivers Pd — — 2.7 W 3, 8 Standby Current (Power down mode) I SB — — 100 mA 5 Output Voltage Logic Low VOL 0 — 0.4 V 4 Logic High VOH 2.4 VDDQ-0.4 — VDDQ VDDQ V V 4, 6 4, 7 Note: 1. 2. 3. 4. 5. 6. 7. 8. 0 ≤ Vin ≤ V DD 0 ≤ VI/O ≤ V DD, Tristate I/O I(I/O) = 0 mA, Address increment read 50% / write 50%, VDD = VDD max, Frequency = 125 MHz I OH = –2 mA or IOL = 2 mA All inputs (except clock) are held at either VSS or VDDQ, and ZZ is held at V DDQ for VDDQ = 3.3 V supply for VDDQ = 2.5 V supply Output Load Capacitance = 29 pF Input Capacitance (Ta = 25°C, f = 1 MHz) Parameter Symbol Min Max Unit Pin Name Note Address Input Capacitance CINA — 5 pF SAn, SS, SWE, SWEx 1 Clock Input Capacitance CINC — 8 pF K, K, G 1 I/O Capacitance CINIO — 7 pF DQxm 1 Note: 1. This value is measured by sampling and not 100% tested. 7 HM67S18258 Series AC Test Conditions • • • • • • • Note Temperature Input Reference Point for Differential Signals Input pulse levels Clock Input pulse levels Input Rise/Fall Time Clock input Rise/Fall Time Output timing reference (vih/vil) • Output load Note: 0˚C ≤ Ta ≤ 70˚C (Tj max = 110°C) Differential Cross-Over Point 0 to 2.5 V 1.8 to 2.1 V 0.5 to 1.5 ns (10% to 90%) 0.3 to 1.0 ns (10% to 90%) 2.0 V/0.8 V for VDDQ = 3.3 V 1.65 V/1.15 V for VDDQ = 2.5 V See figures 1. These levels are efficent under open termination load condition. These vih/vil levels under termination load will be determined by correlation between open load and termination load. I/O 20pF 50Ω (Including scope and jig capacitance) 1.4V AC Timing Measurement Vih Vil setup hold min setup hold min Vih Vil max 8 1 1 max HM67S18258 Series AC Characteristics (Ta = 0˚ to 70˚C [Tj max = 110°C], VDD=3.3V± 5%) Single Differential Clock Register-Latch Mode (M1 = VDD, M2 = VSS ) -7 Parameter Symbol Min Max Unit Notes Clock Cycle t KHKH 8.0 — ns Clock High Width t KHKL 2.0 — ns Clock Low Width t KLKH 2.0 — ns K Clock Access t KHQV — 7.0 ns K Clock Access t KLQV — 3.0 ns Output Enable Access t GLQV — 3.5 ns K Low to Q Change t KLQX 1.0 — ns K Low to Low-Z t KLQX2 1.0 — ns 1 Output Enable to Low-Z t GLQX 1.0 — ns 1 K Clock High to Hi-Z t KHQZ 1.0 3.5 ns 2 Output Enable to Hi-Z t GHQZ 0.0 3.5 ns 2 Address Setup Time t AVKH 0.5 — ns SA, SS, SWE, Data Setup Time t DVKH 0.5 — ns SWEa, SWEc Address Hold Time t KHAX 1.0 — ns SA, SS, SWE, Data Hold Time t KHDX 1.0 — ns SWEa, SWEc Clock Control Read Control Output Buffer Control Setup Times Hold Times Notes: 1. Transition is measured ±200 mV from steady voltage with specified loading in Test Load. 2. Transition is measured start point of output high impedance from output Low impedance. 9 HM67S18258 Series Timing Waveforms Single Clock Register Latch Mode Read Cycle 1 tKHKH K K SA tKHKL tAVKH A1 tKLKH tKHAX A2 A3 tAVKH tKHAX tAVKH tKHAX A4 SS SWE SWEx tKHQV DQ Notes: 10 G = VIL Do 0 Do 1 tKLQV tKLQX Do 2 Do 3 HM67S18258 Series Read Cycle 2 (SS Controlled) tKHKH K K SA tKHKL tKLKH tAVKH A1 tKHAX A3 tAVKH A4 tKHAX SS tAVKH tKHAX SWE SWEx tKHQZ(Max) DQ Do 0 Do 1 Do 3 tKHQZ(Min) Note: tKLQX2 1. G =VIL. 2. Do1 represents the output data for the input address A1. 11 HM67S18258 Series Read Cycle 3 (G Controlled) tKHKH K K SA tKHKL tAVKH A1 tKLKH tKHAX A2 tAVKH tKHAX tAVKH tKHAX A3 A4 tGHQZ(Max) tGLQV SS SWE SWEx G DQ Do 0 Do 1 Do 2 tGHQZ(Min) 12 Do 3 tGLQX HM67S18258 Series Write Cycle tKHKH K K SA tKHKL tAVKH A1 tKLKH tKHAX A2 tAVKH tKHAX tAVKH tKHAX tAVKH tKHAX tDVKH tKHDX A3 A4 Di 2 Di 3 SS SWE SWEx G DQ Di 0 Di 1 13 HM67S18258 Series Read-Write Cycle READ tKHKH READ WRITE tKHKL tKLKH K K SA tAVKH A1 A2 tAVKH A3 READ READ WRITE tKHAX A4 A5 A6 A7 tKHAX SS tAVKH tKHAX tAVKH tKHAX SWE SWEx G(Low-Fix) tKHQV DQ Do 0 tKLQV tKLQX tKHQZ(max) Do 1 Do 2 tDVKH Di 3 tKHDX Do 4 Do 5 Di 6 tKLQV(max) (1) During this period DQ pins are in the output state so that the input signal of opposite phase to the outputs must not be applied. 14 HM67S18258 Series Boundary Scan Test Access Port Operations overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all of the functions required for 1149.1. the HM67S18258 contains a TAP controller. Instruction resister, Boundary scan resister, Bypass and ID resister. Test Access Port Pins Symbol I/O Name TCK Test Clock TMS Test Mode Select TDI Test Data In TDO Test Data Out Notes: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to V SS . TDO should be left unconnected. TAP DC Operating Characteristics (Ta = 0˚C to 70˚C [Tj max = 110°C]) Parameter Symbol Min Max Boundary scan Input High voltage VIH 2.0 V VDD + 0.3 V Boundary scan Input Low voltage VIL –0.5 V 0.8 V Boundary scan Input Leakage Current I LI –1µA +1µA 1 Boundary scan Output Low voltage VOL 0.4 V 2 Boundary scan Output High voltage VOH 2.4 V Note 3 Notes: 1. 0 ≤ Vin ≤ V DD 2. I OL = 2 mA 3. I OH = –2 mA 15 HM67S18258 Series TAP AC Operating Characteristics (Ta = 0˚C to 70˚C [Tj max = 110 °C]) Parameter Symbol Min Max Unit Test Clock Cycle Time t THTH 67 — ns Test Clock High Pulse Width t THTL 30 — ns Test Clock Low Pulse Width t TLTH 30 — ns Test Mode Select Setup t MVTH 10 — ns Test Mode Select Hold t THMX 10 — ns Capture Setup t CS 10 — ns Capture Hold t CH 10 — ns TDI Valid to TCK High t DVTH 10 — ns TCK High to TDI Don’t Care t THDX 10 — ns TCK Low to TDO Unknown t TLQX 0 — ns TCK Low to TDO Valid t TLQV — 20 ns Notes: 1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. 16 HM67S18258 Series TAP AC Test Conditions • • • • • • • 0°C ≤ Ta ≤ 70°C [Tj max = 110°C] 1.5 V 0 to 2.5 V 2.0 ns typical (10% to 90%) 1.5 V 1.5 V See figures Temperature Input Reference Point for Single-Ended Signals Input pulse levels Input Rise/Fall Time Output timing reference Test load termination supply voltage (VT ) Output Load VT DUT 50 Ω Z0 = 50 Ω TDO boundary scan AC test Load 17 HM67S18258 Series TAP Timing Diagram tTHTH tTHTL tTLTH tMVTH tTHMX TCK TMS tDVTH tTHDX TDI tTLQV tTLQX TDO tCS tCH RAM ADDRESS TAP Timing Diagram 18 HM67S18258 Series Test Access Port Registers Register Name Length Symbol Instruction Register 3 bits IR [0;2] Bypass Register 1 bits BP ID Register 32 bits ID [0;31] Boundary Scan Register 51 bits BS [1;51] Note TAP Controller Instruction Set IR2 IR1 IR0 Instruction Operation 0 0 0 SAMPLE-Z Tristate all data drivers and capture the pad value 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 BYPASS 1 0 0 SAMPLE 1 0 1 BYPASS 1 1 0 BYPASS 1 1 1 BYPASS Tristate all data drivers and capture the pad value Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1. 19 HM67S18258 Series Boundary Scan Order Bit # Bump ID Signal Name Bit # Bump ID Signal Name 1 5R M2 27 2B NC 2 6T SA4 28 3A SA14 3 4P SA5 29 3C SA15 4 6R SA6 30 2C SA16 5 5T SA7 31 2A SA17 6 7T ZZ 32 1D DQc0 7 7P DQa0 33 2E DQc1 8 6N DQa1 34 2G DQc2 9 6L DQa2 35 1H DQc3 10 7K DQa3 36 3G SWEc 11 5L SWEa 37 4D NC 12 4L K 38 4E SS 13 4K K 39 4G NC 14 4F G 40 4H NC 15 6H DQa4 41 4M SWE 16 7G DQa5 42 2K DQc4 17 6F DQa6 43 1L DQc5 18 7E DQa7 44 2M DQc6 19 6D DQa8 45 1N DQc7 20 6A SA8 46 2P DQc8 21 6C SA9 47 3T SA0 22 5C SA10 48 2R SA1 23 5A SA11 49 4N SA2 24 6B NC 50 2T SA3 25 5B SA12 51 3R M1 26 3B SA13 Notes: 1. Bit#1 is the first scan bit to exit the chip. 2. NC pads listed in the TABLE are represented in the Boundary Scan Register by a Place Holder. Place Holder registers are internally connected to VSS. 3. The clock pins (K and K) are needed as PECL differential levels. And, clock reciever generated single clock signal. This signal and its inverted signal are used for Boundary Scan Register input signal. 20 HM67S18258 Series ID register Bit# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value X X X X 0 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Vendor Revision No. 4M, 16M Depth Depth 4M, 16M Width Width Use in the future Vendor ID No. Fix TAP Controller State Diagram 1 0 Test-LogicReset 0 Run-Test/ Idle 1 1 SelectDR-Scan 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR Pause-IR 0 1 0 1 0 Exit2-DR Exit2-IR 1 1 Update-DR Note: 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 SelectIR-Scan 0 0 Update-IR 1 0 The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. 21 HM67S18258 Series Package Outline Unit : mm 0.20 HM67S18258BP (BP-119A) 4× A 6 × 1.27 16 × 1.27 -C- -A- 0.35 C 4×C1.2 14.00 0.15 C 22.00 21.0 ± 0.10 Pin 1 Index -B- 2.10 ± 0.25 0.60 ± 0.10 13.0 ± 0.10 119× φ0.75 ± 0.15 φ0.30 M C A B φ0.15 M C HITACI CODE BP-119A JEDEC CODE Conforms EIAJ CODE Weight Details of the part A 22 1.2g HM67S18258 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 23 HM67S18258 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Oct. 1, 1996 Initial issue — K.Mitsumoto 1 Feb. 21, 1997 P1. 3.3V± 0.1V Operatiion to 3.3V± 5% Operation (Y. Matsui) S.Nakazato Change HM67S18258BP-7H to HM67S18258BP-7 VDDmin 3.2 to 3.135 VDDmax 3.4 to 3.465 VDDQmin 3.2/.6 to 3.135/2.375 VDDQmax 3.4/2.6 to 3.465/2.75 I DDmax 500 to 600 I OH 2mA to - 2mA I OL - 2mA to 2mA P.7 Change termination load t KHKL 3.2 to 2.0 t KLKH 3.2 to 2.0 Add tKHQZmin Add Note 2 Delete Soft Error Rate 2 Nov. 18, 1997 BP-119 to BP-119A (Y. Matsui) S. Nakazato 3 Jul. 27, 1998 Delete the word “Product Preview” (Y. Matsui) S. Nakazato 24