ETC HN58X25128I

HN58X25128I/HN58X25256I
Serial Peripheral Interface
128k EEPROM (16-kword × 8-bit)
256k EEPROM (32-kword × 8-bit)
Electrically Erasable and Programmable Read Only Memory
ADE-203-1371 (Z)
Preliminary
Rev. 0.0
Nov. 15, 2002
Description
HN58X25xxx Series is the Serial Peripheral Interface (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by
employing advanced MONOS memory technology and CMOS process and low voltage circuitry technology.
It also has a 64-byte page programming function to make it’s write operation faster.
Note: Hitachi’s serial EEPROM are authorized for using consumer applications such as cellular phones,
camcorders, audio equipments. Therefore, please contact Hitachi’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Serial peripheral interface (SPI bus)
 SPI mode 0 (0,0), 3 (1,1)
• Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
• Power dissipation:
 Standby: 3 µA (max)
 Active (Read): 5 mA (max)
 Active (Write): 5 mA (max)
• Automatic page write: 64-byte/page
• Write cycle time: 5 ms (2.5 V min), 8 ms (1.8 V min)
• Endurance: 10 Cycles
5
• Data retention: 10 Years
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HN58X25128I/HN58X25256I
• Small size packages: SOP-8pin and TSSOP-14pin
• Shipping tape and reel
 TSSOP-14pin : 2,000 IC/reel
 SOP-8pin
: 2,500 IC/reel
• Temperature range: −40 to +85 °C
Ordering Information
Type No.
Internal organization
Operating voltage Frequency
Package
HN58X25128FPI
128-kbit (16834 × 8-bit)
1.8 V to 5.5 V
150mil 8-pin plastic
SOP (FP-8DB)
HN58X25256FPI
256-kbit (32768 × 8-bit)
HN58X25128TI
128-kbit (16834 × 8-bit)
HN58X25256TI
256-kbit (32768 × 8-bit)
Rev.0.0, Nov. 2002, page 2 of 27
5 MHz
(2.5 V to 5.5 V)
3 MHz
(1.8 V to 5.5 V)
1.8 V to 5.5 V
5 MHz
(2.5 V to 5.5 V)
3 MHz
(1.8 V to 5.5 V)
14-pin plastic
TSSOP (TTP-14D)
HN58X25128I/HN58X25256I
Pin Arrangement
8-pin SOP
14-pin TSSOP
S
1
14
VCC
Q
2
13
HOLD
C
NC
3
12
NC
D
NC
4
11
NC
NC
5
10
NC
W
6
9
C
VSS
7
8
D
S
1
8
VCC
Q
2
7
HOLD
W
3
6
VSS
4
5
(Top view)
(Top view)
Pin Description
Pin name
Function
C
Serial clock
D
Serial data input
Q
Serial data output
S
Chip select
W
Write protect
HOLD
Hold
VCC
Supply voltage
VSS
Ground
Rev.0.0, Nov. 2002, page 3 of 27
HN58X25128I/HN58X25256I
Block Diagram
High voltage generator
HOLD
D
Q
Rev.0.0, Nov. 2002, page 4 of 27
Y
decoder
C
Address generator
S
W
Control logic
VSS
X
decoder
VCC
Memory array
Y-select & Sense amp.
Serial-parallel converter
HN58X25128I/HN58X25256I
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
–0.6 to + 7.0
Input voltage relative to VSS
2
Unit
V
3
VIN
–0.5* to +7.0*
V
Operating temperature range*
Topr
–40 to +85
°C
Storage temperature range
Tstg
–65 to +125
°C
1
Notes: 1. Including electrical characteristics and data retention.
2. VIN (min): –3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
1.8

5.5
V
VSS
0
0
0
Input voltage
VIH
VCC × 0.7

VCC + 0.5*
V
Operating temperature range
V
2
VIL
–0.3*

VCC × 0.3
V
Topr
–40

+85
°C
1
Notes: 1. VIN (min): –1.0 V for pulse width ≤ 50 ns.
2. VIN (max): VCC + 1.0 V for pulse width ≤ 50 ns.
Rev.0.0, Nov. 2002, page 5 of 27
HN58X25128I/HN58X25256I
DC Characteristics
Parameter
Symbol
Min
Max
Unit
Test conditions
Input leakage current
ILI
—
2
µA
VCC = 5.5 V, VIN = 0 to 5.5 V
(S, D, C, HOLD, W)
Output leakage current
ILO
—
2
µA
VCC = 5.5 V, VOUT = 0 to 5.5 V
(Q)
Standby
ISB
—
3
µA
VIN = VSS or VCC,
VCC = 5.5 V
Active
ICC1
—
5
mA
VCC = 5.5 V, Read at 5 MHz
VIN = VCC × 0.1/VCC × 0.9
Q = OPEN
ICC2
—
5
mA
VCC = 5.5 V, Write at 5 MHz
VIN = VCC × 0.1/VCC × 0.9
VOL1
—
0.4
V
VCC = 5.5 V, IOL = 2 mA
VOL2
—
0.4
V
VCC = 2.5 V, IOL = 1.5 mA
VOH1
VCC × 0.8
—
V
VCC = 5.5 V, IOL = −2 mA
VOH2
VCC × 0.8
—
V
VCC = 2.5 V, IOL = −0.4 mA
VCC current
Output voltage
Rev.0.0, Nov. 2002, page 6 of 27
HN58X25128I/HN58X25256I
AC Characteristics
Test Conditions
• Input pules levels:
 VIL = VCC × 0.2
 VIH = VCC × 0.8
• Input rise and fall time: ≤ 10 ns
• Input and output timing reference levels: VCC × 0.3, VCC × 0.7
• Output reference levels: VCC × 0.5
• Output load: 100 pF
Rev.0.0, Nov. 2002, page 7 of 27
HN58X25128I/HN58X25256I
(Ta = −40 to +85°C, VCC = 2.5 V to 5.5 V)
Parameter
Symbol
Alt
Min
Max
Unit
Clock frequency
fC
fSCK
—
5
MHz
S active setup time
tSLCH
tCSS1
90
—
ns
S not active setup time
tSHCH
tCSS2
90
—
ns
S deselect time
tSHSL
tCS
90
—
ns
S active hold time
tCHSH
tCSH
90
—
ns
S not active hold time
tCHSL
—
90
—
ns
Clock high time
tCH
tCLH
90
—
ns
1
Clock low time
tCL
tCLL
90
—
ns
1
Clock rise time
tCLCH
tRC
—
1
µs
2
Clock fall time
tCHCL
tFC
—
1
µs
2
Data in setup time
tDVCH
tDSU
20
—
ns
Data in hold time
tCHDX
tDH
30
—
ns
Clock low hold time after HOLD not
active
tHHCH
—
70
—
ns
Clock low hold time after HOLD active tHLCH
—
40
—
ns
Clock high setup time before HOLD
active
tCHHL
—
60
—
ns
Clock high setup time before HOLD
not active
tCHHH
—
60
—
ns
Output disable time
tSHQZ
tDIS
—
100
ns
Clock low to output valid
tCLQV
tV
—
70
ns
Output hold time
tCLQX
tHO
0
—
ns
Output rise time
tQLQH
tRO
—
50
ns
Output fall time
tQHQL
tFO
—
50
ns
2
HOLD high to output low-Z
tHHQX
tLZ
—
50
ns
2
HOLD low to output low-Z
tHLQZ
tHZ
—
100
ns
2
Write time
tW
tWC
—
5
ms
Notes: 1. tCH + tCL ≥ 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
Rev.0.0, Nov. 2002, page 8 of 27
Notes
2
2
HN58X25128I/HN58X25256I
(Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol
Alt
Min
Max
Unit
Notes
Clock frequency
fC
fSCK
—
3
MHz
S active setup time
tSLCH
tCSS1
100
—
ns
S not active setup time
tSHCH
tCSS2
100
—
ns
S deselect time
tSHSL
tCS
150
—
ns
S active hold time
tCHSH
tCSH
100
—
ns
S not active hold time
tCHSL
—
100
—
ns
Clock high time
tCH
tCLH
150
—
ns
1
Clock low time
tCL
tCLL
150
—
ns
1
Clock rise time
tCLCH
tRC
—
1
µs
2
Clock fall time
tCHCL
tFC
—
1
µs
2
Data in setup time
tDVCH
tDSU
30
—
ns
Data in hold time
tCHDX
tDH
50
—
ns
Clock low hold time after HOLD not
active
tHHCH
—
140
—
ns
Clock low hold time after HOLD active tHLCH
—
90
—
ns
Clock high setup time before HOLD
active
tCHHL
—
120
—
ns
Clock high setup time before HOLD
not active
tCHHH
—
120
—
ns
Output disable time
tSHQZ
tDIS
—
200
ns
Clock low to output valid
tCLQV
tV
—
120
ns
Output hold time
tCLQX
tHO
0
—
ns
Output rise time
tQLQH
tRO
—
100
ns
Output fall time
tQHQL
tFO
—
100
ns
2
HOLD high to output low-Z
tHHQX
tLZ
—
100
ns
2
HOLD low to output low-Z
tHLQZ
tHZ
—
100
ns
2
Write time
tW
tWC
—
8
ms
2
2
Notes: 1. tCH + tCL ≥ 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
Rev.0.0, Nov. 2002, page 9 of 27
HN58X25128I/HN58X25256I
Timing Waveforms
Serial Input Timing
tSHSL
S
tCHSL
tCHSH
tSHCH
tSLCH
C
tDVCH
D
tCHCL
tCLCH
tCHDX
MSB IN
LSB IN
High Impedance
Q
Hold Timing
S
tHHCH
tHLCH
tCHHL
C
tCHHH
D
tHLQZ
Q
HOLD
Rev.0.0, Nov. 2002, page 10 of 27
tHHQX
HN58X25128I/HN58X25256I
Output Timing
S
tSHQZ
tCH
C
tCL
D
ADDR
LSB IN
tCLQV
tCLQX
Q
tCLQX
tCLQV
LSB OUT
tQLQH
tQHQL
Rev.0.0, Nov. 2002, page 11 of 27
HN58X25128I/HN58X25256I
Pin Function
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
serial clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the
data to be written. Values are latched on the rising edge of serial clock (C).
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial
data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after
the falling edge of serial clock (C).
S)
Chip select (S
When this input signal is high, the device is deselected and serial data output (Q) is at high impedance.
Unless an internal write cycle is in progress, the device will be in the standby mode. Driving chip select (S)
low enables the device, placing it in the active power mode. After power-up, a falling edge on chip select (S)
is required prior to the start of any instruction.
HOLD)
Hold (HOLD
HOLD
The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the
device. During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and
serial clock (C) are don’t care. To start the hold condition, the device must be selected, with chip select (S)
driven low.
W)
Write protect (W
The main purpose of this input signal is to freeze the size of the area of memory that is protected against write
instructions (as specified by the values in the BP1 and BP0 bits of the status register). This pin must be
driven either high or low, and must be stable during all write operations.
Rev.0.0, Nov. 2002, page 12 of 27
HN58X25128I/HN58X25256I
Functional Description
Status Register
The following figure shows the Status Register Format. The Status Register contains a number of status and
control bits that can be read or set (as appropriate) by specific instructions.
Status Register Format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bits
Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status
Register cycle.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions.
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect
(W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to
be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD,
BP1, BP0) become read-only bits.
Instructions
Each instruction starts with a single-byte code, as summarized in the following table . If an invalid
instruction is sent (one not contained in the following table), the device automatically deselects itself.
Rev.0.0, Nov. 2002, page 13 of 27
HN58X25128I/HN58X25256I
Instruction Set
Instruction
Description
Instruction Format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Write Enable (WREN):
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to
do this is to send a Write Enable instruction to the device. As shown in the following figure, to send this
instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on
serial data input (D). The device then enters a wait state. It waits for the device to be deselected, by chip
select (S) being driven high.
Write Enable (WREN) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
Q
Rev.0.0, Nov. 2002, page 14 of 27
1
2
3
4
5
VIH
VIL
Instruction
VIH
VIL
High-Z
6
7
HN58X25128I/HN58X25256I
Write Disable (WRDI):
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device.
As shown in the following figure, to send this instruction to the device, chip select (S) is driven low, and the
bits of the instruction byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven
high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
 Power-up
 WRDI instruction execution
 WRSR instruction completion
 WRITE instruction completion
Write Disable (WRDI) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
Q
1
2
3
4
5
6
7
VIH
VIL
Instruction
VIH
VIL
High-Z
Rev.0.0, Nov. 2002, page 15 of 27
HN58X25128I/HN58X25256I
Read Status Register(RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may
be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these
cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new
instruction to the device. It is also possible to read the Status Register continuously, as shown in the
following figure.
Read Status Register (RDSR) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
VIH
VIL
VIH
VIL
Status Register Out
Q
High-Z
7
6
5
4
3
2
1
0
7
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status
Register cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When
set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no
Write or Write Status Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as
defined in the Status Register Format table) becomes protected against Write (WRITE) instructions. The
Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect
(W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to
be put in the Hardware Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and
Rev.0.0, Nov. 2002, page 16 of 27
HN58X25128I/HN58X25256I
write protect (W) signal is driven low). In this mode, the non-volatile bits of the Status Register (SRWD,
BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Write Status Register (WRSR):
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before
it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch(WEL).
The instruction sequence is shown in the following figure. The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip select (S)
must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and
before the next rising edge of serial clock (C). Otherwise, the Write Status Register (WRSR) instruction is
not executed. As soon as chip select (S) is driven high, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, Write
Enable Latch(WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the
values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as
defined in the Status Register Format table.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write
Disable (SRWD) bit in accordance with the write protect (W) signal. The Status Register Write Disable
(SRWD) bit and write protect (W) signal allows the device to be put in the Hardware Protected Mode (HPM).
The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is
entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at
their current values just before the start of the execution of the Write Status Register (WRSR) instruction.
The new, updated values take effect at the moment of completion of the execution of Write Status Register
(WRSR) instruction.
Rev.0.0, Nov. 2002, page 17 of 27
HN58X25128I/HN58X25256I
Write Status Register (WRSR) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
VIH
VIL
Status Register In
D
VIH
VIL
Q
7
6
5
4
3
2
1
0
MSB
High-Z
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The
bits of the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses
are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data
output (Q).
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and
the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be
continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can
occur at any time during the cycle. The addressed first byte can be any byte within any page. The instruction
is not accepted, and is not executed, if a Write cycle is currently in progress.
Rev.0.0, Nov. 2002, page 18 of 27
HN58X25128I/HN58X25256I
Read from Memory Array (READ) Sequence
S
W
C
VIH
VIL
VIH
VIL
VIH
0
1
2
3
4
5
6
7
8
9 10
VIL
Instruction
D
20 21 22 23 24 25 26 27 28 29 30 31
16-Bit Address
VIH
15 14 13
3
2
1
0
VIL
Data Out 1
Note:
Data Out 2
High-Z
Q
7
6
5
4
3
2
1
0
7
1. Depending on the memory size, as shown in the following table, the most significant address bits
are don’t care.
Address Range Bits
Device
HN58X25256I
HN58X25128I
Address bits
A14 to A0
A13 to A0
Notes: 1. b15 is don’t care on the HN58X25256
2. b15 and b14 are don’t care on the HN58X25128
Write to Memory Array (WRITE):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The
bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case
of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the
instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period
tWC (as specified in AC Characteristics). At the end of the cycle, the Write In Progress (WIP) bit is reset to 0.
If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the
input data is shifted in, so that more than a single byte, starting from the given address towards the end of the
same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are
incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address
counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming
data. (The page size of these device is 64 bytes).
Rev.0.0, Nov. 2002, page 19 of 27
HN58X25128I/HN58X25256I
The instruction is not accepted, and is not executed, under the following conditions:
 If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just
before)
 If a Write cycle is already in progress
 If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Byte Write (WRITE) Sequence (1 Byte)
S
W
C
VIH
VIL
VIH
VIL
VIH
0
1
2
3
4
VIH
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
16-Bit Address
15 14 13
3
2
Data Byte 1
1
0
7
6
5
4
3
2
1
0
VIL
High-Z
Q
Note:
6
VIL
Instruction
D
5
1. Depending on the memory size, as shown in Address Range Bits table, the most significant
address bits are don’t care.
Rev.0.0, Nov. 2002, page 20 of 27
HN58X25128I/HN58X25256I
Byte Write (WRITE) Sequence (Page)
S
W
C
VIH
VIL
VIH
VIL
0
VIH
1
2
3
4
5
6
7
8
9
16-Bit Address
VIH
15 14 13
W
C
2
1
0
7
6
5
4
3
2
1
1
0
0
High-Z
VIH
VIL
VIH
VIL
VIH
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
VIL
Data Byte 2
7
D
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
High-Z
Q
Note:
3
Data Byte 1
VIL
Q
S
20 21 22 23 24 25 26 27 28 29 30 31
VIL
Instruction
D
10
1. Depending on the memory size, as shown in Address Range Bits table, the most significant
address bits are don’t care.
Data Protect
The protection features of the device are summarized in the following table. When the Status Register Write
Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status
Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction, regardless weather write protect (W) is driven high or low.
Rev.0.0, Nov. 2002, page 21 of 27
HN58X25128I/HN58X25256I
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be
considered, depending on the state of write protect (W):
 If write protect (W) is driven high, it is possible to write to the Status Register provided that the Write
Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
 If write protect (W) is driven low, it is not possible to write to the Status Register even if the Write
Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to
write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the
data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits
of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
 By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low.
 By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high.
If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated,
and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register,
can be used.
Write Protected Block Size
Status register bits
Array addresses protected
BP1
BP0
Protected blocks
HN58X25256I
HN58X25128I
0
0
None
None
None
0
1
Upper quarter
6000h − 7FFFh
3000h − 3FFFh
1
0
Upper half
4000h − 7FFFh
2000h − 3FFFh
1
1
Whole memory
0000h − 7FFFh
0000h − 3FFFh
Rev.0.0, Nov. 2002, page 22 of 27
HN58X25128I/HN58X25256I
Protection Modes
Memory protect
Write protection of
the status register
W signal
SRWD bit
Mode
1
0
Software
protected
(SPM)
Status register is
Write protected
writable (if the WREN)
instruction has set the
WEL bit). The values
in the BP1 and BP0
bits can be changed.
Ready to accept
Write instructions
0
0
1
1
0
1
Hardware
protected
(HPM)
Status register is
Write protected
hardware write
protected. The values
in the BP1 and BP0
bits cannot be
changed.
Ready to accept
Write instructions
Note:
1
Protected area*
1
Unprotected area*
1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown
in the former table.
Hold Condition
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial
clock (C) are don’t care.
To enter the hold condition, the device must be selected, with chip select (S) low.
Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device
while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be
used if it is required to reset any processes that had been in progress.
The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C)
already being low (as shown in the following figure).
The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C)
already being low.
The following figure also shows what happens if the rising and falling edges are not timed to coincide with
serial clock (C) being low.
Rev.0.0, Nov. 2002, page 23 of 27
HN58X25128I/HN58X25256I
Hold Condition Activation
HOLD status
HOLD status
C
HOLD
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger
and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this
EEPROM have a power on reset function. Be careful of the notices described below in order for the power
on reset function to operate correctly.
• S should be fixed to VCC during VCC on/off. Low to high or high to low transition during VCC on/off
may cause the trigger for the unintentional programming.
• VCC should be turned on/off after the EEPROM is placed in a standby state.
• VCC should be turned on from the ground level (VSS) in order for the EEPROM not to enter the
unintentional programming mode.
• VCC turn on speed should be slower than 10 µs/V.
• When WRSR or WRITE instruction is executed before VCC turns off, VCC should be turned off after
waiting write cycle time (tW).
Rev.0.0, Nov. 2002, page 24 of 27
HN58X25128I/HN58X25256I
Package Dimensions
HN58X25128FPI/HN58X25256FPI (FP-8DB)
As of July, 2002
Unit: mm
3.90
4.89
5.15 Max
5
8
0.69 Max
0.034
*0.22 +– 0.017
0.20 ± 0.03
4
1.73 Max
1
6.02 ± 0.18
1.06
*0.42 +0.063
–0.064
0.40 ± 0.06
0.114
0.14 +– 0.038
0˚ – 8˚
1.27
+ 0.289
0.60 – 0.194
0.10
0.25 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
JEITA
Mass (reference value)
FP-8DB
—
—
0.08 g
Rev.0.0, Nov. 2002, page 25 of 27
HN58X25128I/HN58X25256I
HN58X25128TI/HN58X25256TI (TTP-14D)
As of July, 2002
Unit: mm
4.40
5.00
5.30 Max
14
8
1
7
0.65
*0.22+0.08
–0.07
0.20 ± 0.06
1.0
0.13 M
6.40 ± 0.20
*Dimension including the plating thickness
Base material dimension
Rev.0.0, Nov. 2002, page 26 of 27
0.07 +0.03
–0.04
0.10
*0.17 ± 0.05
0.15 ± 0.04
1.10 Max
0.83 Max
0˚ – 8˚
0.50 ± 0.10
Hitachi Code
JEDEC
JEITA
Mass (reference value)
TTP-14D
—
—
0.05 g
HN58X25128I/HN58X25256I
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe Ltd.
Electronic Components Group
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Ltd.
Hitachi Tower
16 Collyer Quay #20-00
Singapore 049318
Tel : <65>-6538-6533/6538-8577
Fax : <65>-6538-6933/6538-3877
URL : http://semiconductor.hitachi.com.sg
Hitachi Europe GmbH
Electronic Components Group
Dornacher Str 3
D-85622 Feldkirchen
Postfach 201, D-85619 Feldkirchen
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Asia Ltd.
(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road
Hung-Kuo Building
Taipei (105), Taiwan
Tel : <886>-(2)-2718-3666
Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
URL : http://semiconductor.hitachi.com.tw
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon Hong Kong
Tel : <852>-2735-9218
Fax : <852>-2730-0281
URL : http://semiconductor.hitachi.com.hk
Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 7.0
Rev.0.0, Nov. 2002, page 27 of 27