HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -7.5 -8 -8A Units fCK 133 125 125 MHz tCK3 7.5 8 8 ns tAC3 5.4 6 6 ns tCK2 10 10 12 ns tAC2 6 6 6 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature • Four Banks controlled by BA0 & BA1 • Programmable CAS Latency: 2 & 3 • Programmable Wrap Sequence: Sequential or Interleave • Programmable Burst Length: 1, 2, 4, 8 • Full page burst length (optional) for sequential wrap around • Multiple Burst Read with Single Write Operation • Automatic Command • Data Mask for Read / Write control (x4, x8) • Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Power Down and Clock Suspend Mode • 8192 refresh cycles / 64 ms (7,8 µs) • Random Column Address every CLK ( 1-N Rule) • Single 3.3V +/- 0.3V Power Supply • LVTTL Interface versions • Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) • -7.5 parts for PC133 3-3-3 operation -8 parts for PC100 2-2-2 operation -8A parts for PC100 3-2-2 operation and Controlled Precharge The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x 16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.17 µm 256MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages. INFINEON Technologies 1 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Ordering Information Type Speed Grade Package Description HYB 39S256400CT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 16M x 4 SDRAM HYB 39S256400CT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM HYB 39S256400CT-8A PC100-322-620 P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM HYB 39S256800CT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 8M x 8 SDRAM HYB 39S256800CT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 8M x 8 SDRAM HYB 39S256800CT-8A PC100-322-620 P-TSOP-54-2 (400mil) 125MHz 4B x 8M x 8 SDRAM HYB 39S256160CT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 4M x 16 SDRAM HYB 39S256160CT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 4M x 16 SDRAM HYB 39S256160CT-8A PC100-322-620 P-TSOP-54-2 (400mil) 125MHz 4B x 4M x 16 SDRAM HYB39S256xx0CTL PC100-xxx-620 P-TSOP-54-2 (400mil) Low Power Versions (on request) Pin Description and Pinouts: CLK Clock Input DQ Data Input /Output CKE Clock Enable DQM, LDQM, UDQM Data Mask CS Chip Select Vdd Power (+3.3V) RAS Row Address Strobe Vss Ground CAS Column Address Strobe Vddq Power for DQ’s (+ 3.3V) WE Write Enable Vssq Ground for DQ’s A0-A12 Address Inputs NC not connected BA0, BA1 Bank Select INFINEON Technologies 2 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM 16 M x 16 32 M x 8 64 M x 4 VDD VDD VDD DQ0 DQ0 N.C. VDDQ VDDQ VDDQ DQ1 DQ2 N.C. DQ1 N.C. DQ0 VSSQ VSSQ VSSQ DQ3 DQ4 N.C. DQ2 N.C. N.C. VDDQ VDDQ VDDQ DQ5 DQ6 N.C. DQ3 N.C. DQ1 VSSQ VSSQ VSSQ DQ7 N.C. N.C. VDD VDD VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 N.C. WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 N.C. WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS VSS VSS N.C. DQ7 DQ15 VSSQ VSSQ VSSQ N.C. DQ3 N.C. DQ6 DQ14 DQ13 VDDQ VDDQ VDDQ N.C. N.C. N.C. DQ5 DQ12 DQ11 VSSQ VSSQ VSSQ N.C. DQ2 N.C. DQ4 DQ10 DQ9 VDDQ VDDQ VDDQ N.C. N.C. DQ8 VSS VSS VSS N.C. DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 N.C. DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 N.C. UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS VSS TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch) SPP04126 Pinout for x4, x8 & x16 organised 256M-DRAMs INFINEON Technologies 3 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Column Address Counter Column Address Buffer Row Address Buffer Row Decoder Row Decoder Row Decoder Row Decoder Memory Array Memory Array Memory Array Memory Array 8196 x 2048 x 4 Bit Input Buffer Bank 1 8196 x 2048 x 4 Bit Bank 2 8196 x 2048 x 4 Bit Output Buffer Refresh Counter Column Decoder Sense amplifier & I(O) Bus Bank 0 Column Decoder Sense amplifier & I(O) Bus A0 - A12, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Row Addresses A0 - A9, A11, AP, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Column Addresses Bank 3 8196 x 2048 x 4 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQM DQ0 - DQ3 Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing) INFINEON Technologies 4 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM A0 - A12, BA0, BA1 Column Address Counter Column Address Buffer Row Address Buffer Row Decoder Row Decoder Row Decoder Row Decoder Memory Array Memory Array Memory Array Memory Array 8192 x 1024 x 8 Bit Input Buffer Bank 1 8192 x 1024 x 8 Bit Bank 2 8192 x 1024 x 8 Bit Output Buffer Refresh Counter Column Decoder Sense amplifier & I(O) Bus Bank 0 Column Decoder Sense amplifier & I(O) Bus A0 - A9, AP, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Row Addresses Column Decoder Sense amplifier & I(O) Bus Column Addresses Bank 3 8192 x 1024 x 8 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQM DQ0 - DQ7 Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing) INFINEON Technologies 5 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM A0 - A8, AP, BA0, BA1 A0 - A12, BA0, BA1 Column Address Counter Column Address Buffer Row Address Buffer Row Decoder Row Decoder Bank 0 8192 x 512 x 16 Bit Input Buffer Memory Array Bank 1 8192 x 512 x 16 Bit Memory Array Bank 2 8192 x 512 x 16 Bit Output Buffer Row Decoder Column Decoder Sense amplifier & I(O) Bus Memory Array Refresh Counter Row Decoder Column Decoder Sense amplifier & I(O) Bus Column Decoder Sense amplifier & I(O) Bus Row Addresses Column Decoder Sense amplifier & I(O) Bus Column Addresses Memory Array Bank 3 8192 x 512 x 16 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQMU DQML DQ0 - DQ15 Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing) INFINEON Technologies 6 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A12 Input Level – During a Bank Activate command cycle, A0-A12 define the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An define the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: 64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits) 32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits) 16M x16 SDRAM CAn = CA8 (Page Length = 512 bits) In addition to the column address, A10(= AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input DQx Level – Bank Select Inputs. Bank address inputs selects which of the four banks a command applies to. Input Level Output – Data Input/Output pins operate in the same manner as on conventional DRAMs. INFINEON Technologies 7 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Pin Type Signal Polarity Function DQM LDQM UDQM Input Pulse VDD VSS VDDQ VSSQ Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs. Supply – – Power and ground for the input buffers and the core logic. Supply – – Isolated power supply and ground for the output buffers to provide improved noise immunity. INFINEON Technologies 8 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device State CKE n-1 CKE n DQM BA0 BA1 AP= A10 Addr . CS RAS CAS WE Bank Active Idle3 H X X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active3 H X X V L V L H L L Active 3 H X X V H V L H L L Active 3 H X X V L V L H L H Read with Autoprecharge Active 3 H X X V H V L H L H Mode Register Set Idle H X X V V V L L L L No Operation Any H X X X X X L H H H Burst Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L X X X X L L L H Self Refresh Exit Idle (Self Refr.) H X X X L H X X X X L H H X Clock Suspend Entry Active H L X X X X X X X X Power Down Entry (Precharge or active standby) Idle Active4 H X X X H L X X X X L H H X Clock Suspend Exit Active L H X X X X X X X X Power Down Exit Any (Power Down) H X X X L H X X X X L H H L Data Write/Output Enable Active H X L X X X X X X X Data Write/Output Disable Active H X H X X X X X X X Write with Autoprecharge Read Notes 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can’t be entered in a burst cycle. When this command assert in the burst mode cycle device is clock suspend mode. INFINEON Technologies 9 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Operation Mode CAS Latency BT Burst Length Mode Register (Mx) Operation Mode Burst Type M9 0 Mode burst read / burst write M3 Type 0 Sequential 1 burst read / single write 1 Interleave Burst Length CAS Latency M6 M5 M4 Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 1 0 1 1 1 0 1 1 1 Reserved M2 M1 M0 0 0 0 0 Length Sequential Interleave 0 1 1 0 1 2 2 1 0 4 4 0 1 1 8 8 1 0 0 1 0 1 1 1 0 1 1 1 Reserved Reserved Full page *) *) optional feature on this device INFINEON Technologies 10 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature on this device. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do nor self terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 or 8, full page burst INFINEON Technologies 11 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM continues until it is terminated using other commands. Full page operation is an optional feature on this device, which is built in by design, but not tested on every component. Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. Burst Length and Sequence: Burst Length Starting Address (A2 A1 A0) Sequential Burst Addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4 x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 Full Page (optional) nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 Cn, Cn+1, Cn+2 6 7 0 1 2 3 4 5 Interleave Burst Addressing (decimal) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 not supported Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic INFINEON Technologies 12 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to „high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE „high“. One clock delay is required for power down mode entry and and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with AutoPrecharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (“write recovery time”) after the last data in. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last data out to apply the precharge command. INFINEON Technologies 13 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Bank Selection by Address Bits A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 x x all Banks Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. INFINEON Technologies 14 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 °C Storage temperature range......................................................................................– 55 to + 150 °C Input/output voltage .............................................................................................– 0.3 to Vdd+0.3 V Power supply voltage VDD / VDDQ ............................................................................ – 0.3 to + 4.6 V Power Dissipation............................................. ..........................................................................1 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operation and Characteristics: TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. Unit Notes max. Input high voltage VIH 2.0 Vdd+0.3 V 1, 2 Input low voltage VIL – 0.3 0.8 V 1, 2 Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V 3 Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V 3 Input leakage current, any input (0 V < VIN < Vddq, all other inputs = 0 V) II(L) –5 5 µA Output leakage current (DQ is disabled, 0 V < VOUT < Vdd) IO(L) –5 5 µA Notes: 1. All voltages are referenced to VSS. 2. Vih may overshoot to Vdd + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Values min. max. Unit Input capacitance (CLK) CI1 2.5 3.5 pF Input capacitance CI2 2.5 3.8 pF CIO 4.0 6.0 pF (A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM) Input / Output capacitance (DQ) INFINEON Technologies 15 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Operating Currents (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. ICC1 OPERATING CURRENT -7.5 -8/-8A max. max. 230 170 Note mA tck=tckmin, All banks operated in random access, all banks operated in ping-pong manner. 3, 4 tck = min. ICC2P 2 2 mA 3 tck = min. ICC2N 40 30 mA 3 NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 50 45 mA 3 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P 10 10 mA 3 BURST OPERATING CURRENT tck = min., Read command cycling ICC4 150 100 mA AUTO REFRESH CURRENT tck = min., trc=trcmin., Auto Refresh command cycling ICC5 240 220 mA ICC6 3 3 mA 1.7 1.7 mA PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V tck=infinity 3,4 standard version L-version 3 Notes: 3. These parameters depend on the cycle rate. All values are measured at 133 MHz operation frequency for -7.5 devices and at 100 MHz for -8/-8A devices. Input signals are changed once during tck. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. INFINEON Technologies 16 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM AC Characteristics 1)2) TA = 0 to 70 °C; VSS = 0 V; Vdd = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol -7.5 PC133333 -8 PC100222 min. max. min. Unit -8A PC100322 max. min. max. 8 10 – – 8 12 – – Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK 7.5 10 Clock Frequency CAS Latency = 3 CAS Latency = 2 tCK – – 133 100 – – 125 100 – – Access Time from Clock CAS Latency = 3 CAS Latency = 2 tAC – – 5.4 6 – – 6 6 – – 6 6 ns ns Clock High Pulse Width tCH 2.5 – 3 – 3 – ns Clock Low Pulse Width tCL 2.5 – 3 – 3 – ns Transition time tT 0.3 1.2 0.5 10 0.5 10 ns Input Setup Time tIS 1.5 – 2 – 2 – ns 4 Input Hold Time tIH 0.8 – 1 – 1 – ns 4 CKE Setup Time tCKS 1.5 – 2 – 2 – ns 4 CKE Hold Time tCKH 0.8 – 1 – 1 – ns 4 Mode Register set to Active delay tRSC 2 – 2 – 2 – CLK Power Down Mode Entry Time tSB 0 7.5 0 8 0 8 ns Row to Column Delay Time tRCD 20 – 20 – 20 ns 5 Row Precharge Time tRP 20 – 20 – 20 ns 5 Row Active Time tRAS 45 100k 48 100k 48 100k ns 5 Row Cycle Time tRC 67 – 70 – 70 – ns 5 ns ns 125 MHz 83 MHz 2, 3, 7 Setup and Hold Times Common Parameters INFINEON Technologies 17 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Parameter Limit Values Symbol -7.5 PC133333 min. -8 PC100222 max. min. Unit -8A PC100322 max. min. max. Activate(a) to Activate(b) Command period tRRD 15 – 16 – 16 CAS(a) to CAS(b) Command period tCCD 1 – 1 – 1 – CLK Refresh Period (8192 cycles) tREF – 64 – 64 – 64 ms Self Refresh Exit Time tSREX 1 – 1 Data Out Hold Time tOH 3 – 3 – 3 – ns Data Out to Low Impedance Time tLZ 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 7 3 8 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK Data Input to Precharge (write recovery) tWR 2 – 2 – 2 – CLK 8 DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK ns 5 Refresh Cycle 1 CLK 6 Read Cycle 2, 7 Write Cycle INFINEON Technologies 18 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Notes for AC Parameters: 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is meas ured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shown in fig.1.Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC I/O t OH 50 pF OUTPUT 1.4 V t HZ SPT03404 Measurement conditions for tac and toh fig.1 3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 8. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices with twr = 1 CLK for operations at less or equal 83 MHz will be available. INFINEON Technologies 19 8.00 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Package Outlines 0.8 15˚±5˚ 0.35 +0.1 -0.05 26x 0.8 = 20.8 3) 0.1 54x 0.5 ±0.1 11.76 ±0.2 0.2 M 54x 28 6 max 54 10.16 ±0.13 2) 0.15 +0.06 -0.03 1±0.05 15˚±5˚ 0.1±0.05 Plastic Package P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 1 2.5 max 27 22.22 ±0.13 1) GPX09039 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side 2) INFINEON Technologies 20 8.00 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. AC- Parameters 8.1 AC Parameters for a Write Timing 8.2 AC Parameters for a Read Timing 9. Mode Register Set 10. Power on Sequence and Auto Refresh (CBR) 11. Clock Suspension (using CKE) 11. 1 Clock Suspension During Burst Read CAS Latency = 2 11. 2 Clock Suspension During Burst Read CAS Latency = 3 11. 3 Clock Suspension During Burst Write CAS Latency = 2 11. 4 Clock Suspension During Burst Write CAS Latency = 3 12. Power Down Mode and Clock Suspend 13. Self Refresh ( Entry and Exit ) 14. Auto Refresh ( CBR ) 15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst INFINEON Technologies 21 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 1. Bank Activate Command Cycle (CAS latency = 3) T0 T1 T T T T T CLK Address Bank B Row Addr. Bank B Col. Addr. t RCD Command Bank B Activate NOP Bank B Row Addr. Bank A Row Addr. t RRD NOP Write B with Auto Precharge Bank A Activate NOP Bank B Activate t RC "H" or "L" SPT03784 2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A NOP NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s CAS latency = 3 t CK3 , DQ’s INFINEON Technologies DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 SPT03712 22 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A Read B NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 SPT03713 4. Read to Write Interval 4.1 Read to Write Interval (Burst Length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles Write latency t DQW of DQMx DQMx t DQZ Command NOP Read A NOP NOP DQ’s NOP DOUT A0 NOP Write B NOP NOP DIN B0 DIN B1 DIN B2 Must be Hi-Z before the Write Command "H" or "L" INFINEON Technologies SPT03787 23 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 4 2. Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 Write A NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 CLK t DQW DQM t DQZ 1 Clk Interval Command NOP NOP Bank A Activate NOP Read A Must be Hi-Z before the Write Command CAS latency = 2 t CK2 , DQ’s "H" or "L" SPT03939 4. 3. Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP CLK t DQW DQM t DQZ Command NOP Read A NOP NOP Read A NOP Write B Must be Hi-Z before the Write Command CAS latency = 2 t CK2 , DQ’s DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2 CAS latency = 3 t CK3 , DQ’s DOUT A0 DIN B0 DIN B1 DIN B2 "H" or "L" INFINEON Technologies SPT03940 24 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 5. Burst Write Operation ( (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care CLK Command DQ’s The first data element and the Write are registered on the same clock edge. INFINEON Technologies Extra data is ignored after termination of a Burst. 25 SPT03790 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 6. Write and Read Interrupt 6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Write B NOP NOP NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 CLK 1 Clk Interval Command NOP Write A 1 Clk Interval DQ’s DIN A0 DIN B0 SPT03791 6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A Read B NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s DIN A0 don’t care CAS latency = 3 t CK3 , DQ’s DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 don’t care Input data for the Write is ignored. DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ’s at least one clock cycle before the Read data appears on the outputs to avoid data contention. SPT03719 INFINEON Technologies 26 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 7. Burst Write and Read with Auto Precharge 7.1 Burst Write with Auto-Precharge (Burst Length = 2, CAS latency = 2, 3 ) T0 T1 Bank A Active NOP T2 T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 CLK CAS Latency = 2: Command Write A Auto Precharge t WR DIN A0 DQ’s NOP NOP NOP t RP * DIN A1 Activate CAS Latency = 3: Command Bank A Active NOP NOP Write A NOP Auto Precharge NOP NOP t WR DIN A0 DQ’s t RP * DIN A1 * Activate Begin Auto Precharge Bank can be reactivated after trp 7.2 Burst Read with Auto-Precharge (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A with AP NOP NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 DQ’s CAS latency = 3 DQ’s * DOUT A0 DOUT A1 DOUT A2 t RP DOUT A3 t RP * DOUT A0 DOUT A1 DOUT A2 DOUT A3 * Begin Auto Precharge Bank can be reactivated after trp INFINEON Technologies 27 SPT03721_2 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 8. AC Parameters 8.1 AC Parameters for a Write Timing Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CH t CK2 t CL CKE t CKS t CH t CKH Begin Auto Precharge Bank B Begin Auto Precharge Bank A t CS CS RAS CAS WE BS tAH AP RBx RAx RAy RAz RBy RAz RBy t AS Addr. RAx CAx RBx RAy CBx RAy DQM t WR t RCD t DS t RP t DH t RC Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 DQ Activate Command Bank A Activate Command Bank B Write with Auto Precharge Command Bank A INFINEON Technologies t RP t RRD Ay0 Ay1 Ay2 Ay3 Activate Write Command Command Bank A Bank A Write with Auto Precharge Command Bank B t WR Precharge Activate Activate Command Command Command Bank A Bank A Bank B SPT03910_2 28 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 8.2 AC Parameters for a Read Timing Burst Length = 2, CAS Latency = 2 T0 T1 T2 T3 T4 T6 T5 T7 T8 T9 T10 T11 T12 T13 CLK t CH t CK2 t CL CKE t CKH t CS Begin Auto Precharge Bank B t CKS t CH CS RAS CAS WE BS t AH RAx AP RBx RAy t AS RAx Addr. CAx RBx RBx RAy t RRD t RAS t RC DQM tAC2 t LZ t OH t RCD DQ Hi-Z Read Command Bank A Activate Command Bank B 29 t RP t AC2 Ax0 Activate Command Bank A INFINEON Technologies t HZ t HZ Ax1 Read with Auto Precharge Command Bank B Bx0 Precharge Command Bank A Bx1 Activate Command Bank A SPT03911_2 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 9. Mode Register Set CAS Latency = 2 T0 T1 T2 T3 T5 T4 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t RSC CS RAS CAS WE BS AP Address Key Addr. Precharge Command All Banks Any Command Mode Register Set Command INFINEON Technologies SPT03912_2 30 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 10. Power on Sequence and Auto Refresh (CBR) T2 T3 T4 CKE T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ ~ ~ ~ ~ CLK T1 ~ ~ T0 2 Clock min. Minimum of 8 Refresh Cycles are required ~ ~ ~ ~ High Level is required ~ ~ ~ ~ ~ ~ AP ~ ~ ~ ~ BS ~ ~ ~ ~ ~ ~ WE ~ ~ ~ ~ ~ ~ ~ ~ CAS ~ ~ ~ ~ ~ ~ ~ ~ RAS ~ ~ ~ ~ ~ ~ ~ ~ CS ~ ~ ~ ~ ~ ~ ~ ~ Addr. ~ ~ ~ ~ Address Key DQM t RC ~ ~ DQ ~ ~ t RP Hi-Z Precharge Command All Banks Inputs must be stable for 200 µs INFINEON Technologies 8th Auto Refresh Command 1st Auto Refresh Command Mode Register Set Command Any Command SPT03913 31 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 11. Clock Suspension ( Using CKE) 11.1 Clock Suspension During Burst Read CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM t CSL t CSL DQ Hi-Z Ax0 Read Activate Command Command Bank A Bank A INFINEON Technologies t HZ t CSL Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles 32 SPT03914 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 11.2 Clock Suspension During Burst Read CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx t CSL t CSL DQM t CSL t HZ DQ Hi-Z Ax0 Activate Command Bank A INFINEON Technologies Read Command Bank A Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles 33 SPT03915 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 11.3 Clock Suspension During Burst Write CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend 1 Cycle DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A INFINEON Technologies SPT03916 34 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 11.4 Clock Suspension During Burst Write CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BA A8/AP RAx Addr. RAx CAx DQMx DQ Hi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend 1 Cycle DAx2 Clock Suspend 2 Cycles Clock Suspend 3 Cycles Write Command Bank A INFINEON Technologies DAx3 SPT03917 35 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 12. Power Down Mode and Clock Suspend Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CKS t CK2 t CKS CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM t HZ DQ Hi-Z Ax0 Ax1 Activate Command Bank A Active Standby Clock Suspend Mode Entry Read Command Bank A Ax2 Clock Mask Start Clock Suspend Mode Exit Clock Mask End Ax3 Precharge Command Bank A Precharge Standby Power Down Mode Entry Any Command Power Down Mode Exit SPT03918 INFINEON Technologies 36 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 13. Self Refresh (Entry and Exit) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ CLK ~ ~ CKE ~ ~ t CKS t CKS ~ ~ ~ ~ CS ~ ~ ~ ~ RAS ~ ~ CAS ~ ~ ~ ~ ~ ~ WE ~ ~ BS ~ ~ ~ ~ AP ~ ~ ~ ~ ~ ~ Addr. t SREX t RC*) ~ ~ DQM Hi-Z ~ ~ DQ All Banks must be idle Self Refresh Entry Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit Any Command *) minimum RAS cycle time depends on CAS Latency and trc INFINEON Technologies 37 SPT03919-2 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 14. Auto Refresh (CBR) Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx t RC t RP DQM CAx t RC (Minimum Interval) Hi-Z Ax0 Ax1 Ax2 Ax3 DQ Precharge Auto Refresh Command Command All Banks Auto Refresh Command Activate Read Command Command Bank A Bank A SPT03920_2 INFINEON Technologies 38 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 15. Random Column Read (Page within same Bank) 15.1 CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A INFINEON Technologies Read Command Bank A Read Command Bank A Read Command Bank A 39 Precharge Command Bank A Activate Command Bank A Az0 Az1 Az2 Az3 Read Command Bank A SPT03921 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 15.2 CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A INFINEON Technologies Read Command Bank A Read Command Bank A Read Command Bank A 40 Precharge Command Bank A Activate Command Bank A Read Command Bank A SPT03922 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 16. Random Column write (Page within same Bank) 16.1 CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RBw Addr. RBw RBz CBx CBy DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 CBw RBz CBz DQM Hi Z DQ Activate Write Command Command Bank B Bank B DBy1 DBy2 Write Write Command Command Bank B Bank B DBy3 DBz0 DBz1 DBz2 DBz3 Precharge Activate Read Command Command Command Bank B Bank B Bank B SPT03923_2 INFINEON Technologies 41 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 16.2. CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RBz Addr. RBz RBz CBz CBx CBy RBz CBz DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank B INFINEON Technologies Write Command Bank B Write Command Bank B Write Command Bank B 42 DBz0 DBz1 Precharge Command Bank B Activate Command Bank B Write Command Bank B SPT03924 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 17. Random Row Read (Interleaving Banks) with Precharge 17.1 CAS Latency = 2 Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RBx Addr. RBx RBy RAx CBx RAx CAx RBy CBy t RP t RCD DQM t AC2 Hi-Z DQ Read Activate Command Command Bank B Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Precharge Activate Command Command Bank B Bank B Activate Command Bank A Read Command Bank A INFINEON Technologies 43 By0 By1 Read Command Bank B SPT03925_2 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 17.2 CAS Latency = 3 Burst Length = 8, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS AP RBx Addr. RBx RAx CBx RBy RAx CAx RBy t AC3 t RCD CBy t RP DQM DQ Hi-Z Activate Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Read Command Bank B Read Command Bank A Activate Command Bank A Precharge Command Bank B Activate Command Bank B Read Command Bank B Precharge Command Bank A SPT03926 INFINEON Technologies 44 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 18. Random Row Write (Interleaving Banks) with Precharge 18.1 CAS Latency = 2 Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RBx CAx RAy RBx CBx t RCD RAy t WR CAy t WR t RP DQM Hi-Z DQ DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 Activate Write Command Command Bank B Bank B Precharge Command Bank A INFINEON Technologies 45 DBx4 Activate Command Bank A DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Precharge Command Bank B Write Command Bank A SPT03927_2 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 18.2 CAS Latency = 3 Burst Length = 8, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T9 CLK t CK3 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RAy RBx CAx RBx CBx t RCD RAy t WR t RP CAy t WR DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B SPT03928 INFINEON Technologies 46 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 19. Precharge termination of a Burst 19.1 CAS Latency = 2 Burst Length = 8 or Full Page, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RAz RAy CAx RAy CAy t RP RAz CAz t RP t RP Ay0 Ay1 Ay2 Az0 Az1 Az2 DQM DQ Hi Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked. Precharge Command Bank A Read Command Bank A Precharge Command Bank A Read Command Bank A Activate Command Bank A Activate Command Bank A Precharge Command Bank A Precharge Termination of a Read Burst. SPT03933 INFINEON Technologies 47 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM INFINEON Technologies 48 HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Change List 23.8.99 First Rev. 6.10.99 Clock Suspend Mode not supported anymore (Dr.Savignac) Changes on pages 1, 8 & 15 Waveforms: chapters 11 & 12 deleted and renumbered 3.12.99 some PC133 parameters changed according to INTELs PC133 specification 27.1.2000 Some ICC currents changed after measurement of first lots Datasheet changed from Target to Preliminary 11.4.2000 confusion note 4 on page 8, removed, burst stop is supported for BL =2,4 & 8 14.4.2000 Full page burst is functional beginning with designstep DD3A. Implemented into the datasheet as optional (untested) feature Mail from Ralf Schneider, April 12. 00 25.4.2000 Power Down Exit with one clock beginning with DD3D designstep Clock suspend mode functional with DD3D designstep Clock suspend mode is added in the datasheet and the waveform drawings again. Tras interlock changed to 4 clocks twr = 2 Clock on this design version Note for availability of components with twr = 1 clock interlock 28.6.2000 Preliminary datasheet changed to final Change request from Mr. Lüken: Text change on page 16 (for clarification) page 17: “mode register set-up time” renamed to “Mode Register set to Active delay” Waveform Drawing changed from SPT03910 to SPT03910_2 Waveform Drawing changed from SPT03923 to SPT03923_2 Waveform Drawing changed from SPT03925 to SPT03925_2 Waveform Drawing changed from SPT03927 to SPT03927_2 20.7.2000 Last minute changes requested by Mr. Lüken page 16: note 4 for ICC1 Waveform Drawing changed from SPT03911 to SPT03911_2 Waveform Drawing SPT03925_2 trp arrow corrected 8.8.2000 ICC6 for Low Power Versions changed from 1.5 to 1.7 mA (Discussion with Hahn and Lüken) INFINEON Technologies 21 8.00