CYPRESS CY7C09169AV-12AI

CY7C09159AV
CY7C09169AV3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
CY7C09159AV
CY7C09169AV
3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
Features
• 3.3V Low operating power
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
— Active = 135 mA (typical)
— Standby = 10 µA (typical)
• Fully synchronous interface for easier operation
• Two Flow-Through/Pipelined devices
• Burst counters increment addresses internally
— 8K x 9 organization (CY7C09159AV)
— Shorten cycle times
— 16K x 9 organization (CY7C09169AV)
— Minimize bus noise
• Three Modes
— Supported in Flow-Through and Pipelined modes
— Flow-Through
— Pipelined
• Dual Chip Enables for easy depth expansion
— Burst
• Automatic power-down
• Pipelined output mode on both ports allows fast 83-MHz
operation
• Commercial and industrial temperature ranges
• 0.35-micron CMOS for optimum speed/power
• Pb-Free packages available
• Available in 100-pin TQFP
• High-speed clock to data access 9 and 12 ns (max.)
Logic Block Diagram
R/WL
R/WR
OEL
OER
CE0L
CE1L
1
0
0
0/1
1
FT/PipeL
0/1
[1]
A0−A12/13L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
0
0
1
FT/PipeR
0/1
9
I/O0L−I/O8L
CE0R
CE1R
1
9
I/O
Control
I/O0R−I/O8R
I/O
Control
13/14
13/14
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
[1]
A0−A12/13R
CLKR
ADSR
CNTENR
CNTRSTR
Notes:
1. A0−A12 for 8K; A0−A13 for 16K.
Cypress Semiconductor Corporation
Document #: 38-06053 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C09159AV
CY7C09169AV
Functional Description
The CY7C09159AV and CY7C09169AV are high-speed
synchronous CMOS 8K and 16K x 9 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.[2]
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available tCD1 = 18 ns after the
address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
LOW- to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations.
In the pipelined mode, one cycle is required with CE0 LOW and
CE1 HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
2. When simultaneously writing to the same location, final value cannot be guaranteed.
Document #: 38-06053 Rev. *B
Page 2 of 16
CY7C09159AV
CY7C09169AV
Pin Configuration
NC
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
NC
NC
100-Pin TQFP
(Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
1
75
NC
NC
2
74
NC
A7L
3
73
A7R
A8L
4
72
A8R
A9L
5
71
A9R
A10L
6
70
A10R
A11L
7
69
A11R
A12L
8
68
A12R
[3]A13L
9
67
A13R [3]
66
NC
NC
10
NC
11
NC
12
VCC
13
NC
14
NC
CY7C09169AV (16K x 9)
CY7C09159AV (8K x 9)
65
NC
64
NC
63
GND
62
NC
15
61
NC
NC
16
60
NC
NC
17
59
NC
CE0L
18
58
CE0R
CE1L
19
57
CE1R
CNTRSTL
20
56
CNTRSTR
R/WL
21
55
R/WR
OEL
22
54
OER
FT/PIPEL
23
53
FT/PIPER
NC
24
52
GND
NC
25
51
NC
NC
NC
I/O8R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/01R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
I/O8L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09159AV
CY7C09169AV
-9
CY7C09159AV
CY7C09169AV
-12
Unit
fMAX2 (Pipelined)
67
50
MHz
Max Access Time (Clock to Data, Pipelined)
9
12
ns
Typical Operating Current ICC
135
115
mA
Typical Standby Current for ISB1 (Both Ports TTL Level)
20
20
mA
Typical Standby Current for ISB3 (Both Ports CMOS Level)
10
10
µA
Note:
3. This pin is NC for CY7C09159AV.
Document #: 38-06053 Rev. *B
Page 3 of 16
CY7C09159AV
CY7C09169AV
Pin Definitions
Left Port
Right Port
Description
A0L–A13L
A0R–A13R
Address Inputs (A0−A12 for 8K; A0−A13 for 16K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to
their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual-port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current ..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied ..–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VCC+0.5V
DC Input Voltage......................................–0.5V to VCC+0.5V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 300 mV
Industrial[5]
–40°C to +85°C
3.3V ± 300 mV
Note:
4. The voltage on any input or I/O pin can not exceed the power pin during power-up
5. Industrial parts are available in CY7C09169AV only.
Document #: 38-06053 Rev. *B
Page 4 of 16
CY7C09159AV
CY7C09169AV
Electrical Characteristics Over the Operating Range
CY7C09159AV
CY7C09169AV
-9
Parameter
Description
Min.
VOH
Output HIGH Voltage (VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage (VCC = Min., IOH = +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Typ.
V
Ind.
V
10
0.8
20
75
95
155
Ind.[5]
Level)[6]
Com’l.
Ind.
10
500
85
115
[5]
Com’l.
Ind.[5]
V
10
µA
115
180
mA
155
250
mA
20
70
mA
–10
230
[5]
Com’l.
V
2.0
135
Com’l.
Unit
0.4
Ind.[5]
Level)[6]
Max.
2.4
0.4
–10
Standby Current (One Port CMOS Level)[6]
CEL | CER ≥ VIH, f = fMAX
ISB4
Min.
2.4
Com’l.
Standby Current (Both Ports CMOS
CEL & CER ≥ VCC – 0.2V, f = 0
ISB3
Max.
0.8
Standby Current (One Port TTL Level)[6]
CEL | CER ≥ VIH, f = fMAX
ISB2
Typ.
2.0
Standby Current (Both Ports TTL
CEL & CER ≥ VIH, f = fMAX
ISB1
-12
30
80
mA
85
140
mA
95
150
mA
10
500
µA
10
500
µA
75
100
mA
85
110
mA
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
10
pF
10
pF
AC Test Loads
3.3V
3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
OUTPUT
RTH = 250Ω
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
C = 5 pF
R2 = 435Ω
(c) Three-state Delay (Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
Note:
6. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Document #: 38-06053 Rev. *B
Page 5 of 16
CY7C09159AV
CY7C09169AV
Switching Characteristics Over the Operating Range
CY7C09159AV
-9
Parameter
Description
Min.
-12
Max.
Min.
Max.
Unit
fMAX1
fMax Flow-Through
40
33
MHz
fMAX2
fMax Pipelined
67
50
MHz
tCYC1
Clock Cycle Time - Flow-Through
25
30
ns
tCYC2
Clock Cycle Time - Pipelined
15
20
ns
tCH1
Clock HIGH Time - Flow-Through
12
12
ns
tCL1
Clock LOW Time - Flow-Through
12
12
ns
tCH2
Clock HIGH Time - Pipelined
6
8
ns
tCL2
Clock LOW Time - Pipelined
6
8
ns
tR
Clock Rise Time
3
3
ns
tF
Clock Fall Time
3
3
ns
tSA
Address Set-up Time
4
4
ns
tHA
Address Hold Time
1
1
ns
tSC
Chip Enable Set-up Time
4
4
ns
tHC
Chip Enable Hold Time
1
1
ns
tSW
R/W Set-up Time
4
4
ns
tHW
R/W Hold Time
1
1
ns
tSD
Input Data Set-up Time
4
4
ns
tHD
Input Data Hold Time
1
1
ns
tSAD
ADS Set-up Time
4
4
ns
tHAD
ADS Hold Time
1
1
ns
tSCN
CNTEN Set-up Time
4
4
ns
tHCN
CNTEN Hold Time
1
1
ns
tSRST
CNTRST Set-up Time
4
4
ns
tHRST
CNTRST Hold Time
1
1
ns
tOE
Output Enable to Data Valid
tOLZ
OE to Low Z
2
tOHZ
OE to High Z
1
7
ns
tCD1
Clock to Data Valid - Flow-Through
20
25
ns
tCD2
Clock to Data Valid - Pipelined
9
12
ns
tDC
Data Output Hold After Clock HIGH
tCKHZ
Clock HIGH to Output High Z
2
tCKLZ
Clock HIGH to Output Low Z
2
10
12
2
7
2
1
ns
2
9
2
ns
ns
9
2
ns
ns
Port to Port Delays
tCWDD
Write Port Clock High to Read Data Delay
40
40
ns
tCCS
Clock to Clock Set-up Time
15
15
ns
Document #: 38-06053 Rev. *B
Page 6 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[7, 8, 9, 10]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
An
ADDRESS
An+1
An+2
An+3
tCKHZ
tDC
tCD1
DATAOUT
Qn
Qn+1
Qn+2
tDC
tCKLZ
tOHZ
tOLZ
OE
tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[7, 8, 9, 10]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes:
7. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
8. ADS = VIL, CNTEN and CNTRST = VIH
9. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
10. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document #: 38-06053 Rev. *B
Page 7 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms (continued)
Bank Select Pipelined Read[11, 12]
-
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE0(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
tDC
A0
ADDRESS(B2)
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
D3
D1
D0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE0(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
D4
D2
tCKLZ
tCKLZ
Left Port Write to Flow-Through Right Port Read[13, 14, 15, 16]
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tHD
tSD
DATAINL
VALID
tCCS
CLKR
R/WR
ADDRESSR
tCD1
tSW
tSA
tHW
tHA
NO
MATCH
MATCH
tCWDD
DATAOUTR
tCD1
VALID
tDC
VALID
tDC
Notes:
11. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
12. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
13. The same waveforms apply for a right port write to flow-through left port read.
14. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
15. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
16. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Document #: 38-06053 Rev. *B
Page 8 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[10, 17, 18, 19]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
An+2
An+2
An+3
An+4
tSD tHD
tHA
DATAIN
tCD2
tCKHZ
Dn+2
tCD2
tCKLZ
Qn
DATAOUT
READ
Pipelined Read-to-Write-to-Read (OE
tCH2
tCYC2
Qn+3
NO OPERATION
WRITE
READ
Controlled)[10, 17, 18, 19]
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
ADDRESS
tSW tHW
tSW
tHW
An
tSA
An+1
An+2
tHA
An+3
An+4
An+5
tSD tHD
Dn+2
DATAOUT
Dn+3
tCD2
DATAIN
tCKLZ
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes:
17. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
18. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
19. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06053 Rev. *B
Page 9 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[8, 10, 17, 18, 19]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
DATAIN
An+2
An+2
tSD
tHA
An+3
tHD
Dn+2
tCD1
tCD1
DATAOUT
An+4
tCD1
Qn
Qn+1
tDC
tCKHZ
READ
tCD1
Qn+3
tCKLZ
NO
OPERATION
WRITE
tDC
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[8, 10, 17, 18, 19]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
DATAIN
An+1
tSD
tHA
An+3
An+4
An+5
tHD
Dn+2
tDC
tCD1
DATAOUT
An+2
Dn+3
tOE
tCD1
Qn
tCD1
Qn+4
tOHZ
tCKLZ
tDC
OE
READ
Document #: 38-06053 Rev. *B
WRITE
READ
Page 10 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[20]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx-1
tCD2
Qx
READ
EXTERNAL
ADDRESS
Qn
tDC
Qn+1
READ WITH COUNTER
Qn+2
COUNTER HOLD
Qn+3
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[20]
tCH1
tCYC1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
tCD1
Qx
Qn
Qn+1
Qn+2
Qn+3
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ
WITH
COUNTER
Note:
20. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Document #: 38-06053 Rev. *B
Page 11 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[21, 22]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Notes:
21. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
22. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Document #: 38-06053 Rev. *B
Page 12 of 16
CY7C09159AV
CY7C09169AV
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[10, 17, 23, 24]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
AX
0
tSW
tHW
tSD
tHD
1
An+1
An
An+1
R/W
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
ADS
CNTEN
CNTRST
DATAIN
D0
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
Q1
Qn
READ
ADDRESS n
Notes:
23. CE0 = VIL; CE1 = VIH.
24. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06053 Rev. *B
Page 13 of 16
CY7C09159AV
CY7C09169AV
Read/Write and Enable Operation[25, 26, 27]
Inputs
OE
CLK
CE0
Outputs
CE1
R/W
I/O0–I/O9
Operation
[28]
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected[28]
X
L
H
L
DIN
L
L
H
H
DOUT
Read[28]
L
H
X
High-Z
Outputs Disabled
H
X
Write
Address Counter Control Operation[25, 29, 30, 31]
Address
Previous
Address
X
X
CLK
ADS
CNTEN
CNTRST
I/O
Mode
X
X
L
Dout(0)
Reset
Counter Reset to Address 0
Operation
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
H
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
Notes:
25. “X” = “don’t care,” “H” = VIH, “L” = VIL.
26. ADS, CNTEN, CNTRST = “don’t care.”
27. OE is an asynchronous input signal.
28. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
29. CE0 and OE = VIL; CE1 and R/W = VIH.
30. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle.
31. Counter operation is independent of CE0 and CE1.
Document #: 38-06053 Rev. *B
Page 14 of 16
CY7C09159AV
CY7C09169AV
Ordering Information
8K x9 3.3V Synchronous Dual-Port SRAM
Speed
(ns)
9
12
Ordering Code
Package
Name
Operating
Range
Package Type
CY7C09159AV-9AC
A100
100-Pin Thin Quad Flat Pack
CY7C09159AV-9AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
CY7C09159AV-12AC
A100
100-Pin Thin Quad Flat Pack
CY7C09159AV-12AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
Commercial
16K x9 3.3V Synchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Operating
Range
Package Type
9
CY7C09169AV-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
12
CY7C09169AV-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09169AV-12AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
CY7C09169AV-12AI
A100
100-Pin Thin Quad Flat Pack
CY7C09169AV-12AXI
A100
100-Pin Pb-Free Thin Quad Flat Pack
Industrial
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06053 Rev. *B
Page 15 of 16
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C09159AV
CY7C09169AV
Document History Page
Document Title: CY7C09159AV/CY7C09169AV 3.3V 8K/16K x 9 Synchronous Dual Port SRAM
Document Number: 38-06053
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110205
11/15/01
SZV
Change from Spec number: 38-00839 to 38-06053
*A
122303
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
*B
393581
See ECN
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C09159AV-9AXC, CY7C09159AV-12AXC, CY7C09169AV-12AXC,
CY7C09169AV-12AXI
Document #: 38-06053 Rev. *B
Page 16 of 16