ETC INA-32063-BLK

3.0 GHz Wideband Silicon
RFIC Amplifier
Technical Data
INA-32063
Features
• 17 dB Gain at 1.9 GHz
Surface Mount SOT-363
(SC-70) Package
• +3 dBm P1 dB at 1.9 GHz
• Single +3V Supply
• Unconditionally Stable
Applications
Pin Connections and
Package Marking
GND 2 1
GND 1 2
32
• LO Buffer and Driver
Amplifier for Cellular,
Cordless, Special Mobile
Radio, PCS, ISM, Wireless
LAN, DBS, TVRO, and TV
Tuner
INPUT 3
6 OUTPUT
& Vd
5 GND 1
4 Vd
Note: Package marking provides
orientation and identification.
Simplified Schematic
Vd
Output & Vd
Input
Gnd1
Gnd2
Description
Hewlett-Packard’s INA-32063 is a
Silicon RFIC amplifier that offers
excellent gain and output power
for applications to 3.0 GHz.
Packaged in an ultraminiature
SOT-363 package, it requires half
of the board space of a SOT-143
package.
The INA-32063 offers wide
bandwidth and good linearity and
17 dB gain with a modest supply
current. With its input and output
matched internally to 50 Ω, the
INA-32063 is a simple to use gain
block that is suitable for
numerous applications.
The INA-32063 is fabricated using
HP’s 30 GHz – fmax, ISOSAT™
Silicon-bipolar process that uses
nitride, self-alignment,
submicrometer lithography,
trench isolation, ion implantation,
and polyimide intermetal dielectric and scratch protection to
achieve superior performance,
uniformity and reliability.
2
Absolute Maximum Ratings
Symbol
Parameter
Units
Absolute
Maximum[1]
Vd
Device Voltage,
RF output to ground
V
6.0
Pin
CW RF Input Power
dBm
+7.0
Tj
Junction Temperature
°C
150
TSTG
Storage Temperature
°C
-65 to 150
Thermal Resistance[2]:
θjc = 170°C/W
Notes:
1. Operation of this device above any one
of these limits may cause permanent
damage.
2. TC = 25°C (TC is defined to be the
temperature at the package pins where
contact is made to the circuit board)
INA-32063 Electrical Specifications, TC = 25°C, ZO = 50 Ω,Vd = 3 V
Symbol
|S 21| 2
NF50
P1dB
IP3
VSWRin
VSWRout
Ιd
Parameters and Test Conditions
Gain in 50 Ω system
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Noise Figure
f = 1.9 GHz
Output Power at 1 dB Gain Compression
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Output Third Order Intercept Point
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Input VSWR
f = 0.1 – 2.4 GHz
Output VSWR
f = 0.1 – 2.4 GHz
Device Current
Units Min.
dB
15.5[3]
dB
dBm
dBm
mA
Typ. Max. Std.
Dev.[4]
16.8
17.8
0.39
18.2
4.4
0.21
3.6
4.8
4.0
15.3
14.4
11.5
1.1:1
1.6:1
20
25 [3]
1.1
Notes:
3. Guaranteed specifications are 100% tested in production.
4. Standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots
during the initial characterization of this product, and is intended to be used as an estimate for distribution of the
typical specification.
3
INA-32063 Typical Performance, TC = 25°C, ZO = 50 Ω, V d = 3 V
25
6
8
2.7 V
3.0 V
3.3 V
NOISE FIGURE (dB)
GAIN (dB)
20
15
10
5
4.5
4
2.7 V
3.0 V
3.3 V
5
0
0.5
1.0
2.0
2.5
3.0
0.5
1.0
2.5
3.0
0
20
10
P1 dB (dBm)
4
2
4
0
3
1.5
2.0
2.5
-2
0
3.0
0.5
1.0
1.5
2.0
2.5
0
3.0
15
2.5
3.0
FREQUENCY (GHz)
Figure 7. Input and Output VSWR vs.
Frequency.
-40°C
+25°C
+85°C
8
0
2.0
12
10
5
0
3.0
14
20
10
VSWR in
VSWR out
2.5
16
IP3 (dBm)
Id (mA)
1
2.0
18
25
1.5
1.5
Figure 6. Output Power for 1 dB Gain
Compression vs. Frequency and
Temperature.
-40°C
+25°C
+85°C
30
2
1.0
FREQUENCY (GHz)
Figure 5. Noise Figure vs. Frequency
and Temperature.
2.5
1.5
0.5
FREQUENCY (GHz)
35
1.0
3.0
-40°C
+25°C
+85°C
6
4.5
3
4
0.5
2.5
3.5
Figure 4. Gain vs. Frequency and
Temperature.
0
2.0
8
FREQUENCY (GHz)
0.5
1.5
Figure 3. Output Power for 1 dB Gain
Compression vs. Frequency and
Voltage.
-40°C
+25°C
+85°C
5
-40°C
+25°C
+85°C
1.0
1.0
5.5
NOISE FIGURE (dB)
15
0.5
0.5
FREQUENCY (GHz)
6.5
6
GAIN (dB)
2.0
Figure 2. Noise Figure vs. Frequency
and Voltage.
25
VSWR
1.5
FREQUENCY (GHz)
Figure 1. Gain vs. Frequency and
Voltage.
0
2
-2
0
FREQUENCY (GHz)
5
4
0
3.5
1.5
2.7 V
3.0 V
3.3 V
6
P1 dB (dBm)
5.5
6
0
1
2
3
4
5
Vd (V)
Figure 8. Supply Current vs. Voltage
and Temperature.
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
Figure 9. Third Order Intercept
Point, IP3 vs. Frequency and
Temperature.
3.0
4
INA-32063 Typical Scattering Parameters[5], TC = 25°C, ZO = 50 Ω,Vd = 3.0 V
Freq.
GHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
Mag
S11
Ang
dB
S21
Mag
Ang
dB
S12
Mag
Ang
0.034
0.034
0.039
0.043
0.053
0.054
0.059
0.065
0.072
0.080
0.084
0.090
0.096
0.101
0.107
0.109
0.108
0.110
0.113
0.118
0.121
0.129
0.138
0.151
0.163
0.175
0.189
0.199
0.208
0.216
0.224
0.234
0.243
0.254
0.266
0.280
0.292
0.301
0.309
0.317
0.323
0.327
0.328
0.331
0.333
0.334
0.337
0.338
0.342
0.347
19
30
35
41
53
49
49
50
49
47
48
46
45
46
45
43
41
38
36
32
26
20
13
6
-1
-7
-13
-19
-26
-33
-40
-48
-57
-64
-71
-77
-83
-88
-92
-97
-101
-105
-109
-113
-117
-122
-126
-130
-134
-137
16.5
16.5
16.6
16.6
16.6
16.7
16.7
16.8
16.8
16.9
17.0
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
18.0
18.1
18.1
18.2
18.2
18.1
18.0
17.9
17.8
17.6
17.3
17.1
16.8
16.5
16.1
15.8
15.4
14.9
14.5
14.1
13.7
13.3
12.9
12.4
12.0
11.6
11.2
10.8
10.4
10.0
6.72
6.71
6.73
6.75
6.78
6.80
6.85
6.90
6.94
7.00
7.09
7.16
7.23
7.32
7.40
7.48
7.59
7.69
7.79
7.88
7.98
8.03
8.06
8.09
8.09
8.04
7.96
7.84
7.73
7.56
7.36
7.16
6.92
6.67
6.39
6.13
5.86
5.58
5.32
5.07
4.84
4.61
4.39
4.19
3.99
3.81
3.63
3.47
3.31
3.17
-4
-9
-13
-17
-22
-26
-30
-35
-39
-44
-48
-53
-58
-62
-67
-72
-77
-83
-88
-94
-100
-106
-112
-119
-125
-132
-138
-145
-152
-158
-165
-171
-177
176
170
165
159
154
149
144
139
134
130
126
122
118
114
110
106
103
-26.8
-27.9
-27.7
-28.3
-28.3
-28.0
-28.5
-28.9
-29.1
-29.2
-29.1
-29.3
-29.5
-29.8
-29.9
-29.6
-29.9
-30.1
-30.5
-30.6
-30.8
-31.1
-31.3
-31.5
-31.6
-32.0
-32.3
-32.8
-33.3
-33.6
-34.2
-35.1
-35.8
-36.7
-37.1
-38.3
-38.8
-39.0
-38.3
-37.6
-36.5
-35.3
-34.0
-32.8
-31.7
-30.7
-29.8
-29.0
-28.0
-27.2
0.046
0.040
0.041
0.039
0.038
0.040
0.038
0.036
0.035
0.035
0.035
0.034
0.033
0.033
0.032
0.033
0.032
0.031
0.030
0.029
0.029
0.028
0.027
0.027
0.026
0.025
0.024
0.023
0.022
0.021
0.019
0.018
0.016
0.015
0.014
0.012
0.011
0.011
0.012
0.013
0.015
0.017
0.020
0.023
0.026
0.029
0.032
0.036
0.040
0.044
3
0
-3
-10
-7
-10
-12
-13
-12
-11
-13
-15
-15
-15
-14
-16
-19
-20
-22
-23
-25
-27
-29
-31
-34
-37
-42
-46
-51
-56
-63
-70
-78
-86
-97
-110
-121
-130
-142
-152
-160
-166
-173
-178
177
172
168
165
162
159
Note:
5. Reference plane per Figure 15 in Applications Information section.
Mag
0.215
0.230
0.227
0.238
0.226
0.218
0.223
0.224
0.220
0.215
0.211
0.211
0.206
0.205
0.204
0.194
0.193
0.194
0.197
0.198
0.206
0.214
0.220
0.225
0.232
0.242
0.247
0.250
0.250
0.249
0.246
0.239
0.229
0.220
0.212
0.196
0.182
0.170
0.156
0.139
0.124
0.110
0.095
0.079
0.065
0.052
0.041
0.031
0.022
0.013
S 22
Ang
-5
-6
-7
-8
-8
-9
-12
-16
-21
-25
-29
-33
-40
-47
-55
-63
-68
-77
-85
-94
-101
-111
-120
-128
-135
-143
-151
-160
-166
-173
180
173
168
163
157
151
146
142
136
131
125
120
112
101
88
68
42
15
-5
-17
K
Factor
1.68
1.89
1.84
1.91
1.96
1.87
1.94
2.02
2.05
2.03
2.06
2.10
2.07
2.10
2.11
2.04
2.07
2.10
2.13
2.17
2.13
2.17
2.22
2.20
2.26
2.33
2.42
2.53
2.67
2.84
3.20
3.46
4.02
4.44
4.95
6.00
6.84
7.18
6.90
6.69
6.08
5.64
5.05
4.61
4.30
4.04
3.85
3.59
3.39
3.22
5
The Vd connection to the amplifier is RF bypassed by placing a
capacitor to ground near the Vd
pin of the amplifier package.
INA-32063 Applications
Information
Introduction
The INA-32063 is a +3 volt silicon
RFIC amplifier that is designed
with a two stage internal network
to provide a broadband gain and
50 Ω input and output impedance.
With a typical +4.8 dBm P-1 dB
compressed output power at
1900 MHz, for only 20 mA supply
current. The broad bandwidth,
INA-32063, is well suited for
amplifier applications in mobile
communication systems.
A feature of the INA-32063 is a
positive gain slope over the
1–2.5 GHz range that is useful in
many satellite-based TV and
datacom systems.
In addition to use in buffer and
driver amplifier applications in
the cellular market, the
INA-32063 will find many
applications in battery operated
wireless communication systems.
Operating Details
The INA-32063 is a voltage-biased
device that operates from a
+3 volt power supply with a
typical current drain of 20 mA. All
bias regulation circuitry is
integrated into the RFIC.
Figure 10 shows a typical implementation of the INA-32063. The
supply voltage for the INA-32063
must be applied to two terminals,
the Vd pin and the RF Output pin.
32
Gnd1
Gnd1
RF
Output
RFC
Vd
RF
Input
Cblock
Figure 10. Basic Amplifier
Application.
Blocking capacitors are normally
placed in series with the RF Input
and the RF Output to isolate the
DC voltages on these pins from
circuits adjacent to the amplifier.
The values for the blocking and
bypass capacitors are selected to
provide a reactance at the lowest
frequency of operation that is
small relative to 50 Ω.
Cbypass
Gnd 1
Gnd 2
VIA
Figure 12. INA-32063 Potential
Ground Loop.
Gnd 1
VIA
Gnd 2
VIA
Example Layout for 50 Ω
Output Amplifier
Figure 13. INA-32063 Suggested
Layout.
An example layout for an amplifier using the INA-32063 with
50 Ω input and 50 Ω output is
shown in Figure 11.
At least one ground via should be
placed adjacent to each ground
pin to assure good RF grounding.
Multiple vias are used to reduce
the inductance of the path to
ground and should be placed as
close to the package terminals as
practical.
Gnd 1
RF Input
50 Ω
Gnd 2
50 Ω
RF Output
and Vd
Gnd 1
Figure 11. RF Layout.
Cout
Gnd2
The power supply connection to
the RF Output pin is achieved by
means of a RF choke (inductor).
The value of the RF choke must
be large relative to 50 Ω in order
to prevent loading of the RF
Output. The supply voltage end of
the RF choke is bypassed to
ground with a capacitor. If the
physical layout permits, this can
be the same bypass capacitor that
is used at the Vd terminal of the
amplifier.
are used to bring the ground to
the topside of the circuit where
needed. The performance of
INA-32063 is sensitive to ground
path inductance. The two-stage
design creates the possibility of a
feedback loop being formed
through the ground returns of the
stages, Gnd 1 and Gnd 2.
This example uses a
microstripline design (solid
groundplane on the backside of
the circuit board). The circuit
board material is 0.031-inch thick
FR-4. Plated through holes (vias)
The effects of the potential
ground loop shown in Figure 12
may be observed as a “peaking” in
the gain versus frequency
response, an increase in input
VSWR, or even as return gain at
the input of the INA-32063.
Figure 14 shows an assembled
amplifier. The +3 volt supply is
fed directly into the Vd pin of the
6
INA-32063 and into the RF Output
pin through the RF choke (RFC).
Capacitor C3 provides RF bypassing for both the V d pin and the
power supply end of the RFC.
Capacitor C4 is optional and may
be used to add additional bypassing for the V d line. A well-bypassed Vd line is especially
necessary in cascades of amplifier stages to prevent oscillation
that may occur as a result of RF
feedback through the power
supply lines.
A convenient method for making
RF connection to the demonstration board is to use a PCB mounting type of SMA connector
(Johnson 142-0701-881, or
equivalent). These connectors
can be slipped over the edge of
the PCB and the center conductor
soldered to the input and output
lines. The ground pins of the
connectors can be soldered to the
ground plane on the backside of
board.
C1
C2
32
For this demonstration circuit,
the value chosen for the RF
choke was 120 nH (Coilcraft
1008CS-221, TOKO LL2012 -F or
equivalent). All of the blocking
and bypass capacitors are 100 pF.
The gap in the output transmission line was bridged using
copper foil cut to size. These
values provide excellent amplifier
performance from under 50 MHz
through 2.4 GHz. Larger values
for the choke and capacitors can
be used to extend the lower end
of the bandwidth. Since the gain
of the INA-32063 extends down to
DC, the frequency response of the
amplifier is limited only by the
values of the capacitors and
choke.
INA-3XX63 DEMO BOARD
RFC
C3
C4
Vd
Figure 14. Assembled Amplifier.
PCB Materials
Typical choices for PCB material
for low cost wireless applications
are FR-4 or G-10 with a thickness
of 0.025 (0.635 mm) or
0.031inches (0.787 mm) A thickness of 0.062 inches (1.574 mm) is
the maximum that is recommended for use with this particular device. The use of a thicker
board material increases the
inductance of the plated through
vias used for RF grounding and
may deteriorate circuit performance. Adequate grounding is
needed not only to obtain maximum amplifier performance but
also to reduce any possibility of
instability.
Phase Reference Planes
The positions of the reference
planes used to measure S-Parameters for this device are shown in
Figure 15. As seen in the illustration, the reference planes are
located at the point where the
package leads contact the test
circuit.
REFERENCE
PLANES
TEST CIRCUIT
Figure 15. Phase Reference Planes.
SOT-363 PCB Layout
The INA-32063 is packaged in the
miniature SOT-363 (SC-70)
surface mount package. A PCB
pad layout for the SOT-363
package is shown in Figure 16
(dimensions are in inches). This
layout provides ample allowance
for package placement by automated assembly equipment
without adding pad parasitics that
could impair the high frequency
performance of the INA-32063.
The layout that is shown with a
nominal SOT-363 package footprint superimposed on the PCB
pads for reference.
7
0.026
0.075
0.035
0.016
Figure 16. PCB Pad Layout for
INA-32063 (dimensions in inches).
Statistical Parameters
Several categories of parameters
appear within this data sheet.
Parameters may be described
with values that are either
“minimum or maximum,”
“typical,” or “standard
deviations.” The values for
parameters are based on comprehensive product characterization
data, in which automated measurements are made on a large
number of parts taken from
3 non-consecutive process lots of
semiconductor wafers. The data
derived from product characterization tends to be normally
distributed, e.g., fits the standard
“bell curve.”
Parameters considered to be the
most important to system performance are bounded by minimum
or maximum values. For the
INA-32063, these parameters are:
Power Gain (|S21| 2 ) and the
Device Current (Id). Each of
these guaranteed parameters is
100% tested. Values for most of
the parameters in the table of
Electrical Specifications that are
described by typical data are the
mathematical mean (µ), of the
normal distribution taken from
the characterization data. For
parameters where measurements
or mathematical averaging may
not be practical, such as
S-parameters or Noise Parameters and the performance
curves, the data represents a
nominal part taken from the
“center” of the characterization
distribution. Typical values are
intended to be used as a basis for
electrical design.
To assist designers in optimizing
not only the immediate circuit
using the INA-32063, but to also
optimize and evaluate trade-off
that affect a complete wireless
system, the standard deviation
(σ) is provided for many of the
Electrical Specifications parameters (at 25°C) in addition to the
mean. The standard deviation is a
measure of the variability about
the mean. It will be recalled that a
normal distribution is completely
described by the mean and
standard deviation.
Standard statistics tables or
calculations provide the probability of a parameter falling between
any two values, usually symmetrically located about the mean.
Referring to Figure 17 for example, the probability of a
parameter being between ±1σ is
68.3%; between ±2σ is 95.4%; and
between ±3σ is 99.7%.
68%
95%
99%
-3σ
-2σ
-1σ Mean +1σ +2σ
(µ), typ
+3σ
Parameter Value
Figure 17. Normal Distribution.
SMT Assembly
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
low mass, such as the SOT-363
package, will reach solder reflow
temperatures faster than those
with a greater mass.
The INA-32063 has been qualified
to the time-temperature profile
shown in Figure 18. This profile is
representative of an IR reflow
type of surface mount assembly
process.
After ramping up from room
temperature, the circuit board
with components attached to it
(held in place with solder paste)
passes through one or more
preheat zones. The preheat zones
increase the temperature of the
board and components to prevent
thermal shock and begin evaporating solvents from the solder
paste. The reflow zone briefly
elevates the temperature sufficiently to produce a reflow of the
solder. The rates of change of
temperature for the ramp-up and
cool down zones are chosen to be
low enough to not cause deformation of the board or damage to
components due to thermal
shock.
For more information on mounting considerations for packaged
microwave semiconductors
8
please refer to Hewlett-Packard
application note AN-A006.
Electrostatic Sensitivity
These parameters are typical for
a surface mount assembly
process for the INA-32063. As a
general guideline, the circuit
board and components should
only be exposed to the minimum
temperatures and times necessary
to achieve a uniform reflow of
solder.
RFICs are electrostatic
discharge (ESD)
sensitive devices.
Although the
INA-32063 is robust in design,
permanent damage may occur to
these devices if they are subjected to high-energy electrostatic
discharges. Electrostatic charges
as high as several thousand volts
(which readily accumulate on the
The INA-32063 is an ESD Class 1
device. Therefore, proper ESD
precautions are recommended
when handling, inspecting, and
assembling these devices to avoid
damage.
250
TMAX
TEMPERATURE (°C)
200
150
For more information on Electrostatic Discharge and Control refer
to Hewlett-Packard application
note AN-A004R.
Reflow
Zone
100
Preheat
Zone
Cool Down
Zone
50
0
0
60
120
180
TIME (seconds)
Figure 18. Surface Mount Assembly Profile.
human body and on test equipment) can discharge without
detection and may result in
degradation in performance or
failure. Electronic devices may be
subjected to ESD damage in any
of the following areas:
• Storage & handling
• Inspection & testing
• Assembly
• In-circuit use
240
300
9
Package Dimensions
Outline 63 (SOT-363/SC-70)
1.30 (0.051)
REF.
2.20 (0.087)
2.00 (0.079)
1.35 (0.053)
1.15 (0.045)
0.650 BSC (0.025)
0.425 (0.017)
TYP.
2.20 (0.087)
1.80 (0.071)
0.10 (0.004)
0.00 (0.00)
0.30 REF.
1.00 (0.039)
0.80 (0.031)
0.25 (0.010)
0.15 (0.006)
10°
0.30 (0.012)
0.10 (0.004)
0.20 (0.008)
0.10 (0.004)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
INA-32063 Part Number Ordering Information
Part Number
Devices per Container
Container
INA-32063-BLK
100
tape strip in antistatic bag
INA-32063-TR1
3,000
7" reel
INA-32063-TR2
10,000
13" reel
Tape Dimensions and Product Orientation
For Outline 63
P
P2
D
P0
E
F
W
C
32
32
D1
t1 (CARRIER TAPE THICKNESS)
Tt (COVER TAPE THICKNESS)
K0
8° MAX.
A0
DESCRIPTION
5° MAX.
B0
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
2.24 ± 0.10
2.34 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.088 ± 0.004
0.092 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 + 0.010
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
THICKNESS
W
t1
8.00 ± 0.30
0.255 ± 0.013
0.315 ± 0.012
0.010 ± 0.0005
COVER TAPE
WIDTH
TAPE THICKNESS
C
Tt
5.4 ± 0.10
0.062 ± 0.001
0.205 ± 0.004
0.0025 ± 0.00004
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P2
2.00 ± 0.05
0.079 ± 0.002
www.hp.com/go/rf
For technical assistance or the location of
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office, distributor or representative call:
Americas/Canada: 1-800-235-0312 or
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Far East/Australasia: Call your local HP
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Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1998 Hewlett-Packard Co.
Printed in U.S.A.
5967-5769E (5/98)