RoboClock®, CY7B9950 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer Features Description The CY7B9950 RoboClock® is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high performance computer and communication systems. ■ 2.5V or 3.3V operation ■ Split output bank power supplies ■ Output frequency range: 6 MHz to 200 MHz ■ 50 ps typical matched-pair Output-output skew ■ 50 ps typical Cycle-cycle jitter ■ 49.5/50.5% typical output duty cycle ■ Selectable output drive strength ■ Selectable positive or negative edge synchronization ■ Eight LVTTL outputs driving 50 Ω terminated lines ■ LVCMOS/LVTTL over-voltage-tolerant reference input ■ Phase adjustments in 625-/1250-ps steps up to +7.5 ns ■ 2x, 4x multiply and (1/2)x, (1/4)x divide ratios ■ Spread-Spectrum compatible ■ Industrial temp. range: –40°C to +85°C ■ 32-pin TQFP package The user can program the phase of the output banks through nF[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to the feedback input to achieve different reference frequency multiplications, and divide ratios and zero input-output delay. The device also features split output bank power supplies, which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising, or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from ± 12 mA to ± 24 mA(3.3V). Logic Block Diagram TEST PE/HD FS 3 3 REF VDDQ1 3 PLL FB 3 1F1:0 3 3 2F1:0 3 3 3F1:0 3 1Q0 Phase Select 1Q1 2Q0 Phase Select 2Q1 3Q0 Phase Select and /K 3Q1 VDDQ3 3 4F1:0 3 4Q0 Phase Select and /M 4Q1 VDDQ4 sOE# Cypress Semiconductor Corporation Document #: 38-07338 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 27, 2007 [+] Feedback CY7B9950 Pinouts 3F1 Document #: 38-07338 Rev. *D REF VSS TEST 2F1 2F0 27 26 25 VDD 30 28 FS 31 29 3F0 32 Figure 1. Pin Diagram - 32 Pin TQFP package Top view 1 2 3 24 1F1 4F0 4F1 23 22 1F0 PE/HD VDDQ4 4 5 21 20 VDDQ1 1Q0 4Q1 4Q0 VSS 6 7 19 18 1Q1 8 17 9 10 11 12 13 14 15 16 VSS 3Q1 3Q0 VDDQ3 FB VDD 2Q1 2Q0 CY7B9950 sOE# VSS VSS Page 2 of 12 [+] Feedback CY7B9950 Table 1. Pin Definitions Name IO[1] REF I 13 FB I LVTTL 27 TEST I Three-level When MID or HIGH, disables Phase-locked Loop (PLL)[3]. REF goes to outputs of Bank 1 and Bank 2. REF also goes to outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for normal operation. 22 sOE# I, PD Two-level Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0, and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. 4 PE/HD I, PU Three-level Selects Positive or Negative Edge Control and High or Low Output Drive Strength. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. When at MID level, the output drive strength is increased and the outputs synchronize with the positive edge of the reference clock (see Table 7 on page 4). 24, 23, 26, 25, 1, 32, 3, 2 nF[1:0] I Three-level Select Frequency and Phase of the Outputs (see Table 2, Table 3, Table 4 on page 4, Table 5 on page 4, and Table 6 on page 4). I Three-level O LVTTL Four Banks of Two Outputs (see Table 2, Table 3, and Table 4 on page 4) Pin 29 31 FS 19, 20, 15, nQ[1:0] 16, 10, 11, 6, 7 Type Description LVTTL/LVCMOS Reference Clock Input. Feedback Input. Selects VCO Operating Frequency Range (see Table 5 on page 4) 21 VDDQ1[2] PWR Power Power Supply for Bank 1 and Bank 2 Output Buffers (see Table 8 on page 4 for supply level constraints). 12 VDDQ3[2] PWR Power Power Supply for Bank 3 Output Buffers (see Table 8 on page 4 for supply level constraints). 5 VDDQ4[2] PWR Power Power Supply for Bank 4 Output Buffers (see Table 8 on page 4 for supply level constraints). 14,30 8,9,17,18,28 VDD[2] PWR Power Power Supply for Internal Circuitry (see Table 8 on page 4 for supply level constraints). VSS PWR Power Ground Device Configuration Table 3. Output Divider Settings — Bank 4 The outputs of the CY7B9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 2 and Table 3, respectively. Table 2. Output Divider Settings — Bank 3 3F[1:0] K — Bank3 Output Divider LL 2 HH 4 Other[4] 1 4F[1:0] M — Bank4 Output Divider LL 2 Other[4] 1 The three-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY7B9950 PLL operating frequency range that corresponds to each FS level is given in Table 4 on page 4. Notes 1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer 2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic are cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 4. These states are used to program the phase of the respective banks (see Table 6 on page 4). Document #: 38-07338 Rev. *D Page 3 of 12 [+] Feedback CY7B9950 Table 4. Frequency Range Select FS PLL Frequency Range L 24 to 50 MHz the tU value is: tU = 1 / (fNOM x MF), where MF is a multiplication factor, which is determined by the FS setting as indicated in Table 5. Table 5. MF Calculation M 48 to 100 MHz FS MF fNOM at which tU is 1.0 ns(MHz) H 96 to 200 MHz L 32 31.25 M 16 62.5 H 8 125 The selectable output skew is in discrete increments of time units (tU).The value of tU is determined by the FS setting and the maximum nominal frequency. The equation used to determine Table 6. Output Skew Settings nF[1:0] Skew (1Q[0:1],2Q[0:1]) Skew (3Q[0:1]) Skew (4Q[0:1]) LL[5] –4tU Divide By 2 Divide By 2 LM –3tU –6tU v6tU LH –2tU –4tU –4tU ML –1tU –2tU v2tU MM Zero Skew Zero Skew Zero Skew MH +1tU +2tU +2tU HL +2tU +4tU +4tU HM +3tU +6tU +6tU HH +4tU Divide By 4 Inverted[6] In addition to determining whether the outputs synchronize to the rising or the falling edge of the reference signal, the 3-level PE/HD pin controls the output buffer drive strength as indicated in Table 7. The CY7B9950 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level that is equal or higher than on any one of the output power supplies. Governing Agencies The following agencies provide specifications that apply to the CY7B9950. The agency name and relevant specification is listed below. Table 9. Governing Agencies and Specifications Agency Name JEDEC Table 7. PE/HD Settings Specification JESD 51 (Theta JA) JESD 65 (Skew, Jitter) PE/HD Synchronization Output Drive Strength[7] IEEE 1596.3 (Jitter Specs) L Negative Low Drive UL-194_V0 94 (Moisture Grading) M Positive High Drive MIL H Positive Low Drive 883E Method 1012.1 (Therma Theta JC) Table 8. Power Supply Constraints VDD VDDQ1[8] VDDQ3[8] VDDQ4[8] 3.3V 3.3V or 2.5V 3.3V or 2.5V 3.3V or 2.5V 2.5V 2.5V 2.5V 2.5V Notes: 5. LL disables outputs if TEST = MID and sOE# = HIGH. 6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID and sOE# disables them LOW when PE/HD = LOW. 7. Please refer to “DC Parameters” section for IOH/IOL specifications. 8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V. Document #: 38-07338 Rev. *D Page 4 of 12 [+] Feedback CY7B9950 Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Operating Voltage Functional @ 2.5V ± 5% 2.375 2.625 V VDD Operating Voltage Functional @ 3.3V ± 10% 2.97 3.63 V VIN(MIN) Input Voltage Relative to VSS VSS – 0.3 – V VIN(MAX) Input Voltage Relative to VDD – VDD + 0.3 V TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional – 155 °C ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 42 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 105 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating MSL Moisture Sensitivity Level FIT Failure in Time At 1/8 in. V–0 1 Manufacturing Testing 10 ppm DC Electrical Specifications at 2.5V Parameter Description Condition VDD 2.5 Operating Voltage 2.5V ± 5% VIL Input LOW Voltage REF, FB and sOE# Inputs VIH Input HIGH Voltage VIHH [9] Input HIGH Voltage Min Max Unit 2.375 2.625 V – 0.7 V 1.7 – V 3-Level Inputs – VDD – 0.4 (TEST, FS, nF[1:0], PE/HD) (These pins V /2 – 0.2 V /2 + 0.2 DD are normally wired to VDD, GND or uncon- DD – 0.4 nected.) VIMM[9] Input MID Voltage VILL[9] Input LOW Voltage IIL Input Leakage Current VIN = VDD/GND, VDD = max. (REF and FB inputs) I3 3-Level Input DC Current HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) V V V –5 5 μA – 200 μA –50 50 μA –200 – μA IPU Input Pull-up Current VIN = VSS, VDD = max. –25 – μA IPD Input Pull-down Current VIN = VDD, VDD = max., (sOE#) – 100 μA VOL Output LOW Voltage VOH Output HIGH Voltage IOL = 12 mA (PE/HD = L/H), (nQ[0:1]) – 0.4 V IOL = 20 mA (PE/HD = MID), (nQ[0:1]) – 0.4 V IOH = –12 mA (PE/HD = L/H), (nQ[0:1]) 2.0 – V IOH = –20 mA (PE/HD = MID), (nQ[0:1]) 2.0 – V – 2 mA IDDQ Quiescent Supply Current VDD = max., TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded IDD Dynamic Supply Current At 100 MHz CIN Input Pin Capacitance 150 mA 4 pF Note 9. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. Document #: 38-07338 Rev. *D Page 5 of 12 [+] Feedback CY7B9950 DC Specifications at 3.3V Parameter Description Condition VDD 3.3 Operating Voltage 3.3V ± 10% VIL Input LOW Voltage REF, FB and sOE# Inputs VIH Input HIGH Voltage VIHH[9] Input HIGH Voltage VIMM[9] Input MID Voltage VILL[9] Input LOW Voltage IIL Input Leakage Current VIN = VDD/GND,VDD = max. (REF and FB inputs) I3 3-Level Input DC Current HIGH, VIN = VDD 3-Level Inputs (TEST, FS, nF[1:0], PE/HD) (These pins are normally wired to VDD,GND or unconected.) MID, VIN = VDD/2 LOW, VIN = VSS 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) IPU Input Pull-up Current VIN = VSS, VDD = max. Min Max Unit 2.97 3.63 V – 0.8 V 2.0 – V VDD – 0.6 – V VDD/2 – 0.3 VDD/2 + 0.3 V – 0.6 V –5 5 μA – 200 μA –50 50 μA –200 – μA –100 – μA IPD Input Pull-down Current VIN = VDD, VDD = max., (sOE#) – 100 μA VOL Output LOW Voltage IOL = 12 mA (PE/HD = L/H), (nQ[0:1]) – 0.4 V IOL = 24 mA (PE/HD = MID), (nQ[0:1]) – 0.4 V VOH Output HIGH Voltage IOH = –12 mA (PE/HD = L/H), (nQ[0:1]) 2.4 – V IOH = –24 mA (PE/HD = MID), (nQ[0:1]) 2.4 – V IDDQ Quiescent Supply Current VDD = max., TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded – 2 mA IDD Dynamic Supply Current At 100 MHz CIN Input Pin Capacitance Document #: 38-07338 Rev. *D 230 mA 4 pF Page 6 of 12 [+] Feedback CY7B9950 AC Test Loads and Waveforms Figure 2. AC Test Loads VDDQ Output 150Ω 20 pF Output 150Ω For Lock Output 20 pF For All Other Outputs Figure 3. Output Waveforms tORISE tORISE tOFALL tPWH 2.0V tOFALL tPWH 1.7V VTH =1.25V VTH =1.5V tPW L tPWL 0.7V 0.8V 2.5V LVTTL OUTPUT WAVEFORM 3.3V LVTTL OUTPUT WAVEFORM Figure 4. Test Waveforms ≤ 1 ns ≤ 1 ns ≤1 ns ≤1 ns 2.5V 3.0V 1.7V 2.0V VTH =1.25V VTH =1.5V 0.8V 0V 0.7V 0V 2.5V LVTTL INPUT TEST WAVEFORM 3.3V LVTTL INPUT TEST WAVEFORM AC Input Specifications Parameter Description Condition TR,TF Input Rise/Fall Time 0.8V – 2.0V TPWC Input Clock Pulse HIGH or LOW TDCIN Input Duty Cycle FREF Reference Input Frequency Document #: 38-07338 Rev. *D Min Max Unit – 10 ns/V 2 – ns 10 90 % FS = LOW 6 50 FS = MID 12 100 FS = HIGH 24 200 MHz Page 7 of 12 [+] Feedback CY7B9950 Switching Characteristics Parameter Description Condition Min Typ Max Unit FOR Output Frequency Range 6 – 200 MHz VCOLR VCO Lock Range 200 – 400 MHz VCOLBW VCO Loop Bandwidth 0.25 – 3.5 MHz tSKEWPR Matched-Pair Skew[10] Skew between the earliest and the latest output transitions within the same bank. – 50 100 ps tSKEW0 Output-Output Skew[10] Skew between the earliest and the latest output transitions among all outputs at 0tU. – 100 200 ps tSKEW1 Skew between the earliest and the latest output transitions among all outputs for which the same phase delay has been selected. – 100 200 ps tSKEW2 Skew between the nominal output rising edge to the inverted output falling edge. – – 500 ps Skew between non-inverted outputs running at different frequencies. – – 500 ps tSKEW4 Skew between nominal to inverted outputs running at different frequencies. – – 500 ps tSKEW5 Skew between nominal outputs at different power supply levels. – – 650 ps Skew between the outputs of any two devices under identical settings and conditions (VDDQ,VDD,temp, air flow, frequency, etc.). – – 750 ps –250 – +250 ps Fout < 100 MHz, measured at VDD/2 48 49.5/ 50.5 52 % Fout > 100 MHz, measured at VDD/2 45 48/ 52 55 tSKEW3 Output-Output Skew[10] tPART Part-Part Skew tPD0 Ref-FB Propagation Delay[11] tODCV Output Duty Cycle tPWH Output High Time Deviation from 50% Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. – – 1.5 ns tPWL Output Low Time Deviation from 50% Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. – – 2.0 ns tR/tF Output Rise/Fall Time Measured at 0.8V – 2.0V for VDD = 3.3V and 0.7V–1.7V for VDD = 2.5V. 0.15 – 1.5 ns tLOCK PLL lock time[12,13] – – 0.5 ms tCCJ Cycle-Cycle Jitter Divide by one output frequency, FS = L, FB = divide by 1, 2, 4. – 50 100 ps Divide by one output frequency, FS = M/H, FB = divide by 1, 2, 4. – 70 150 ps Note 10. Test load = 20 pF, terminated to VCC/2. All outputs are equally loaded. 11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V – 2.0V. 12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter. Document #: 38-07338 Rev. *D Page 8 of 12 [+] Feedback CY7B9950 AC Timing Definitions Figure 5. Timing Definitions tREF tPW L tPW H REF tPD t0DCV t0DCV FB tCCJ1-12 Q tSKEW PR tSKEW 0,1 tSKEW PR tSKEW 0,1 OTHER Q tSKEW 1 tSKEW 1 INVERTED Q tSKEW3 tSKEW 3 tSKEW3 REF DIVIDED BY 2 tSKEW1,3,4 tSKEW 1,3,4 REF DIVIDED BY 4 Document #: 38-07338 Rev. *D Page 9 of 12 [+] Feedback CY7B9950 Ordering Information Part Number Package Type Product Flow Status CY7B9950AC 32 TQFP Commercial, 0° to 70°C Not for new design CY7B9950ACT 32 TQFP – Tape and Reel Commercial, 0° to 70°C Not for new design CY7B9950AI 32 TQFP Industrial, –40° to 85°C Not for new design CY7B9950AIT 32 TQFP – Tape and Reel Industrial, –40° to 85°C Not for new design CY7B9950AXC 32 TQFP Commercial, 0° to 70°C Active CY7B9950V-5AXC 32 TQFP Commercial, 0° to 70°C Active CY7B9950AXCT 32 TQFP – Tape and Reel Commercial, 0° to 70°C Active Pb-free CY7B9950AXI 32 TQFP Industrial, –40° to 85°C Active CY7B9950AXIT 32 TQFP – Tape and Reel Industrial, –40° to 85°C Active Document #: 38-07338 Rev. *D Page 10 of 12 [+] Feedback CY7B9950 Package Drawing and Dimension Figure 6. 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32 51-85063-*B Document #: 38-07338 Rev. *D Page 11 of 12 [+] Feedback CY7B9950 Document History Page Document Title: RoboClock® CY7B9950 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer Document Number: 38-07338 Rev. ECN No. Issue Date Orig. of Change ** 121663 11/25/02 RGL New Data Sheet *A 122548 12/12/02 RGL Removed the PD#/DIV and DS[1:0] pins in VIHH,VIMM and VILL for both 2.5V and 3.3V DC Electrical Specs tables *B 124646 03/05/03 RGL Corrected the description of Pin 27(TEST) in the Pin Description table Corrected the description of Pin 12 (VDDQ) in the Pin Description table Corrected the Min and Max values of VDD from 2.25/2.75 to 2.375/2.625 Volts in the Absolute Maximum Conditions table *C 433662 See ECN RGL Added Lead-free devices Added Jitter typical values *D 1562063 See ECN Description of Change PYG/AESA Added Lead-free CY7B9940V-5AXC to Ordering Information Added Status column to Ordering Information table © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07338 Rev. *D Revised September 27, 2007 Page 12 of 12 RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback