B9940L 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 150-ps max. output-to-output skew Dual- or single-supply operation: — 3.3V core and 3.3V outputs The B9940L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL- or an LVCMOS/LVTTL-compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V compatible and can drive two series-terminated 50Ω transmission lines. With this capability the B9940L has an effective fan-out of 1:36. Low output-to-output skews make the B9940L an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin-compatible with MPC940L • Industrial temperature range: -40°C to 85°C • 32-pin LQFP package Block Diagram Cypress Semiconductor Corporation Document #: 38-07105 Rev. *C • 3901 North First Street • Q0 Q1 Q2 VDDC Q3 Q4 Q5 VSS 31 30 29 28 27 26 25 12 13 14 15 16 Q14 Q13 Q12 VDDC B9940L VSS TCLK_SEL Q0-Q17 11 18 24 23 22 21 20 19 18 17 Q15 1 1 2 3 4 5 6 7 8 9 TCLK VSS VSS TCLK T C LK _S E L P E C L _C L K P E C L_ C LK # VDD VDDC 10 0 VDDC Q16 VDD PECL_CLK PECL_CLK# 32 Pin Configuration Q17 • • • • • • Description Q6 Q7 Q8 VDD Q9 Q 10 Q 11 VSS San Jose, CA 95134 • 408-943-2600 Revised December 26, 2002 B9940L Pin Description[1] Pin Name PWR I/O Description 5 PECL_CLK I, PU PECL Input Clock 6 PECL_CLK# I, PD PECL Input Clock 3 TCLK 9, 10, 11, 13, Q(17:0) 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 I, PD External Reference/Test Clock Input VDDC TCLK_SEL O Clock Outputs I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 8, 16, 29 VDDC 3.3V or 2.5V Power Supply for Output Clock Buffers 7, 21 VDD 3.3V or 2.5V Power Supply 1, 2, 12, 17, 25 VSS Common Ground Note: 1. PD = internal pull-down, PU = internal pull-up. Document #: 38-07105 Rev. *C Page 2 of 5 B9940L Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................–65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection ............................................... 2 kV VSS < (Vin or Vout) < VDD. Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Current: ............................................±20 mA DC Parameters VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage All other inputs VSS – 0.8 V VIH Input High Voltage All other inputs 2.0 – VDD V IIL Input Low Current[3] – – –200 µA IIH Input High Current[3] – – 200 µA VPP Peak-to-Peak Input Voltage PECL_CLK 500 – 1000 mV VDD = 3.3V VDD – 1.4 – VDD – 0.6 V Range[4] VCMR Common Mode PECL_CLK VDD = 2.5V VDD – 1.0 – VDD – 0.6 V VOL Output Low Voltage[5] IOL = 20 mA – – 0.5 V VOH Output High Voltage[5] IOH = –20 mA, VDDC = 3.3V 2.4 – – V IOH = –20 mA, VDDC = 2.5V 1.8 – – V IDDQ Quiescent Supply Current Zout Output Impedance Cin – 2 5 mA VDD = 3.3V 9 14 19 Ω VDD = 2.5V 11 18 26 – 4 – pF Input Capacitance AC Parameters VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter Fmax tPD tPD Description Conditions Min. Typ. Max. Units – – 200 MHz VDD = 3.3V 2.0 3.5 4.0 ns VDD = 2.5V 2.6 4.0 5.2 VDD = 3.3V 1.8 3.3 3.8 VDD = 2.5V 2.3 3.8 4.4 Maximum Input Frequency PECL_CLK to Q Delay [7, 9] TTL_CLK to Q Delay[7, 9] [6] ns FoutDC Output Duty Cycle[7, 8, 9] Measured at VDD/2 45 – 55 % Tskew Output-to-Output Skew[7, 9] VDD = 3.3V, Fin = 150 MHz – – 150 ps VDD = 2.5V, Fin = 150 MHz – – 200 Tskew(pp) Part-to-Part Skew[10] PECL, VDDC = 3.3V – – 1.4 ns – – 2.2 PECL, VDDC = 2.5V Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power suppl sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. Outputs loaded with 30 pF each. 10. Across temperature and voltage ranges, includes output skew. Document #: 38-07105 Rev. *C Page 3 of 5 B9940L AC Parameters VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C (continued)[6] Parameter Tskew(pp) Tskew(pp) tR/tF Description Part-to-Part Conditions Skew[10] Min. Typ. Max. Units ns TCLK, VDDC = 3.3V – – 1.2 TCLK, VDDC = 2.5V – – 1.7 PECL_CLK – – 850 TCLK – – 750 Output Clocks Rise/Fall Time[7, 9] 0.7V to 2.0V, VDDC = 3.3V 0.3 – 1.1 0.5V to 1.8V, VDDC = 2.5V 0.3 – 1.2 Part to Part Skew[11] ps ns Ordering Information Part Number Package Type Production Flow IMIB9940LBL 32-pin LQFP Industrial, –40°C to +85°C IMIB9940LBLT 32-pin LQFP–Tape and Reel Industrial, –40°C to +85°C Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Note: 11. For a specific temperature and voltage, includes output skew. Document #: 38-07105 Rev. *C Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. B9940L Document History Page Document Title: B9940L 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07105 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107509 06/14/01 NDP Convert from IMI to Cypress *A 116093 09/09/02 HWT Converted from Word Doc to Framemaker Corrected the Ordering Information to match the DevMaster Corrected Output Impedance Type to 9/11,14/18, and 19/26 in DC parameters *B 120824 11/21/02 RGL Corrected minor typo *C 122783 12/26/02 RBI Add power up requirements to maximum ratings information Document #: 38-07105 Rev. *C Page 5 of 5