CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Burst Capability—linear or interleaved burst order • Low standby power • Can support up to 133-MHz bus operations with zero wait states Functional Description[1] • Data is transferred on every clock The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 8.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Offered in JEDEC-standard lead-free 100 TQFP, and 165-ball fBGA packages for CY7C1471V33 and CY7C1473V33. 209-ball fBGA package for CY7C1475V33. • Three chip enables for simple depth expansion. • Automatic Power-down feature available using ZZ mode or CE deselect. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.5 ns Maximum Operating Current 335 305 mA Maximum CMOS Standby Current 150 150 mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05288 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 5, 2004 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY 1 Logic Block Diagram – CY7C1473V33 (4M x 18) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BWA WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWB MEMORY ARRAY S E N S E A M P S WE D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPA DQPB E INPUT E REGISTER OE CE1 CE2 CE3 ZZ READ LOGIC SLEEP CONTROL Logic Block Diagram – CY7C1471V33 (2M x 36) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BWA BWB BWC WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWD WRITE DRIVERS MEMORY ARRAY S E N S E A M P S WE OE CE1 CE2 CE3 ZZ Document #: 38-05288 Rev. *E D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPA DQPB DQPC DQPD E INPUT E REGISTER READ LOGIC SLEEP CONTROL Page 2 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Logic Block Diagram – CY7C1475V33 (1M x 72) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G E O U T P U T B U F F E R S E DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh WE INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ Document #: 38-05288 Rev. *E INPUT REGISTER 0 E READ LOGIC Sleep Control Page 3 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Pin Configurations Document #: 38-05288 Rev. *E A 40 41 42 43 44 45 46 47 48 49 50 VDD A A A A A A A A A 37 A0 VSS 36 A1 39 35 A NC / 144M 34 A 38 33 A NC / 288M 32 A 81 A 82 A 83 A 84 ADV/LD 85 OE 86 CEN VSS 90 WE VDD 91 88 CE3 92 CLK BWA 93 89 BWC BWB BWD 96 94 CE2 97 95 CE1 A 98 87 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1471V33 31 BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE BYTE C DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 99 100 A 100-lead TQFP DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A Page 4 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Pin Configurations (continued) Document #: 38-05288 Rev. *E A 40 41 42 43 44 45 46 47 48 49 50 VDD A A A A A A A A A 37 A0 VSS 36 A1 39 35 A NC / 144M 34 A 38 33 A NC / 288M 32 A 81 A 82 A 83 A 84 ADV/LD 85 OE 86 90 CEN VSS 91 WE VDD 92 88 CE3 93 CLK BWA 94 89 NC BWB 95 NC CE2 97 96 CE1 A 98 87 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1473V33 31 BYTE B VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE NC NC NC 99 100 A 100-lead TQFP A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ BYTE A DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Page 5 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Pin Configurations (continued) 165-ball fBGA (3 Chip Enable with JTAG) CY7C1471V33 (2M x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC / 288M A CE1 BWC BWB CE3 CEN ADV/LD A A NC R NC A CE2 BWD BWA CLK WE OE A A NC / 144M DQPC DQC NC DQC VDDQ VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VSS VDD VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB DQB DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC A A A TDI NC A1 VSS NC TDO A A A NC MODE A A A TMS A0 TCK A A A A CY7C1473V33 (4M x 18) 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC / 288M 1 A CE1 BWB NC CE3 CEN ADV/LD A A A NC A CE2 NC BWA CLK WE OE A A NC / 144M NC NC NC DQB VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VDDQ NC NC DQPA DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC NC DQB DQB NC NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC A A A R MODE A A A Document #: 38-05288 Rev. *E VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC TDI NC A1 TDO A A A NC TMS A0 TCK A A A A Page 6 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Pin Configurations (continued) 209-ball PBGA CY7C1475V33 (1M × 72) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 A ADV/LD A CE3 A DQb DQb B DQg DQg BWSc BWSg NC WE A BWSb BWSf DQb DQb C DQg DQg BWSh BWSd NC CE1 NC BWSe BWSa DQb DQb D DQg DQg VSS NC NC OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSSQ DQf DQf VDDQ DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ K NC NC CLK NC VSS CEN VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa NC VDD VDDQ VDDQ DQa DQa N DQh DQh VDDQ VDDQ VDD P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe R DQPd DQPh VDDQ T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe A A A A NC DQe DQe U DQd DQd NC A V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe Document #: 38-05288 Rev. *E Page 7 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Pin Definitions Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH InputSynchronous Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK InputClock CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ InputAsynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. DQs I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OSynchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. MODE Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD Power Supply Power supply inputs to the core of the device. VDDQ VSS Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. I/O Power Supply Power supply for the I/O circuitry. Ground Ground for the device. TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. Document #: 38-05288 Rev. *E Page 8 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Pin Definitions (continued) Name TMS I/O Description JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG -Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC - No Connects. Not internally connected to the die. 144M and 288M are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are synchronous flow-through burst SRAMs designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BWX can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. Burst Read Accesses supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The Write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for Byte Write operations, see Truth Table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWX signals. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 provides Byte Write capability that is described in the Truth Table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1471V33, CY7C1473V33 and CY7C1475V33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have an on-chip burst counter that allows the user the ability to Document #: 38-05288 Rev. *E Page 9 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Burst Write Accesses The CY7C1471V33, CY7C1473V33, and CY7C1475V33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description IDDZZ Sleep mode standby current Test Conditions Min. ZZ > VDD – 0.2V tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled Max. Unit 150 mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Truth Table [2, 3, 4, 5, 6, 7, 8] Operation Deselect Cycle Address Used CE1 CE2 CE3 ZZ None H X X L Deselect Cycle None X Deselect Cycle None Continue Deselect Cycle None Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) ADV/LD WE BWX OE CEN CLK DQ L X X X L L->H Tri-State L X X X L L->H Tri-State X H L X L X L L X X X L L->H Tri-State X X X L H X X X L L->H Tri-State External L H L L L H X L L L->H Data Out (Q) Next X X X L H X X L L L->H Data Out (Q) External L H L L L H X H L L->H Tri-State Next X X X L H X X H L L->H Tri-State External L H L L L L L X L L->H Data In (D) Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Truth Table for details. 3. Write is defined by BWX, and WE. See Truth Table for Read/Write. 4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes. 5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. Document #: 38-05288 Rev. *E Page 10 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Truth Table (continued)[2, 3, 4, 5, 6, 7, 8] Address Used CE1 CE2 CE3 ZZ Write Cycle (Continue Burst) Next X X X L Operation NOP/Write Abort (Begin Burst) None Write Abort (Continue Burst) Ignore Clock Edge (Stall) L H L ADV/LD WE BWX OE CEN CLK DQ H X L X L L->H Data In (D) L L L H X L L->H Tri-State Next X X X L H X H X L L->H Tri-State Current X X X L X X X X H L->H - None X X X H X X X X X X Tri-State Sleep Mode Truth Table for Read/Write[2, 3, 9] Function (CY7C1471V33) WE BWA BWB BWC BWD Read H X X X X Write No bytes written L H H H H Write Byte A – (DQA and DQPA) L L H H H Write Byte B – (DQB and DQPB) Write Byte C – (DQC and DQPC) L H L H H L H H L H Write Byte D – (DQD and DQPD) L H H H L Write All Bytes L L L L L Truth Table for Read/Write[2, 3, 9] Function (CY7C1473V33) Read WE BWB BWA H X X Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Truth Table for Read/Write[2, 3, 9] Function (CY7C1475V33) WE BWx Read H X Write – No Bytes Written L H Write Byte X − (DQx and DQPx) L L Write All Bytes L All BW = L Note: 9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05288 Rev. *E Page 11 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Disabling the JTAG Feature Test Data-Out (TDO) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram 0 TAP Controller State Diagram 1 Bypass Register TEST-LOGIC RESET 2 1 0 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 Selection Circuitry TDO Identification Register CAPTURE-IR x . . . . . 2 1 0 Boundary Scan Register SHIFT-IR 1 Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 0 1 EXIT1-DR 1 EXIT1-IR 0 1 TCK 0 PAUSE-DR 0 TMS PAUSE-IR 1 TAP CONTROLLER 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 TDI 0 1 0 0 1 Selection Circuitry 0 UPDATE-IR 1 0 Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Document #: 38-05288 Rev. *E TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Page 12 of 29 PRELIMINARY Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register CY7C1471V33 CY7C1473V33 CY7C1475V33 Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Document #: 38-05288 Rev. *E The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still Page 13 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY BYPASS possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min. Max Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 25 ns tTL TCK Clock LOW time 25 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 5 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes: 10.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11.Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05288 Rev. *E Page 14 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Test Conditions Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Max. Unit IOH = –4.0 mA, VDDQ = 3.3V 2.4 V IOH = –1.0 mA, VDDQ = 2.5V 2.0 V IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V IOL = 100 µA Input HIGH Voltage Input LOW Voltage Input Load Current Min. VDDQ = 3.3V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Instruction Field CY7C1471V33 CY7C1473V33 CY7C1475V33 (2Mx36) (4Mx18) (1Mx72) Description Revision Number (31:29) 000 000 000 Device Depth (28:24)[13] 01011 01011 01011 Architecture/Memory Type(23:18) 001001 001001 001001 Defines memory type and architecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density 00000110100 00000110100 00000110100 1 1 1 Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Describes the version number Reserved for internal use Allows unique identification of SRAM vendor Indicates the presence of an ID register Notes: 12. All voltages referenced to VSS (GND). 13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05288 Rev. *E Page 15 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order–165FBGA 71 52 - Boundary Scan Order– 209BGA - - 110 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05288 Rev. *E Page 16 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Boundary Scan Exit Order (x36) (continued) Boundary Scan Exit Order (x36) 165-Ball ID Bit # 165-Ball ID 1 C1 38 M11 2 D1 39 L11 3 E1 40 M10 4 D2 41 L10 5 E2 42 K11 6 F1 43 J11 7 G1 44 K10 8 F2 45 J10 9 G2 46 H11 10 J1 47 G11 11 K1 48 F11 12 L1 49 E11 13 J2 50 D10 14 M1 51 D11 15 N1 52 C11 16 K2 53 G10 17 L2 54 F10 18 M2 55 E10 19 R1 56 A10 20 R2 57 B10 21 R3 58 A9 22 P2 59 B9 23 R4 60 A8 24 P6 61 B8 25 R6 62 A7 26 N6 63 B7 27 P11 64 B6 28 R8 65 A6 29 P3 66 B5 30 P4 67 A5 31 P8 68 A4 32 P9 69 B4 33 P10 70 B3 34 R9 71 A3 35 R10 72 A2 36 R11 73 B2 37 N11 Bit # Document #: 38-05288 Rev. *E Page 17 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Boundary Scan Exit Order (x18) (continued) Boundary Scan Exit Order (x18) 165-Ball ID Bit # 165-Ball ID 1 D2 45 A7 2 E2 46 B7 3 F2 47 B6 4 G2 48 A6 5 J1 49 B5 6 K1 50 A4 7 L1 51 B3 8 M1 52 A3 9 N1 53 A2 10 R1 54 B2 Bit # 11 R2 12 R3 13 P2 14 R4 15 P6 16 R6 17 N6 18 P11 19 R8 20 P3 21 P4 22 P8 23 P9 24 P10 25 R9 26 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 37 C11 38 A11 39 A10 40 B10 41 A9 42 B9 43 A8 44 B8 Document #: 38-05288 Rev. *E Boundary Scan Exit Order (x72) Bit # 209-Ball ID 1 A1 2 A2 3 B1 4 B2 5 C1 6 C2 7 D1 8 D2 9 E1 10 E2 11 F1 12 F2 13 G1 14 G2 15 H1 16 H2 17 J1 18 J2 19 L1 20 L2 21 M1 22 M2 23 N1 24 N2 25 P1 26 P2 27 R2 28 R1 29 T1 30 T2 31 U1 Page 18 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Boundary Scan Exit Order (x72) (continued) Boundary Scan Exit Order (x72) (continued) Bit # 209-Ball ID Bit # 209-Ball ID 32 U2 76 H10 33 V1 77 G11 34 V2 78 G10 35 W1 79 F11 36 W2 80 F10 37 T6 81 E10 38 V3 82 E11 39 V4 83 D11 40 U4 84 D10 41 W5 85 C11 42 V6 86 C10 43 W6 87 B11 44 U3 88 B10 45 U9 89 A11 46 V5 90 A10 47 U5 91 A9 48 U6 92 U8 49 W7 93 A7 50 V7 94 A5 51 U7 95 A6 52 V8 96 D6 53 V9 97 B6 54 W11 98 D7 55 W10 99 K3 56 V11 100 A8 57 V10 101 B4 58 U11 102 B3 59 U10 103 C3 60 T11 104 C4 61 T10 105 C8 62 R11 106 C9 63 R10 107 B9 64 P11 108 B8 65 P10 109 A4 66 N11 110 C6 67 N10 111 B7 68 M11 112 A3 69 M10 70 L11 71 L10 72 P6 73 J11 74 J10 75 H11 Document #: 38-05288 Rev. *E Page 19 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Range Commercial DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V Ambient Temperature VDD VDDQ 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range[14, 15] Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[14] Voltage[14] Input Load Current except ZZ and MODE Test Conditions Min. Max. Unit 3.135 3.6 V VDDQ = 3.3V 3.135 VDD V VDDQ = 2.5V 2.375 2.625 V VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V VDDQ = 3.3V 2.0 VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND ≤ VI ≤ VDDQ Input = VDD Input Current of ZZ µA –5 Input Current of MODE Input = VSS 30 Input = VSS µA –30 Input = VDD µA 5 µA IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz 305 mA ISB1 Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 200 mA 10-ns cycle, 100 MHz 200 mA All speeds 150 mA 200 mA 200 mA 165 mA –5 ISB2 Automatic CE VDD = Max, Device Deselected, Power-down VIN ≤ 0.3V or VIN > VDD – 0.3V, Current—CMOS Inputs f = 0, inputs static ISB3 VDD = Max, Device Deselected, or 7.5-ns cycle, 133 MHz Automatic CE Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V 10-ns cycle, 100 MHz Current—CMOS Inputs f = fMAX, inputs switching VDD = Max, Device Deselected, All Speeds Automatic CE Power-down VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, Current—TTL Inputs f = 0, inputs static ISB4 5 µA 335 mA Notes: 14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 15. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05288 Rev. *E Page 20 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Thermal Resistance[16] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions 165 fBGA Typ. 209 BGA Typ. TQFP Typ. Unit 16.3 15.2 24.63 °C/W 2.1 1.7 2.28 °C/W TQFP Max. 209-BGA Max. 6 6 6 pF 5 5 5 pF Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Capacitance[16] Parameter Description Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 165-fBGA Max. Unit CADDRESS Address Input Capacitance CDATA Data Input Capacitance CCTRL Control Input Capacitance 8 8 8 pF CCLK Clock Input Capacitance 6 6 6 pF CI/O Input/Output Capacitance 5 5 5 pF AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 10% 90% 10% 90% GND 5 pF R = 351Ω ≤ 1 ns ≤ 1 ns VL = 1.5V INCLUDING JIG AND SCOPE (a) (c) (b) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT Z0 = 50Ω 10% R = 1538Ω VL = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω (b) ≤ 1 ns ≤ 1 ns (c) Note: 16. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05288 Rev. *E Page 21 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Switching Characteristics Over the Operating Range[21, 22] 133 MHz Parameter Description tPOWER‘ Min. Max. 1 100 MHz Min. Max. Unit 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 2.5 3.0 ns tCL Clock LOW 2.5 3.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.5 2.5 ns tCLZ Clock to Low-Z[18, 19, 20] 3.0 3.0 ns tCHZ Clock to High-Z[18, 19, 20] tOEV OE LOW to Output Valid tOELZ OE LOW to Output Low-Z[18, 19, 20] tOEHZ OE HIGH to Output 6.5 8.5 3.8 3.0 0 High-Z[18, 19, 20] 4.5 ns 3.8 ns 0 3.0 ns ns 4.0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.5 1.5 ns tALS ADV/LD Set-up Before CLK Rise 1.5 1.5 ns tWES WE, BWX Set-up Before CLK Rise 1.5 1.5 ns tCENS CEN Set-up Before CLK Rise 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.5 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tALH ADV/LD Hold After CLK Rise 0.5 0.5 ns tWEH WE, BWX Hold After CLK Rise 0.5 0.5 ns tCENH CEN Hold After CLK Rise 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns Hold Times Notes: 17. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a Read or Write operation can be initiated. 18. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 19. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 20. This parameter is sampled and not 100% tested. 21. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 22. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05288 Rev. *E Page 22 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Switching Waveforms Read/Write Waveforms[23, 24, 25] 1 2 3 tCYC 4 5 6 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCES tCEH tCH tCL CEN CE ADV/LD WE BWX A1 ADDRESS tAS A2 A4 A3 tCDV tAH tDOH tCLZ DQ D(A1) tDS D(A2) Q(A3) D(A2+1) tOEV Q(A4+1) Q(A4) tOELZ WRITE D(A1) WRITE D(A2) D(A5) Q(A6) D(A7) WRITE D(A7) DESELECT tOEHZ tDH OE COMMAND tCHZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) tDOH WRITE D(A5) READ Q(A6) UNDEFINED Notes: 23. For this waveform ZZ is tied LOW. 24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05288 Rev. *E Page 23 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Switching Waveforms (continued) NOP, STALL and DESELECT Cycles[23, 24, 26] 1 2 3 tCYC 4 5 6 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWX A1 ADDRESS tAS A2 A4 A3 tCDV tAH tDOH tCLZ DQ D(A1) tDS D(A2) Q(A3) D(A2+1) tOEV Q(A4+1) Q(A4) tOELZ WRITE D(A1) WRITE D(A2) D(A5) Q(A6) D(A7) WRITE D(A7) DESELECT tOEHZ tDH OE COMMAND tCHZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) tDOH WRITE D(A5) READ Q(A6) UNDEFINED Note: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A Write is not performed during this cycle. Document #: 38-05288 Rev. *E Page 24 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing[27, 28] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 Ordering Code CY7C1471V33-133AXC Package Name Part and Package Type A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) CY7C1475V33-133BGC BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm) CY7C1471V33-133BZXC BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm) A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) CY7C1475V33-100BGC BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm) CY7C1471V33-100BZXC BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm) CY7C1473V33-133AXC CY7C1471V33-133BZC Operating Range Commercial CY7C1473V33-133BZC CY7C1473V33-133BZXC CY7C1475V33-133BGXC 100 CY7C1471V33-100AXC CY7C1473V33-100AXC CY7C1471V33-100BZC CY7C1473V33-100BZC CY7C1473V33-100BZXC CY7C1475V33-100BGXC Please contact your local Cypress sales representative for availability of these parts. Lead-free BG packages (Ordering Code: BGX) will be available in 2005. Notes: 27. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device. 28. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05288 Rev. *E Page 25 of 29 PRELIMINARY CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Document #: 38-05288 Rev. *E Page 26 of 29 CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Package Diagrams (continued) 165-Ball FBGA (15 x 17 x 1.40 mm) BB165C PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE 1.40 MAX. 0.36 C 51-85165-*A Document #: 38-05288 Rev. *E Page 27 of 29 PRELIMINARY CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) BB209A 51-85167-** NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05288 Rev. *E Page 28 of 29 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY Document History Page Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document #: 38-05288 Rev. *E REV. ECN NO. Issue Date Orig. of Change Description of Change ** 114675 08/06/02 PKS New Data Sheet *A 121521 02/07/03 CJM Updated features for package offering Updated ordering information Changed Advanced Information to Preliminary *B 223721 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Removed 150-MHz speed grade offering Included ISB and IDD values Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering *C 235012 See ECN RYQ Minor Change: The data sheets do not match on the spec system and external web. *D 243572 See ECN NJY Changed ball H2 from VDD to NC in the 165-ball FBGA package in page 6 Modified capacitance values on page 21 *E 299511 See ECN SYT Removed 117-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 21 Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Document #: 38-05288 Rev. *E Page 29 of 29