CY2285 100-MHz Pentium®II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs Features • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium® II, and other similar processor-based motherboards — Two CPU clocks at 2.5V up to 100 MHz — Six synchronous PCI clocks, one free-running — Two 3.3V Reference clocks at 14.318 MHz The CY2285 possesses power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2285-2 features an early PCI clock which leads the other PCI clocks by 1–4 ns. The CY2285-2 also features a DIV4 pin which allows for dynamic shifting of CPU and PCI clocks from the default frequency to the default/4. — One 3.3V USB clock running at 48 MHz — One 3.3V USB/IO clock running at 48 MHz/24 MHz Spread Spectrum clocking for EMI control 1.5–4.0 ns delay between CPU and PCI clocks Power-down, CPU stop and PCI stop pins Low skew outputs, ≤ 175 ps between CPU clocks Early PCI clock leads PCI by 1–4 ns (-2 option) DIV4 allows dynamic shifting of CPU and PCI clocks from the default frequency to default/4 (-2 option) • Factory-EPROM programmable output drive and slew rate for EMI customization • Available in space-saving 28-pin SSOP package • • • • • • CY2285 Selector Guide Clock Outputs CY2285-1 CY2285-2 CY2285-3 2 2 2 6[1] 7[1, 2] 6[1] Ref. (14.318 MHz) 2 2 1 USB (48 MHz) 1 1 1 USB/IO (48 MHz/24 MHz selectable) 1 N/A 1 CPU-PCI delay 1.5–4.0 ns 1.5–4.0 ns 1.5–4.0 ns EPCI-PCI delay N/A 1.0–4.0 ns N/A CPU (66, 100 MHz) PCI (CPU/2, CPU/3 MHz) Functional Description The CY2285 is a clock synthesizer/driver for Pentium II, or other similar processor-based mobile PCs requiring up to 100-MHz support. The CY2285 outputs two CPU clocks at 2.5V. There are six PCI clocks, running at one-half or one-third the CPU clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. Additionally, the part outputs two 3.3V reference clocks at 14.318 MHz. The CY2285 provides incorporates the Intel®-defined spread spectrum features. It provides a –0.6% downspread on the CPU and PCI clocks, which can help reduce EMI in certain high-speed systems. Spread Spectrum Notes: 1. One free-running PCI clock. 2. One early PCI clock. SPREAD (-2,-3 option) REF0/SPREAD REF0 (-2 option) Logic Block Diagram DIV4 XTALIN XTALOUT –0.6% –0.6% –0.6% Downspread Downspread Downspread REF1/SEL48 REF1 (-2,-3 option) VDDREF 14.318 MHz OSC. CPU PLL PWR_DWN STOP LOGIC /4 CPUCLK [0–1] Divider VDDCPU Delay VDDPCI EPCICLK (-2 option) EPROM STOP LOGIC PCICLK [1-5] VDDPCI PCICLK_F CPU_STOP PCI_STOP VDDPCI USBCLK SYS PLL VDD48 USB_IOCLK/TS (-1 option) USBCLK/SEL100/66 (-2 option) VDD48 Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 18, 2000 CY2285 Pin Configurations SSOP Top View 28 VDDREF 2 3 27 26 REF1/SEL48 4 25 24 XTAL_OUT PCICLK_F PCICLK1 5 PCICLK2 6 VSSPCI VDDPCI 7 PCICLK3 PCICLK4 PCICLK5 VDD48 USBCLK USB_IOCLK/TS 8 9 10 11 12 REF0 1 28 VDDREF XTAL_IN 2 3 27 26 REF1 SPREAD 4 25 24 VDDCPU CPUCLK0 PCICLK1 5 23 CPUCLK1 PCICLK2 6 22 VSSCPU 7 21 VSSCORE VSSPCI VDDPCI 20 PCI_STOP PCICLK3 19 18 VDDCORE PCICLK4 PCICLK5 VDD48 XTAL_OUT PCICLK_F REF0/SPREAD VDDCPU CPUCLK0 PCICLK1 5 23 CPUCLK1 PCICLK2 6 22 VSSCPU 7 21 VSSCORE VSSPCI VDDPCI 8 20 PCI_STOP PCICLK3 19 18 VDDCORE PCICLK4 PCICLK5 EPCICLK 9 10 11 12 VDD48 13 USBCLK/SEL100/66 14 13 17 16 CPU_STOP PWRDWN SEL100 14 15 VSS48 CY2285-2 1 CY2285-1 VSSREF XTAL_IN SSOP Top View 17 16 15 CPU_STOP PWRDWN DIV4 VSS48 VSSREF 1 28 VDDREF XTAL_IN 2 3 27 26 REF1/SEL48 4 25 24 XTAL_OUT PCICLK_F USBCLK USB_IOCLK/TS 8 CY2285-3 SSOP Top View 9 10 11 12 13 14 SPREAD VDDCPU CPUCLK0 23 CPUCLK1 22 VSSCPU 21 VSSCORE 20 PCI_STOP 19 18 VDDCORE 17 16 15 CPU_STOP PWRDWN SEL100 VSS48 Pin Summary: CY2285-1, CY2285-3 Name Pins Description VDD 8, 12, 19, 28 3.3V Power supply voltage VDDCPU 25 2.5V Power supply for CPU clocks VSS 1, 7, 15, 21, 22 Ground XTALIN[3] 2 Reference crystal input XTALOUT 3 Reference crystal feedback PCI_STOP 20 Active LOW control input to stop PCI clocks CPU_STOP 18 Active LOW control input to stop CPU clocks PWR_DWN 17 Active LOW control input to power down device SEL100 16 Select for enabling 100-MHz or 66-MHz CPU clock HIGH = 100 MHz, LOW = 66 MHz CPUCLK[0:1] 23, 24 2.5V CPU clock outputs PCICLK[1:5] 5, 6, 9, 10, 11 3.3V PCI clock outputs PCICLK_F 4 3.3V Free-running PCI clock output REF0/SPREAD 26 (-1 option) 3.3V 14.318-MHz reference clock output and power-on spread spectrum enable strap option. Strap LOW = Spread Spectrum enable Strap HIGH = Spread Spectrum disable SPREAD 26 (-3 option) Active LOW control input to enable spread spectrum REF1/SEL48 27 3.3V 14.318-MHz reference clock output and power-on 48-/24-MHz select strap option. Strap LOW = 48 MHz on pin14 Strap HIGH = 24 MHz on pin14 USBCLK 13 3.3V 48-MHz USB clock output USB_IOCLK/TS 14 3.3V 48-MHz or 24-MHz output and three-state strapping option. Strap LOW = Enter three-state mode for testing Strap HIGH = Normal Operation [3] Note: 3. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. 2 CY2285 Pin Summary: CY2285-2 Name Pins Description VDD 8, 13, 19, 28 3.3V Power supply VDDCPU 25 2.5V Power supply VSS 7, 15, 21, 22 Ground XTALIN 2 Reference crystal input XTALOUT[3] 3 Reference crystal feedback PCI_STOP 20 Active LOW control input to stop PCI clocks CPU_STOP 18 Active LOW control input to stop CPU clocks PWR_DWN 17 Active LOW control input to power down device DIV4 16 Active LOW control input to enable divide-by-four option on CPU and PCI clocks CPUCLK[0:1] 23, 24 2.5V CPU clock outputs PCICLK[1:5] 5, 6, 9, 10, 11 3.3V PCI clock outputs PCICLK_F 4 3.3V Free-running PCI clock output [3] EPCICLK 12 3.3V Early PCI clock output (Not Free-running) REF0 1 3.3V 14.318-MHz reference clock output REF1 27 3.3V 14.318-MHz reference clock output USBCLK/SEL100/66 14 3.3V 48-MHz USB clock output or select input and frequency select strap option (use 10-kΩ external strap resistor) Strap LOW = 66.6-MHz CPU Frequency Strap HIGH = 100-MHz CPU Frequency SPREAD 26 Active LOW control input to enable Spread Spectrum Actual Clock Frequency Values Clock Output Target Frequency Actual Frequency (MHz) (MHz) PPM CPUCLK 66.67 66.654 –240 CPUCLK 100 99.77 –2300 USB 48-MHz 48 48.008 +167 Power Management Logic PWR_DWN CPUCLK PCICLK PCI_STOP X X 0 Low Low Low Low Off 0 0 1 Low Low Running Running Running Running 0 1 1 Low Running Running Running Running Running 1 0 1 Running Low Running Running Running Running 1 1 1 Running Running Running Running Running Running 3 PCICLK_F Other Clocks CPU_STOP Osc. PLLs Off CY2285 Function Table: CY2285-1 SEL100 SEL48[4] TS[4] SPREAD[4] CPUCLK[0:1] PCICLK[1:5], PCICLK_F USB_IOCLK USBCLK REFCLK [0-1] X X 0 X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 1 1 1 (no spread) 66.6 MHz 33.3 MHz 24 MHz 48 MHz 14.318 MHz 0 0 1 0 (–0.6% downspread) 66.6 MHz 33.3 MHz 48 MHz 48 MHz 14.318 MHz 1 1 1 1 (no spread) 100 MHz 33.3 MHz 24 MHz 48 MHz 14.318 MHz 1 0 1 0 (–0.6% downspread) 100 MHz 33.3 MHz 48 MHz 48 MHz 14.318 MHz Function Table: CY2285-2 SEL100/66[4] SPREAD DIV4 CPUCLK [0:1] PCICLK[1:5], PCICLK_F, EPCICLK USBCLK REFCLK[0:1] 0 0 (–0.6% downspread) 1 66.67 MHz 33.3 MHz 48 MHz 14.318 MHz 0 1 (no spread) 1 66.67 MHz 33.3 MHz 48 MHz 14.318 MHz 1 0 (–0.6% downspread) 1 100 MHz 33.3 MHz 48 MHz 14.318 MHz 1 1 (no spread) 1 100 MHz 33.3 MHz 48 MHz 14.318 MHz 0 0 (–0.6% downspread) 0 16.67 MHz 8.33 MHz 48 MHz 14.318 MHz 0 1 (no spread) 0 16.67 MHz 8.33 MHz 48 MHz 14.318 MHz 1 0 (–0.6% downspread) 0 25.0 MHz 8.33 MHz 48 MHz 14.318 MHz 1 1 (no spread) 0 25.0 MHz 8.33 MHz 48 MHz 14.318 MHz Function Table: CY2285-3 SEL100 SEL48[4] TS[4] SPREAD[4] CPUCLK[0:1] PCICLK[1:5], PCICLK_F USB_IOCLK USBCLK REFCLK1 X X 0 X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 1 1 1 (no spread) 66.6 MHz 33.3 MHz 24 MHz 48 MHz 14.318 MHz 0 0 1 0 (–0.6% downspread) 66.6 MHz 33.3 MHz 48 MHz 48 MHz 14.318 MHz 1 1 1 1 (no spread) 100 MHz 33.3 MHz 24 MHz 48 MHz 14.318 MHz 1 0 1 0 (–0.6% downspread) 100 MHz 33.3 MHz 48 MHz 48 MHz 14.318 MHz Note: 4. Power-on strap option. 4 CY2285 Storage Temperature (Non-Condensing) ... –65°C to +150°C Maximum Ratings Max. Soldering Temperature (10 sec) ...................... +260°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ............................................... +150°C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0.5V to VDD+0.5 Operating Conditions[5] Parameter Description Min. Max. Unit VDD Analog and Digital 3.3V Supply Voltage 3.135 3.465 V VDDCPU CPU Supply Voltage 2.375 2.625 V TA Operating Temperature, Ambient 0 70 °C CL Max. Capacitive Load on CPUCLK PCICLK REF f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 35 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter VIH Description High-level Input Voltage Test Conditions Min. Max. Unit Except Crystal Inputs[6] 2.0 [6] VIL Low-level Input Voltage VOH IOH = 12 mA CPUCLK VOL High-level Output Voltage VDDCPU = 2.375V Low-level Output Voltage VDDCPU = 2.375V IOL = 12 mA CPUCLK VOH High-level Output Voltage VDDPCI, AVDD, VDDREF = 3.135V IOH = 14.5 mA PCICLK VOL Low-level Output Voltage Except Crystal Inputs VDDPCI, AVDD, VDDREF = 3.135V V 0.8 IOH = 16 mA REF IOH = 36 mA REF[7] IOL = 9.4 mA PCICLK IOL = 9 mA REF IOL = 29 mA REF[7] 2.0 V V 0.4 2.4 V V 0.4V V –10 +10 µA 10 µA –10 +10 µA IIH Input High Current VIH = V DD IIL Input Low Current VIL = 0V IOZ Output Leakage Current Three-state IDD25 Power Supply Current for 2.5V clocks VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz 70 mA IDD25 Power Supply Current for 2.5V clocks VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz 100 mA IDD33 Power Supply Current for 3.3V clocks VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs 170 mA IDDS Powerdown Current Current draw in powerdown state 500 µA Notes: 5. Electrical parameters are guaranteed with these operating conditions. 6. Crystal Inputs have CMOS thresholds, nominally VDD/2. 7. CY2285-2 option only. 5 CY2285 Switching Characteristics[8] Over the Operating Range Parameter Output Description Test Conditions Min. Typ. 50 Max. Unit t1 All Output Duty Cycle t1 = t1A ÷ t1B 45 55 % t2 CPUCLK CPU Clock Rising and Falling Edge Rate Between 0.4V and 2.0V 1.0 4.0 V/ns t2 PCICLK PCI Clock Rising and Falling Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t2 REF REF Clock Rising and Falling Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t3 CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V 0.4 1.6 ns t4 CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V 0.4 1.6 ns t5 CPUCLK CPU-CPU Clock Skew Measured at 1.25V 175 ps t6 CPUCLK, PCICLK CPU-PCI Clock Skew Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks 4.0 ns t7 PCICLK, PCICLK PCI-PCI Clock Skew Measured at 1.5V 250 ps t7 EPCICLK, PCICLK EPCI-PCI Clock Skew[7] Measured at 1.5V 4.0 ns t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V 700 ps t11 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V 500 ps t12 CPUCLK, PCICLK Power-up Time CPU and PCI clock stabilization from power-up 3 ms t13 CPUCLK, PCICLK /4 Frequency Slew Time[7] Time for CPU, EPCI, and PCI clock frequency to change from f to f/4 after select input change 25 cycles [9] Notes: 8. All parameters specified with loaded outputs. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 6 100 1.5 1.0 10 CY2285 Switching Waveforms Duty Cycle Timing t1A t1B OUTPUT All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t4 t2 t3 CPU-CPU Clock Skew CPUCLK CPUCLK t5 CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI/EPCI-PCI Clock Skew PCI/EPCICLK PCICLK t7 CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) 7 CY2285 Switching Waveforms (continued) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Ordering Information Ordering Code Package Name Operating Range Package Type CY2285PVC-1 O28 28-Pin SSOP Commercial CY2285PVC-2 O28 28-Pin SSOP Commercial CY2285PVC-3 O28 28-Pin SSOP Commercial Document #: 38-00732-C 8 CY2285 Package Diagram 28-Lead (210-Mil) Shrunk Small Outline Package O28 51-85079-B © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.