FastEdge™ Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features Functional Description • Ten ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs (CLKA) • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable • 50 ps output-to-output skew • 150 ps device-to-device skew • 400 ps propagation delay (typical) • 1.2 ps RMS period jitter (max.) • 1.5 GHz Operation (2.7 GHz maximum toggle frequency) • PECL and HSTL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V • Industrial temperature range: –40°C to 85°C • 32-pin TQFP package • Temperature compensation like 100K ECL The CY2DP3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3110 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL single-ended signal to 10 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point. Since the CY2DP3110 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3110 delivers consistent performance over various platforms • Pin-compatible with MC100ES6111 Block Diagram Pin Configuration V BB VCC Q0 Q0# Q1 Q1# Q2 Q2# VCC Q0 Q0# 32 31 30 29 28 27 26 25 Q1 Q1# VCC VCC CLK_SEL CLKA CLKA# VBB CLKB CLKB# VEE Q2 Q2# CLKA CLKA# Q3 Q3# VEE VCC Q4 Q4# CLKB CLKB# Q3 Q3# Q4 Q4# Q5 Q5# Q6 Q6# VCC Q9# Q9 Q8# Q8 Q7# Q7 VCC Q6 Q6# VEE CY2DP3110 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 Q5 Q5# VEE CLK_SEL 1 2 3 4 5 6 7 8 Q7 Q7# VBB Q8 Q8# Q9 Q9# Cypress Semiconductor Corporation Document #: 38-07469 Rev.*G • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 28, 2004 FastEdge™ Series CY2DP3110 Pin Definitions[1, 2, 3] Pin Name I/O 2 CLK_SEL I,PD 3 CLKA I,PD[1] 4 CLKA# Type Description ECL/PECL Input Clock Select. ECL/PECL Differential Input Clocks. I,PD/PU ECL/PECL Differential Input Clocks. 5 VBB O Bias 6 CLKB, I,PD HSTL Reference Voltage Output. Alternate Differential Input Clocks. 7 CLKB# I,PD/PU HSTL Alternate Differential Input Clocks. 8 VEE –PWR Power Negative Power Supply. 1,9,16, 25,32 VCC +PWR Power Positive Power Supply. 31,29,27,24,22,20,18, 15,13,11 Q(0:9) O ECL/PECL ECL/PECL Differential Output Clocks. 30,28,26,23,21,19,17, 14,12,10 Q#(0:9) O ECL/PECL ECL/PECL Differential Output Clocks. Table 1. Control Operation CLK_SEL 0 CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations 1 CLKB, CLKB# input pair is active. CLKB can be driven with HSTL compatible signals with respective power configurations Governing Agencies The following agencies provide specifications that apply to the CY2DP3110. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name Specification JEDEC JESD 020B (MSL) JESD 8-6 (HSTL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) Mil-Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|). Document #: 38-07469 Rev.*G Page 2 of 9 FastEdge™ Series CY2DP3110 Absolute Maximum Ratings Parameter Description Condition Min. Max. Unit VCC Positive Supply Voltage Non-Functional –0.3 4.6 V VEE Negative Supply Voltage Non-Functional -4.6 0.3 V TS Temperature, Storage Non-Functional –65 +150 °C TJ Temperature, Junction Non-Functional 150 °C ESDh ESD Protection Human Body Model MSL Moisture Sensitivity Level Gate Count Total Number of Used Gates 2000 V 3 N.A. 50 gates Assembled Die Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter Description Condition IBB Output Reference Current LUI Latch Up Immunity Functional, typical TA Temperature, Operating Ambient Functional Min. Relative to VBB Max. Unit |200| uA 100 mA –40 +85 ØJc Dissipation, Junction to Case Functional 35[4] ØJa Dissipation, Junction to Ambient Functional 76[4] °C °C/W °C/W 130[5] IEE Maximum Quiescent Supply Current CIN Input pin capacitance 3 pF LIN Pin Inductance 1 nH VIN Input Voltage Relative to VCC[6] VTT Output Termination Voltage Relative to VCC[6] VOUT Output Voltage Relative to VCC[6] IIN Input Current[7] VEE pin –0.3 mA VCC + 0.3 V VCC – 2 –0.3 V VCC + 0.3 V l150l uA Min. Max. Unit 2.375 3.135 2.625 3.465 V V 1.2 VCC V 0.68 0.9 V VCC – 1.25 VCC – 0.7 V VCC – 1.995 VCC –1.995 VCC – 1.5 VCC – 1.3 V V VCC – 1.165 VCC – 0.880 [11] V VCC – 1.625 V VIN = VIL, or VIN = VIH PECL/HSTL DC Electrical Specifications Parameter Description Condition VCC Operating Voltage 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V VCMR PECL Input Differential Cross Point Voltage[8] Differential operation VX HSTL Input Differential Crosspoint Volt- Standard Load Differential age[9] Operation VOH Output High Voltage IOH = –30 mA[10] VOL Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOL = –5 mA[10] VIH Input Voltage, High Single-ended operation VIL Input Voltage, Low Single-ended operation VBB[3] Output Reference Voltage Relative to VCC[6] VCC – 1.945 [11] VCC – 1.620 VCC – 1.220 V Notes: 4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 6. where VCC is 3.3V±5% or 2.5V±5% 7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. Refer to Figure 1 9. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig. 2. 10. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 11. VIL will operate down to VEE; VIH will operate up to VCC Document #: 38-07469 Rev.*G Page 3 of 9 FastEdge™ Series CY2DP3110 ECL DC Electrical Specifications Parameter Description Condition Min. Max. Unit –2.625 –3.465 –2.375 –3.135 V VEE + 1.2 0V V –1.25 –0.7 V –1.995 –1.995 –1.5 –1.3 V VEE Negative Power Supply –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V VCMR ECL Input Differential cross point voltage[8] Differential operation VOH Output High Voltage IOH = –30 mA[10] VOL Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOL = –5 mA[10] VIH Input Voltage, High Single-ended operation –1.165 –0.880 [11] V VIL Input Voltage, Low Single-ended operation –1.945 [11] –1.625 V VBB[3] Output Reference Voltage – 1.620 – 1.220 V Min. Max. Unit 0.1 1.3 V – 1.5 GHz AC Electrical Specifications Parameter Description Condition VPP PECL/ECL Differential Input Voltage[8] Differential operation VCMRO Output Common Voltage Range (typ.) FCLK Input Frequency 50% duty cycle Standard load TPD Propagation Delay CLKA or CLKB to Output pair[13] PECL, ECL = 660 MHz HSTL < 1GHz 280 280 650 750 ps ps VDIF HSTL Differential Input Voltage[12] Duty Cycle Standard Load Differential Operation 0.4 1.9 V Vo Output Voltage (peak-to-peak; see Figure 2) < 1 GHz 0.375 – V tsk(0) Output-to-output Skew 660 MHz [13], See Figure 3 – 50 ps tsk(PP) Part-to-Part Output Skew 660 MHz [13] – 150 ps TPER Output Period Jitter (rms)[14] 660 MHz [13] – 1.2 ps 660 MHz [13], See Figure 3 – 50 ps 0.08 0.3 ns Skew[15] tsk(P) Output Pulse TR,TF Output Rise/Fall Time (see Figure 2) VCC – 1.425 660 MHz 50% duty cycle Differential 20% to 80% V Notes: 12. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew 13. 50% duty cycle; standard load; differential operation 14. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points. 15. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07469 Rev.*G Page 4 of 9 FastEdge™ Series CY2DP3110 Timing Definitions VCC VCM R M ax = VCC V IH VPP V P P ra n g e 0 .1 V - 1 .3 V VCM R V IL V C M R M in = V E E + 1 .2 VEE Figure 1. PECL/ECL Input Waveform Definitions VCC V C C = 3 .3 V V X m a x = 0 .9 V V IH V D IF V D IF = > = 0 .4 V m in VX V IL V E E = 0 .0 V VEE V X M in = 0 .6 8 Figure 2. HSTL Differential Input Waveform Definitions tr, tf, 2 0 -8 0 % VO Figure 3. ECL/LVPECL Output In p u t C lo c k V P P TP L H , T P D TP H L O u tp u t C lo c k V O tS K (O ) A n o th e r O u tp u t C lo c k Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Document #: 38-07469 Rev.*G Page 5 of 9 FastEdge™ Series CY2DP3110 Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm 5" P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm 5" R T = 50 ohm DUT C Y2DP3110 R T = 50 ohm VTT VTT Figure 5. CY2DP3110 AC Test Reference Applications Information Termination Examples CY2DP3110 VTT VCC R T = 50 ohm R T = 50 ohm 5" Zo = 50 ohm 5" VTT VEE Figure 6. Standard LVPECL – PECL Output Termination CY2DP3110 VTT R T = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 7. Driving a PECL/ECL Single-ended Input Document #: 38-07469 Rev.*G Page 6 of 9 FastEdge™ Series CY2DP3110 C Y 2D P 3110 3 .3 V V C C = 3 .3 V 120 ohm L V D S 5" Z o = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) L V P E C L to L V D S V E E = 0V Figure 8. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface VDD-2 VCC X Y Z One output is shown for clarity Figure 9. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and supplies. Ordering Information Part Number Package Type Product Flow CY2DP3110AI 32-pin TQFP Industrial, –40° to 85°C CY2DP3110AIT 32-pin TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07469 Rev.*G Page 7 of 9 FastEdge™ Series CY2DP3110 Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 Dimensions in mm 51-85088-*B FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07469 Rev.*G Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. FastEdge™ Series CY2DP3110 Document History Page Document Title: CY2DP3110 FastEdge™ Series 1 of 2:10 Differential Clock/Data Fanout Buffer Document Number: 38-07469 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 121284 11/12/02 RGL New Data Sheet *A 126251 04/15/03 RGL Added VBB in the block diagram Corrected specs that does not match EROS/IROS Changed VOHMIN in PECL Output table to VCC-1.2V Shifted table on ECL levels to match PECL Added power-up requirements to absolute maximum conditions Changed title (ComLink to FastEdge) *B 127696 06/12/03 RGL Changed operation value from 3.0 GHz to 1.5 GHz in features Modified Note 21: reduced swing value from up to 3 GHz to 2.2 GHz *C 128731 08/04/03 RGL Specified TTB value from TBD to 250 ps Specified Vo (pp) values from TBDs to 0.34 ps(min) at < 1.5 GHz, 0.30 ps (typ) at 2.2 GHz Changed Jitter value from 10 ps to 1 ps (intrinsic) *D 130299 11/19/03 RGL Corrected the “VCCO” to “VCC” in the Pin Configuration diagram. *E 227708 See ECN RGL/GGK Changed the max. Dissipation, Junction to ambient from 100 to 70°C/W Added Junction Temperature(TJ) parameter of 150°C max Replaced ICC calculation with power calculation in the footnote *F 229393 See ECN RGL/GGK Provided data for TBD’s to match the device *G 247626 See ECN RGL/GGK Changed VOH and VOL to match the Char Data Document #: 38-07469 Rev.*G Page 9 of 9