CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description ■ True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power ■ High speed access: 15 ns ■ Low operating power: ICC = 110 mA (maximum) ■ Fully asynchronous operation The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM, in conjunction with the CY7C142/CY7C146 SLAVE dual-port device. They are used in systems that require 16-bit or greater word widths. This is the solution to applications that require shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. ■ Automatic power down ■ Master CY7C132/CY7C136/CY7C136A[1] easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 ■ BUSY output flag on CY7C132/CY7C136/CY7C136A; BUSY input on CY7C142/CY7C146 ■ INT flag for port to port communication (52-Pin PLCC/PQFP versions) ■ CY7C136, CY7C136A, and CY7C146 available in 52-pin PLCC and 52-pin PQFP packages ■ Pb-free packages available Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data is placed in an unique location (7FF for the left port and 7FE for the right port). An automatic power down feature is controlled independently on each port by the chip enable (CE) pins. Logic Block Diagram R/WL CEL R/WR CER OEL OER I/O7L I/O CONTROL I/O0L I/O CONTROL A 0L I/O0R [2] [2] BUSYL A 10L I/O7R BUSYR ADDRESS DECODER CEL OEL MEMORY ARRAY ADDRESS DECODER ARBITRATION LOGIC (7C132/7C136 ONLY) AND INTERRUPTLOGIC (7C136/7C146 ONLY) A 10R A 0R CER OER R/WL R/WR INTL[3] INTR [3] Notes 1. CY7C136 and CY7C136A are functionally identical. 2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 3. Open drain outputs; pull up resistor required. Cypress Semiconductor Corporation Document #: 38-06031 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 24, 2010 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Pinouts BUSYR INTR A10R 52 51 50 49 48 47 46 45 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R 1 2 3 4 5 6 7 8 9 10 11 12 13 OER A0R A1R A2R A3R A4R A5R 39 38 37 36 35 34 33 32 31 30 29 28 27 7C136/7C136A 7C146 A6R A7R A8R A9R NC I/O7R 1415 16 17 18 19 20 21 22 23 24 25 26 I/O5R I/O6R I/O2R I/O3R I/O4R NC GND I/O0R I/O1R I/O6L I/O7L I/O4L I/O5L I/O5R I/O6R I/O2R I/O3R I/O4R I/O0R I/O1R NC GND 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C136/7C136A 40 7C146 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O6L I/O7L CER R/WR BUSYR INTR A10R CER R/WR BUSYL R/W L CEL VCC A0L OEL A10L INTL 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O4L I/O5L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L INTL BUSYL R/W L CEL VCC Figure 2. 52-Pin PQFP (Top View) A0L OEL A10L Figure 1. 52-Pin PLCC (Top View) Selection Guide Specification Maximum Access Time Maximum Operating Current Com’l/Ind Maximum Standby Current Com’l/Ind 7C136-15[4] 7C146-15 7C132-25 [4] 7C136-25 7C142-25 7C146-25 15 190 75 25 170 65 7C132-30 7C136-30 7C142-30 7C146-30 30 170 65 7C132-35 7C136-35 7C142-35 7C146-35 35 120 45 7C132-45 7C136-45 7C142-45 7C146-45 45 120 45 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 55 110 35 Unit ns mA mA Shaded areas contain preliminary information. Note: 4. 15 ns and 25 ns version available in PQFP and PLCC packages only. Document #: 38-06031 Rev. *G Page 2 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 DC Input Voltage ................................................. −3.5V to +7.0V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Range Ambient Temperature VCC 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Commercial Industrial Electrical Characteristics Over the Operating Range Parameter Description 7C136-15[4] 7C146-15 Test Conditions Min VOH Output HIGH voltage VCC = Min., IOH = –4.0 mA VOL Output LOW voltage IOL = 4.0 mA IOL = 16.0 Max 2.4 mA[5] 7C132-30[4] 7C136-25, 30 7C142-30 7C146-25, 30 Min Max 2.4 7C132-35,45 7C136-35,45 7C142-35,45 7C146-35,45 Min Max 2.4 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 Min Max 2.4 V 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 VIH Input HIGH voltage 2.2 2.2 VIL Input LOW voltage IIX Input load current GND < VI < VCC –5 +5 −5 +5 −5 +5 IOZ Output leakage current GND < VO < VCC, Output Disabled –5 +5 −5 +5 −5 +5 IOS Output short circuit current[6] VCC = Max., VOUT = GND ICC VCC Operating Supply Current CE = VIL, Outputs Open, f = fMAX[7] ISB1 0.8 2.2 0.8 2.2 0.8 Unit V V 0.8 V −5 +5 μA −5 +5 μA –350 −350 −350 −350 mA Com’l/ Ind’l 190 170 120 110 mA Standby current CEL and CER > VIH, [7] both ports, TTL f = f MAX Inputs Com’l/ Ind’l 75 65 45 35 mA ISB2 Standby Current CEL or CER > VIH, One Port, Active Port Outputs Open, TTL Inputs f = fMAX[7] Com’l/ Ind’l 135 115 90 75 mA ISB3 Com’l/ Standby Current Both Ports CEL and Both Ports, CER > VCC – 0.2V, VIN > VCC – 0.2V Ind’l CMOS Inputs or VIN < 0.2V, f = 0 15 15 15 15 mA ISB4 Standby Current One Port CEL or CER > VCC – 0.2V, Com’l/ One Port, Ind’l VIN > VCC – 0.2V or VIN < 0.2V, CMOS Inputs [7] Active Port Outputs Open, f = fMAX 125 105 85 70 mA Shaded areas contain preliminary information. Notes 5. BUSY and INT pins only. 6. Duration of the short circuit should not exceed 30 seconds. 7. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. Document #: 38-06031 Rev. *G Page 3 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Capacitance This parameter is guaranteed but not tested. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 15 pF 10 pF TA = 25°C, f = 1 MHz, VCC = 5.0V Figure 3. AC Test Loads and Waveforms R1 893Ω 5V OUTPUT 5V R1 893Ω 5V OUTPUT R2 347Ω 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 347Ω 5 pF INCLUDING JIG AND SCOPE (a) BUSY Output Load (CY7C132/CY7C136 Only) ALL INPUT PULSES 3.0V 250Ω 1.4V 30 pF (b) THÉVENIN EQUIVALENT OUTPUT 281Ω BUSY OR INT GND 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [8] Parameter Description 7C136-15 [4] 7C146-15 7C132-25 [4] 7C136-25 7C142-25 7C146-25 Min Min Max Max 7C132-30 7C136-30 7C142-30 7C146-30 Min Unit Max Read Cycle tRC Read Cycle Time 15 [9] tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid [9] tDOE OE LOW to Data Valid [9] tLZOE OE LOW to Low Z [7, 10] tHZOE OE HIGH to High Z 15 0 CE LOW to Low Z tHZCE CE HIGH to High Z [7, 10, 11] tPU CE LOW to Power Up [7] 3 5 ns 30 ns 20 ns ns ns 15 ns 15 ns 5 15 0 15 30 3 15 10 0 [7] 15 3 10 ns 0 25 10 [7, 10] CE HIGH to Power Down 0 3 [7, 10, 11] 30 25 15 tLZCE tPD 25 ns 0 25 ns 25 ns Shaded areas contain preliminary information. Notes 8. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30 pF load capacitance. 9. AC test conditions use VOH = 1.6V and VOL = 1.4V. 10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 11. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady state voltage. Document #: 38-06031 Rev. *G Page 4 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [8] (continued) Parameter Write Description 7C136-15 [4] 7C146-15 7C132-25 [4] 7C136-25 7C142-25 7C146-25 Min Min Max Max 7C132-30 7C136-30 7C142-30 7C146-30 Min Unit Max Cycle[12] tWC Write Cycle Time 15 25 30 ns tSCE CE LOW to Write End 12 20 25 ns tAW Address Setup to Write End 12 20 25 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Setup to Write Start 0 0 0 ns tPWE R/W Pulse Width 12 15 25 ns tSD Data Setup to Write End 10 15 15 ns tHD Data Hold from Write End 0 0 0 ns [7] tHZWE R/W LOW to High Z tLZWE R/W HIGH to Low Z [7] 10 0 15 0 15 ns 0 ns Busy/Interrupt Timing tBLA BUSY LOW from Address Match Mismatch[13] 15 20 20 ns 15 20 20 ns tBHA BUSY HIGH from Address tBLC BUSY LOW from CE LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH[13] 15 20 20 ns tPS Port Set Up for Priority 5 5 5 ns tWB R/W LOW after BUSY LOW[14] 0 0 0 ns tWH R/W HIGH after BUSY HIGH 13 20 30 ns tBDD BUSY HIGH to Valid Data 15 25 30 ns tDDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns tWDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns Interrupt Timing [16] tWINS R/W to INTERRUPT Set Time 15 25 25 ns tEINS CE to INTERRUPT Set Time 15 25 25 ns tINS Address to INTERRUPT Set Time 15 25 25 ns tOINR OE to INTERRUPT Reset Time[13] 15 25 25 ns tEINR CE to INTERRUPT Reset Time [13] 15 25 25 ns tINR Address to INTERRUPT Reset Time[13] 15 25 25 ns Shaded areas contain preliminary information. Notes 12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 14. CY7C142/CY7C146 only. 15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 16. 52-pin PLCC and PQFP versions only. Document #: 38-06031 Rev. *G Page 5 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [8] Parameter Description 7C132-35 7C136-35 7C142-35 7C146-35 Min Max 7C132-45 7C136-45 7C142-45 7C146-45 Min Max 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 Min Unit Max Read Cycle tRC Read Cycle Time tAA Address to Data Valid[9] 35 tOHA Data Hold from Address Change 45 35 0 55 45 0 ns 55 ns 0 ns tACE [9] CE LOW to Data Valid 35 45 55 ns tDOE OE LOW to Data Valid[9] 20 25 25 ns 25 ns Z[7, 10] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[7, 10, 11] tLZCE CE LOW to Low Z[7, 10] CE HIGH to High tPU CE LOW to Power Up[7] Write CE HIGH to Power 3 20 5 Z[7, 10, 11] tHZCE tPD 3 5 20 0 Down[7] 3 20 5 20 0 35 ns ns 25 ns 0 35 ns 35 ns Cycle[12] tWC Write Cycle Time 35 45 55 ns tSCE CE LOW to Write End 30 35 40 ns tAW Address Setup to Write End 30 35 40 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Setup to Write Start 0 0 0 ns tPWE R/W Pulse Width 25 30 30 ns tSD Data Setup to Write End 15 20 20 ns tHD Data Hold from Write End 0 tHZWE R/W LOW to High Z [7] tLZWE R/W HIGH to Low Z [7] 0 20 0 0 20 0 ns 25 ns 0 ns Busy/Interrupt Timing tBLA BUSY LOW from Address Match tBHA BUSY HIGH from Address tBLC BUSY LOW from CE LOW Mismatch[13] HIGH[13] 20 25 30 ns 20 25 30 ns 20 25 30 ns 20 25 30 ns tBHC BUSY HIGH from CE tPS Port Set Up for Priority 5 5 5 ns tWB R/W LOW after BUSY LOW[14] 0 0 0 ns tWH R/W HIGH after BUSY HIGH 30 35 35 ns tBDD BUSY HIGH to Valid Data 35 45 45 ns tDDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns tWDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns Document #: 38-06031 Rev. *G Page 6 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [8] (continued) Parameter 7C132-35 7C136-35 7C142-35 7C146-35 Description Min Interrupt Max 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 7C132-45 7C136-45 7C142-45 7C146-45 Min Max Min Unit Max Timing [16] tWINS R/W to INTERRUPT Set Time 25 35 45 ns tEINS CE to INTERRUPT Set Time 25 35 45 ns tINS Address to INTERRUPT Set Time 25 35 45 ns tOINR OE to INTERRUPT Reset Time[13] 25 35 45 ns tEINR CE to INTERRUPT Reset Time[13] 25 35 45 ns 25 35 45 ns tINR Address to INTERRUPT Reset Time[13] Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port-Address Access) [17, 18] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (Either Port-CE/OE )[17, 19] CE tHZCE tACE OE tLZOE tHZOE tDOE tLZCE DATA VALID DATA OUT tPU tPD ICC ISB Notes 17. R/W is HIGH for read cycle. 18. Device is continuously selected, CE = VIL and OE = VIL. 19. Address valid prior to or coincident with CE transition LOW. Document #: 38-06031 Rev. *G Page 7 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A) tRC ADDRESSR ADDRESS MATCH R/WR tPWE DINR VALID tPS ADDRESS MATCH ADDRESSL tBHA BUSYL tBLA tBDD DOUTL VALID tWDD tDDD Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port) [12, 20] tWC ADDRESS tSCE CE tSA tAW tHA tPWE R/W tSD DATAIN tHD DATA VALID OE tHZOE HIGH IMPEDANCE DOUT Note 20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. Document #: 38-06031 Rev. *G Page 8 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[12, 21] tWC ADDRESS tSCE tHA CE tAW tSA tPWE R/W tSD DATAIN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DOUT Figure 9. Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESSL,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESSL,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Note 21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state. Document #: 38-06031 Rev. *G Page 9 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) Figure 10. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146) CE tPWE R/W tWB tWH BUSY Document #: 38-06031 Rev. *G Page 10 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Switching Waveforms (continued) Interrupt Timing Diagrams [16] Figure 12. Left Side Sets INTR tWC ADDRESSL WRITE 7FF tINS CEL tHA tEINS R/WL tSA tWINS INTR Figure 13. Right Side Clears INTR tRC ADDRESSR READ 7FF tHA tINR CER tEINR R/WR OER tOINR INTR Figure 14. Right Side Sets INTL tWC ADDRESSR WRITE 7FE tINS tHA CER tEINS R/WR INTL tSA tWINS Figure 15. Right Side Clears INTL tRC ADDRESSL READ 7FE tHA CEL tINR tEINR R/WL OEL tOINR INTL Document #: 38-06031 Rev. *G Page 11 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Figure 16. Typical DC and AC Characteristics 1.2 ICC 1.0 0.8 0.6 0.4 0.0 4.0 4.5 5.0 1.0 0.8 0.6 VCC = 5.0V VIN = 5.0V 0.4 0.2 ISB3 0.2 ICC 5.5 ISB3 0.6 –55 6.0 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 TA = 25°C 1.4 1.2 1.0 VCC = 5.0V 0.8 0.9 5.0 5.5 0.6 –55 6.0 25 2.5 25.0 2.0 15.0 1.5 0.5 SUPPLY VOLTAGE (V) Document #: 38-06031 Rev. *G 0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 VCC = 5.0V TA = 25°C 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED ICC vs. CYCLE TIME VCC = 5.0V TA = 25°C VIN = 0.5V 1.0 VCC = 4.5V TA = 25°C 5.0 5.0 1.0 0.75 10.0 1.0 4.0 0 1.25 20.0 3.0 0 NORMALIZED ICC 30.0 2.0 20 125 DELTA tAA (ns) NORMALIZED tPC 3.0 1.0 VCC = 5.0V TA = 25°C 40 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 0 60 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0.0 80 125 1.6 1.4 4.5 100 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.0 120 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0.8 4.0 25 OUTPUT SINK CURRENT (mA) 1.2 NORMALIZED ICC, ISB NORMALIZED ICC, ISB 1.4 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 0 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 12 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Ordering Information Speed (ns) 25 Ordering Code Package Diagram CY7C136-25JXC 51-85004 52-Pin Plastic Leaded Chip Carrier (Pb-Free) CY7C136-25NC 51-85042 52-Pin Plastic Quad Flatpack CY7C136-25NXC 55 CY7C136-25JXI 51-85004 52-Pin Plastic Leaded Chip Carrier (Pb-Free) CY7C136-55JC 51-85004 52-Pin Plastic Leaded Chip Carrier CY7C136-55NC Commercial Industrial Commercial 52-Pin Plastic Leaded Chip Carrier (Pb-Free) 51-85042 52-Pin Plastic Quad Flatpack 51-85004 52-Pin Plastic Leaded Chip Carrier (Pb-Free) CY7C136-55NXC CY7C136A-55JXI Operating Range 52-Pin Plastic Quad Flatpack (Pb-Free) CY7C136-55JXC 55 Package Type 52-Pin Plastic Quad Flatpack (Pb-Free) CY7C136A-55NXI 51-85042 52-Pin Plastic Quad Flatpack (Pb-Free) CY7C146-55JXC 51-85004 52-Pin Plastic Leaded Chip Carrier (Pb-Free) Industrial Commercial Ordering Code Definitions CY 7 C XXX XX AS X C Temperature Grade: Commercial Pb-free (RoHS Compliant) Package: J = PLCC; N = PQFP Speed grade: 25/55 ns Density Technology: CMOS Family: Dual-port SRAM Company ID: CY = Cypress Document #: 38-06031 Rev. *G Page 13 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Package Diagrams Figure 17. 52-Pin Plastic Leaded Chip Carrier, 51-85004 51-85004 *B Figure 18. 52-Pin Plastic Quad Flatpack, 51-85042 51-85042 *A Document #: 38-06031 Rev. *G Page 14 of 15 [+] Feedback CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document History Page Document Title: CY7C132, CY7C136, CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Document Number: 38-06031 ECN Submission Date Orig. of Change ** 110171 10/21/01 SZV Change from Spec number: 38-06031 *A 128959 09/03/03 JFU Added CY7C136-55NI to Order Information Revision Description of Change *B 236748 See ECN YDT Removed cross information from features section *C 393184 See ECN YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC, CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC *D 2623658 12/17/08 *E 2678221 03/24/2009 VKN/AESA Added CY7C136A-55JXI, and CY7C136A-55NXI parts. *F 2896210 03/22/2010 RAME Updated Ordering Information Updated Package Diagrams *G 3094400 11/24/10 ADMU Removed partnumber CY7C136-55JI from the ordering information table. Added ordering code definitions. VKN/PYRS Added CY7C136-25JXI part Removed CY7C132/142 from the Ordering information table Removed 48-Pin DIP and 52-Pin Square LCC package from the data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. 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Document #: 38-06031 Rev. *G Revised November 24, 2010 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback