MAXIM MAX1463EAI

19-2549; Rev 0; 8/02
Low-Power Two-Channel Sensor
Signal Processor
The MAX1463 is a highly integrated, low-power, twochannel sensor signal processor optimized for industrial and process control applications such as pressure
sensing and compensation, RTD and thermal-couple
linearization, weight sensing and classification, and
remote process monitoring with limit indication.
The MAX1463 accommodates sensors with outputs
ranging from 1mV/V to 1V/V and supports both programmable current and voltage sensor excitation. The
MAX1463 provides amplification, calibration, signal linearization, and temperature compensation that enable
an overall performance approaching the inherent
repeatability of the sensor without requiring any external trim components.
Two 16-bit voltage output DACs and two 12-bit PWMs
can be used to indicate each of the temperature-compensated sensor signals independently, as a sum or
difference signal, or user-defined relationship between
each signal and temperature. Uncommitted op amps
are available for buffering the DAC outputs, driving
heavier external loads, or providing additional gain and
filtering.
The MAX1463 incorporates a 16-bit CPU, user-programmable 4kB of FLASH program memory, 128 bytes
of FLASH user information, one 16-bit ADC, two 16-bit
DACs, two 12-bit PWM digital outputs, four Rail-to-Rail®
op amps, one SPI™-compatible interface, two GPIOs,
and one on-chip temperature sensor.
The MAX1463 operates from a single 5.0V supply and
is packaged for automotive, industrial, and commercial
temperature ranges in a 28-pin SSOP package.
Applications
Features
♦ Programmable Amplification, Calibration,
Linearization, and Temperature Compensation
♦ Two Differential or Four Single-Ended Sensor
Input Channels
♦ Accommodates Sensor Output Sensitivities from
1mV/V to 1V/V
♦ Two DAC/PWM Output Signal Channels
♦ 4–20mA Output Capability
♦ 4kB of FLASH Memory for Code and Coefficients
♦ 128 Bytes of FLASH Memory for User Information
♦ Integrated Temperature Sensor
♦ Flexible Dual Op-Amp Blocks
♦ Programmable Sensor Input Gain and Offset
♦ Programmable Sensor Sampling Rate and
Resolution
♦ Programmable Current Excitation Source for
Bridge Sensors
♦ Buffered 1.25V Output Reference
♦ No External Trim Components Required
Ordering Information
PART
TEMP RANGE
MAX1463CAI
0°C to +70°C
28 SSOP
MAX1463C/W*
0°C to +70°C
Die
MAX1463EAI
-40°C to +85°C
28 SSOP
MAX1463AAI
-40°C to +125°C
28 SSOP
*Dice are tested at TA = +25°C, DC parameters only.
Pressure Sensor Signal Conditioning
Pin Configuration
Weight Measurement Systems
Thermocouple and RTD Linearization
Transducers and Transmitters
Process Indicators
Calibrators and Controllers
GMR and MR Magnetic Direction Sensors
Functional Diagram and Detailed Block Diagram appear at
end of data sheet.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
SPI is a trademark of Motorola, Inc.
PIN-PACKAGE
TOP VIEW
OUT1SM 1
28 OUT2SM
AMP1M 2
27 AMP2M
AMP1P 3
26 AMP2P
OUT1LG 4
25 OUT2LG
VBG 5
VDD 6
24 ISRC
MAX1463
23 INP1
N.C. 7
22 INM1
CKSEL 8
21 INP2
CKIO 9
20 INM2
CS 10
19 VREF
DO 11
18 VSS
DI 12
17 GPIO2
SCLK 13
16 GPIO1
VSS 14
15 VDDF
SSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1463
General Description
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
ABSOLUTE MAXIMUM RATINGS
VDD - VSS ...............................................................-0.3V to +6.0V
All Other Pins to VSS ...................................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Operating Temperature Ranges (TMIN to TMAX)
MAX1463CAI .....................................................0°C to +70°C
MAX1463EAI...................................................-40°C to +85°C
MAX1463AAI ................................................-40°C to +125°C
MAX1463C/W.....................................................0°C to +70°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5.0V, VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
Supply Voltage
VDD
VSS = 0V
4.5
5.0
5.5
V
Base Operating Current
IBO
CPU stopped (Note 2)
640
715
785
µA
CPU Current
ICPU
All modules off, CPU = on, additive to IBO
(Note 3)
650
820
995
µA
All modules off, ADC = on, ADC clk =
1MHz, additive to IBO; the CPU and ADC
are not on at the same time (Note 3)
840
1035
1150
ADC Current
IADC
µA
All modules off, ADC = on, ADC clk = 7kHz,
additive to IBO; the CPU and ADC are not
on at the same time (Note 3)
510
720
850
DAC Current
IDACn
All modules off, DAC = on, additive to IBO,
(n = 1 or 2) (Note 4)
400
470
520
µA
Large Op-Amp Current
IOPLGn
All modules off, CPU stopped, large op
amp = on (n = 1 or 2)
350
585
700
µA
Small Op-Amp Current
IOPSMn
All modules off, CPU stopped, small op
amp = on (n = 1 or 2)
130
175
210
µA
ANALOG INPUT
Differential Input Impedance
(INP1 to INM1 and
INP2 to INM2)
2
RDIN
PGA[4:0] = 00000, CLK[2:0] = 000
4
PGA[4:0] = 01010, CLK[2:0] = 000
100
PGA[4:0] = 11110, CLK[2:0] = 000
62.5
PGA[4:0] = 00000, CLK[2:0] = 011
32
PGA[4:0] = 01010, CLK[2:0] = 011
800
PGA[4:0] = 11110, CLK[2:0] = 011
500
PGA[4:0] = 00000, CLK[2:0] = 110
256
PGA[4:0] = 01010, CLK[2:0] = 110
6.4
PGA[4:0] = 01000, CLK[2:0] = 110
4
_______________________________________________________________________________________
MΩ
kΩ
MΩ
kΩ
MΩ
Low-Power Two-Channel Sensor
Signal Processor
(VDD = 5.0V, VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Single-Sided Input Impedance
(INP1 to VSS, INM1 to VSS,
INP2 to VSS, INP2 to VSS)
Common-Mode Rejection Ratio
SYMBOL
RSIN
CMRR
Differential Signal-Gain Range
Differential Signal Gain
Gain-Error Temperature
Coefficient
CONDITIONS
MIN
PGA[4:0] = 00000, CLK[2:0] = 000
2
PGA[4:0] = 01010, CLK[2:0] = 000
50
PGA[4:0] = 11110, CLK[2:0] = 000
31.2
PGA[4:0] = 00000, CLK[2:0] = 011
16
PGA[4:0] = 01010, CLK[2:0] = 011
400
PGA[4:0] = 11110, CLK[2:0] = 011
250
PGA[4:0] = 00000, CLK[2:0] = 110
128
PGA[4:0] = 01010, CLK[2:0] = 110
3.2
PGA[4:0] = 01000, CLK[2:0] = 110
2
Common-mode voltage VCM = VSS to VDD
GETCADC
MAX
UNITS
MΩ
kΩ
MΩ
kΩ
MΩ
90
Selectable in 17 steps (Note 5)
AVDIFF
TYP
dB
0.94–240
PGA[4:0] = 00000
0.90
0.94
1.0
PGA[4:0] = 00001
7.0
7.4
8.0
PGA[4:0] = 01010
68
73
78
PGA[4:0] = 10100
125
133
143
PGA[4:0] = 11110
220
240
260
V/V
PGA[4:0] = 00000
-8
ppm/°C
3-bit plus sign
4
Bits
COARSE-OFFSET DAC
Resolution
COREF = VDD,
CO[3:0] = 0111
Effective Offset Adjustment at the
ADC Input
OAADC
COREF = VDD,
CO[3:0] = 0011
COREF = VDD,
CO[3:0] = 0000
PGA[4:0] =
00000 to 01000
130
135
140
PGA[4:0] =
01010 to 10000
256
266
276
PGA[4:0] =
10100 to 11110
450
481
510
PGA[4:0] =
00000 to 01000
55
60
65
PGA[4:0] =
01010 to 10000
107
117
127
PGA[4:0] =
10100 to 11110
180
210
240
PGA[4:0] =
00000 to 01000
0
5
10
PGA[4:0] =
01010 to 10000
3
9
15
PGA[4:0] =
10100 to 11110
-4
+8
+20
% of
ADC
Ref
_______________________________________________________________________________________
3
MAX1463
ELECTRICAL CHARACTERISTICS (continued)
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5.0V, VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
PGA[4:0] =
00000 to 01000
8
12
16
PGA[4:0] =
01010 to 10000
17
23
30
PGA[4:0] =
10100 to 11110
23
33
43
PGA[4:0] =
00000 to 01000
-50
-44
-40
PGA[4:0] =
01010 to 10000
-94
-87
-80
PGA[4:0] =
10100 to 11110
-185
-169
-155
PGA[4:0] =
00000 to 01000
-124
-117
-110
PGA[4:0] =
01010 to 10000
-250
-238
-225
PGA[4:0] =
10100 to 11110
-475
-445
-415
VOS_SM
0
±7
IB_SM
±1
nA
COREF = VDD,
CO[3:0] = 1000
Effective Offset Adjustment at the
ADC Input
OAADC
COREF = VDD,
CO[3:0] = 1011
COREF = VDD,
CO[3:0] = 1111
UNITS
% of
ADC
Ref
SMALL OP AMP
Input Offset Voltage
Input Bias Current
mV
DC Gain
AVOL_SM
OUTnSM = 0.5V to 4.5V (n = 1 or 2),
RLOAD = ∞
100
dB
Gain Bandwidth Product
GBW_SM
AVOL_SM = +1V/V
2.7
MHz
SR_SM
AVOL_SM = +1V/V
Slew Rate
Common-Mode Input Range
CMR_SM
2.2
VSS
V/µs
VDD
V
Common-Mode Rejection Ratio
CMRR_SM
VCM_OPAMP = VSS to VDD
70
dB
Power-Supply Rejection Ratio
PSRR_SM
At DC
70
dB
Input-Referred Noise Voltage
VN_SM
Output High Voltage
VOH_SM
Output Low Voltage
VOL_SM
Output Source Current
Output Sink Current
Maximum Output Load
Capacitance
4
0.1Hz to 1kHz
8.5
0.1Hz to 1MHz
100
RLOAD = ∞
4.9
RLOAD = 4.7kΩ to VSS
4.85
µVRMS
V
RLOAD = ∞
0.1
RLOAD = 4.7kΩ to VDD
0.15
ISRC_SM
VOUTnSM = VOH_SM, RLOAD = 4.7kΩ to VSS
-1.04
mA
ISNK_SM
VOUTnSM = VOL_SM, RLOAD = 4.7kΩ to VDD
1.04
mA
CL_SM
RLOAD = ∞, phase margin > 55°
120
_______________________________________________________________________________________
V
pF
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5.0V, VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOS_LG
0
±4
mV
IB_LG
±225
nA
100
dB
LARGE OP AMP
Input Offset Voltage
Input Bias Current
DC Gain
AVOL_LG
OUTnLG = 0.5V to 4.5V (n = 1 or 2),
RLOAD = ∞
Gain Bandwidth Product
GBW_LG
AVOL_LG = +1V/V
4.0
MHz
SR_LG
AVOL_LG = +1V/V
3.2
V/µs
Slew Rate
Common-Mode Input Range
CMR_LG
VSS
VDD
V
Common-Mode Rejection Ratio
CMRR_LG
VCM OPAMP = VSS to VDD
70
dB
Power-Supply Rejection Ratio
PSRR_LG
At DC
70
dB
0.1Hz to 1kHz
19
0.1Hz to 1MHz
160
Input-Referred Noise Voltage
VN_LG
Output High Voltage
VOH_LG
Output Low Voltage
VOL_LG
Output Source Current
Output Sink Current
RLOAD = ∞
4.95
RLOAD = 1kΩ to VSS
4.90
µVRMS
V
RLOAD = ∞
0.03
RLOAD = 1kΩ to VDD
0.12
ISRC_LG
VOUTnLG = VOH_LG, RLOAD = 1kΩ to VSS
-4.9
mA
ISNK_LG
VOUTnLG = VOL_LG, RLOAD = 1kΩ to VDD
4.9
mA
Maximum Output Load
Capacitance
CL_LG
RLOAD = ∞, phase margin > 55°
200
V
pF
OP-AMP SWITCH
Analog Signal Range
VSW
On-Resistance
RON
VSS
5
VDD
kΩ
V
Off-Isolation
VISO
80
dB
RESDAC
16
Bits
DIGITAL-TO-ANALOG CONVERTER
Resolution
Integral Nonlinearity
INLDAC
3
Bits
Differential Nonlinearity
DNLDAC
±1
Bits
Offset Error
VDAC OS
DAC ref = VDD, DAC data = 0000h
Bit Weight
BWDAC
DAC ref = 5VDC
Power-Supply Rejection Ratio
PSRRDAC
VDD / 2
- 0.05
VDD / 2
+ 0.05
91.55
V
µV/LSB
At DC, DAC ref = VREF
60
dB
Output Noise
ONDAC
DAC buffer is the small op amp
±3
LSB
Output Settling Time
STDAC
To 0.1% of final value
250
µs
12
Bits
8.192
ms
PULSE-WIDTH MODULATOR
Resolution
Period
RESPWM
PPWM
(Note 6)
fCLK = 4.0 MHz
_______________________________________________________________________________________
5
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5.0V, VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Bit Weight
BWPWM
Offset Error
VPWM_OS
Gain Error
GEPWM
Output Jitter
OJPWM
CONDITIONS
MIN
PWM data = 0000h
(Note 7)
TYP
MAX
UNITS
2
µs/LSB
±1
µs
±0.025
%
1/4
LSB
EXTERNAL REFERENCE INPUT
Reference Input Range
Reference Input Resistance
VREF
RREF RES
1.25
VREF = 4V, ADC = ON, DACs = ON
100
(Note 8)
4.2
VDD
V
kΩ
INTERNAL VOLTAGE REFERENCE
Internal Voltage Reference
VIR
Temperature Coefficient
TCIR
4.6
5.0
±110
V
ppm/°C
BUFFERED VOLTAGE REFERENCE OUTPUT
Buffered Bandgap Reference
VBG
Temperature Coefficient
RLOAD = ∞
1.15
RLOAD = 47kΩ to VSS
1.12
TCBG
1.24
1.32
110
V
ppm/°C
CURRENT SOURCE
ISRC[2:0] = 000
Source Current
IISRC
Maximum ISRC Voltage
Selectable in 8
steps
0
ISRC[2:0] = 001
-200
-167
-130
ISRC[2:0] = 100
-814
-668
-545
ISRC[2:0] = 111
-1420
-1169
-915
VDD
- 0.85
VISRC
µA
V
TEMPERATURE SENSOR
SensTS
-2
-50
mV / °C
LSB/ °C
Nonlinearity Error
INLTS
±0.5
%FS
Hysteresis
HistTS
±0.1
%FS
Resolution
RESADC
16
Bits
Integral Nonlinearity
INLADC
2
Bits
Differential Nonlinearity
DNLADC
±1
LSB
4
%FS
±1
LSB
Sensitivity
ANALOG-TO-DIGITAL CONVERTER
ADC Offset Error
VADC_OS
PGA[4:0] = 00000 (0.94),
CO[3:0] = 0000 (Note 9)
Channel-to-Channel Offset Error
Matching
∆VADC_OS
ADC Offset-Supply Rejection
Ratio
OSRRADC
At DC, ADC ref = VREF = 5V
52
dB
ADC Gain-Supply Rejection Ratio
GSRRADC
At DC, ADC ref = VREF = 5V
96
dB
6
_______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
(VDD = 5.0V, VSS = 0V, TA = TMIN to TMAX, fCLK = 4.0MHz. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT (GPIO1, GPIO2, SCLK, DI, CKSEL, CKIO, CS)
Input High Threshold Voltage
VIH
Input Low Threshold Voltage
VIL
Input Hysteresis
0.8 x
VDD
0.2 x
VDD
VIHYS
Input Leakage Current
IIN
Input Capacitance
CIN
V
0.2
V
V
CKSEL, CS = VSS
-50
GPIO1, GPIO2, SCLK, DI, CKIO = VDD
50
5
µA
pF
DIGITAL OUTPUT (GPIO1, GPIO2, DO, CKIO)
GPIO1, GPIO2, DO
RLOAD = ∞
Output Voltage High
CKIO (Note 10)
VOH
RLOAD = 2kΩ to VSS
GPIO1, GPIO2, DO
4.9
CKIO (Note 10)
4.6
0.1
CKIO (Note 10)
VOL
RLOAD = 2kΩ to VDD
V
4.6
GPIO1, GPIO2, DO
RLOAD = ∞
Output Voltage Low
4.9
0.1
GPIO1, GPIO2, DO
0.4
CKIO (Note 10)
V
0.4
FLASH MEMORY
Maximum Erase Cycles
(Notes 11, 12)
10K
Cycles
Minimum Erase Time
tERASE
(Notes 11, 12)
4.2
ms
Minimum Write Time
tWRITE
(Notes 11, 12)
80
µs
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to VSS.
All modules are off, except internal reference, oscillator, VBG buffer, and power-on reset (POR). ISRC is open.
The CPU and ADC are not on at the same time. The ADC and CPU currents are not additive.
IDACn does not include output buffer currents (IOPLGn or IOPSMn).
For gains above 240, an additional digital gain can be provided by the CPU.
The PWM input data is the 12-bit left-justified data in the 16-bit input field.
PWM gain error measured as:
GEPWM =
PWMOUT (F00Xh) − PWMOUT (100Xh)
3584
× 100%
Note 8: The Internal Reference Voltage has a nominal value of 5V (4 ✕ VBG) even when VDD is greater or less than 5VDC.
Note 9: Input-referred offset error is the ADC Offset Error divided by the PGA gain.
Note 10: When the CKIO pin is configured in output mode to observe the internal oscillator signal, the total current is above the
specified limits.
Note 11: fCLK must be within 5% of 4MHz.
Note 12: Allow a minimum elapsed time of 4.2ms when executing a FLASH erase command, before sending any other command.
Allow a minimum elapsed time of 80µs between FLASH write commands.
_______________________________________________________________________________________
7
MAX1463
ELECTRICAL CHARACTERISTICS (continued)
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
TIMING CHARACTERISTICS
(VDD = +5.0V, VSS = 0V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Maximum Programming
Temperature
TPROG
Internal Oscillator Clock
Frequency
fICLK
OSC[4:0] = 00000
External Clock Frequency
fECLK
VCKSEL = 0
MIN
TYP
MAX
70
3.4
4.3
Min
0.2
Max
5
UNITS
°C
5.3
MHz
MHz
External Master Clock Input Low
Time
FECLKIN_LO
tECLK = 1 / fECLK
40
60
%
tECLK
External Master Clock Input High
Time
fECLKIN_HI
tECLK = 1 / fECLK
40
60
%
tECLK
SERIAL INTERFACE (Figure 1)
SCLK Setup to Falling Edge CS
tSC
30
ns
CS Falling Edge to SCLK Rising
Edge Setup Time
tCSS
30
ns
CS Idle Time
tCSI
fCLK = 4MHz
1.5
µs
CS Period
tCS
fCLK = 4MHz
4
µs
SCLK Falling Edge to Data Valid
Delay
tDO
CLOAD = 200pF
Data Valid to SCLK Rising Edge
Setup Time
tDS
30
ns
Data Valid to SCLK Rising Edge
Hold Time
tDH
30
ns
SCLK High Pulse Width
tCH
100
ns
SCLK Low Pulse Width
tCL
100
ns
tCSH
30
ns
CS Rising Edge to SCLK Rising
Edge Hold Time
80
ns
CS Falling Edge to Output
Enable
tDV
CLOAD = 200pF
25
ns
CS Rising Edge to Output
Disable
tTR
CLOAD = 200pF
25
ns
8
_______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
SUPPLY CURRENT
vs. EXTERNAL CLOCK FREQUENCY
2.50
2.45
TA = +25°C
CPU ON 2% OF TIME
ADC ON 98% OF TIME
ADCCLK = 1MHz
DAC1 ON
SMALL OP AMP ON
2.35
2.30
TA = -40°C
MAX1463 toc02
2.30
2.25
2.20
CPU ON 2% OF TIME
ADC ON 98% OF TIME
ADCCLK = 1MHz
DAC1 ON
SMALL OP AMP ON
2.10
2.05
2.25
2.1
4.7
4.9
5.1
5.3
5.5
4.0
4.5
BASE OPERATING CURRENT
vs. SUPPLY VOLTAGE
ADC OUTPUT ERROR
vs. SUPPLY VOLTAGE
0.73
TA = +25°C
0.71
TA = +125°C
0.69
0
-0.01
-0.04
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE, VDD (V)
5.5
ADC INPUT = -0.5 x VDD
-0.02
0.65
BASE
0.7
ADC INPUT = 0.5 x VDD
ADC INPUT = 0
0.01
-0.03
1.1
ADC INPUT = -0.75 x VDD
ADCREF = VDD
PGA[4:0] = 00000
4.5
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE, VDD (V)
-40
-13
15
43
70
98
125
ADC INL
ADC INPUT = 0.75 x VDD
0.02
0.67
DAC + SMALL OP AMP
1.3
TEMPERATURE (°C)
0.03
ADC OUTPUT ERROR (%FS)
TA = -40°C
0.75
ADC
1.5
5.0
0.04
MAX1463 toc04
0.77
4.5
3.5
EXTERNAL CLOCK FREQUENCY (MHz)
0.79
1.7
0.5
3.0
SUPPLY VOLTAGE, VDD (V)
0.81
DAC + LARGE OP AMP
1.9
0.9
2.00
4.5
BASE OPERATING CURRENT, IBO (mA)
2.35
2.15
2.3
5.5
0.006
ADC NONLINEARITY ERROR (%FS)
2.40
2.40
MAX1463 toc06
TA = +125°C
2.5
MODULE CURRENT (mA)
2.55
2.45
MAX1463 toc05
SUPPLY CURRENT, IDD (mA)
2.60
2.50
SUPPLY CURRENT, IDD (mA)
MAX1463 toc01
2.65
MODULE CURRENT
vs. TEMPERATURE
MAX1463 toc03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.004
0.002
0
-0.002
-0.004
PGA[4:0] = 01000
-0.006
-1.0
-0.5
0
0.5
1.0
INPUT VOLTAGE NORMALIZED TO FULL SCALE
_______________________________________________________________________________________
9
MAX1463
Typical Operating Characteristics
(VDD = 5.0V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 5.0V, TA = +25°C, unless otherwise noted.)
ADC DNL
DAC INL
1
0
-1
-2
-3
MAX1463 toc09
0.03
2
0.02
DAC DNL ERROR (LSB)
2
3
MAX1463 toc08
3
DAC DNL
0.04
DAC NONLINEARITY ERROR (%FS)
MAX1463 toc07
4
ADC DNL ERROR (LSB)
0.01
0
-0.01
1
0
-1
-0.02
-2
-0.03
PGA[4:0] = 01000
-0.04
-1.0
-0.5
0
0.5
1.0
-3
-0.8 -0.6 -0.4 -0.2
INPUT VOLTAGE NORMALIZED TO FULL SCALE
0
0.2
0.4
0.6
-0.8 -0.6 -0.4 -0.2
INPUT NORMALIZED TO FULL SCALE
0.05
MAX1463 toc10
5
DAC CODE = 4000h
0
0.2
4
0.04
DAC INPUT = 5555CH (4.5V AT VDD = 5V)
0.03
DAC INPUT = 0000CH (2.5V AT VDD = 5V)
ERROR (%FS)
0.02
1V/div 3
2
0.01
0
-0.01
-0.02
DAC CODE = C000h
DAC INPUT = AAABCH (0.5V AT VDD = 5V)
-0.03
0
-0.04
-0.05
200µs/div
4.5
4.7
4.9
5.1
5.3
5.5
SUPPLY VOLTAGE, VDD (V)
TEMPERATURE SENSOR OUTPUT
vs. TEMPERATURE
4.10
TA = -40°C
4.05
TA = +25°C
4.00
3.95
3.90
3.85
3.80
TA = +125°C
OSCILLATOR
FREQUENCY TRIMMED
TO 4MHz AT +25°C,
VDD = 5V
4.5
4.7
4.9
16000
14000
12000
10000
8000
5.1
5.3
SUPPLY VOLTAGE, VDD (V)
10
18000
MAX1463 toc13
MAX1463 toc12
4.15
TEMPERATURE SENSOR OUTPUT (ADC CODE)
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
5.5
-40
0.4
0.6
0.8
INPUT VOLTAGE NORMALIZED TO FULL SCALE
DAC RATIOMETRICITY ERROR
vs. SUPPLY VOLTAGE
DAC DYNAMIC RESPONSE
1
0.8
MAX1463 toc11
-4
INTERNAL OSCILLATOR FREQUENCY (MHz)
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
-13
15
43
70
98
TEMPERATURE (°C)
______________________________________________________________________________________
125
Low-Power Two-Channel Sensor
Signal Processor
PIN
NAME
1
OUT1SM
Small Op Amp 1 Output
FUNCTION
2
AMP1M
Op Amp 1 Negative Input
3
AMP1P
Op Amp 1 Positive Input
4
OUT1LG
5
VBG
Buffered Bandgap Voltage Output
6
VDD
Positive Supply Voltage Input. Bypass VDD to VSS with a 0.µF ceramic capacitor.
7
N.C.
No Connection
8
CKSEL
Large Op Amp 1 Output
Clock Select Digital Input
9
CKIO
10
CS
SPI Chip Select Digital Input. Active low.
Clock Digital Input/Output
11
DO
SPI Data Output
12
DI
SPI Data Input
13
SCLK
14, 18
VSS
SPI Interface Clock
15
VDDF
16
GPIO1
17
GPIO2
General-Purpose Digital Input/Output 2
19
VREF
External Reference Voltage Input for ADC and DACs
20
INM2
Negative Input for ADC Channel 2
21
INP2
Positive Input for ADC Channel 2
22
INM1
Negative Input for ADC Channel 1
23
INP1
Positive Input for ADC Channel 1
24
ISRC
Current Output for Sensor Excitation
25
OUT2LG
Large Op Amp 2 Output
26
AMP2P
Op Amp 2 Positive Input
27
AMP2M
Op Amp 2 Negative Input
28
OUT2SM
Small Op Amp 2 Output
Negative Power-Supply Input
Positive Supply Voltage for FLASH Memory. Bypass VDDF to VSS with a 0.47µF ceramic capacitor.
General-Purpose Digital Input/Output 1
______________________________________________________________________________________
11
MAX1463
Pin Description
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
tCS
CS
tCSI
tCSS
tCL
tSC
tCH
tCSH
tSC
tCSS
tCL
tCH
tCSH
SCLK
tDS
tDS
tDH
tDH
DI
tDV
tDO
tTR
tDV
tDO
tTR
DO
Figure 1. Serial Interface Timing Diagram
Typical Application Circuit
Analog ratiometric output configuration (Figure 2) provides an output that is proportional to the power-supply
voltage. Ratiometricity is an important consideration for
automotive, battery-operated instruments, and some
industrial applications.
Detailed Description
The MAX1463 is a highly integrated, low-power, twochannel sensor signal processor optimized for industrial and process control applications, such as pressure
sensing and compensation, RTD and thermal-couple
linearization, weight sensing and classification, and
remote process monitoring with limit indication.
The MAX1463 incorporates a 16-bit CPU, user-programmable 4kB of FLASH memory, 128 bytes of
FLASH user information, 16-bit ADC, two 16-bit DACs,
two 12-bit PWM digital outputs, four rail-to-rail op amps,
SPI interface, two GPIOs, and one on-chip temperature
sensor.
Each sensor signal can be amplified, compensated for
temperature, linearized, and the offset and full scale
can be adjusted to the desired value. The MAX1463
can provide outputs as analog voltage (DAC) or digital
(PWM, GPIOs), or simple on/off alarm indication
(GPIOs). The uncommitted op amps can be used to
provide 4–20mA outputs or for additional gain and filtering. Each DAC output is routed to either a small or
12
large op amp. Large op amps are capable of driving
heavier external loads. The unused circuit functions
can be turned off to save power.
All sensor linearization and on-chip temperature compensation is done by a user-defined algorithm stored in
FLASH memory. The user-defined algorithm is programmed over the serial interface and stored in 4kB of
integrated FLASH memory.
The MAX1463 uses an internal 4MHz oscillator or an
externally supplied 4MHz clock. CPU code execution
and ADC operation is fully synchronized to minimize
the noise interference of a CPU-based sensor processor system. The internal clock can be routed off chip for
driving external circuit components to maintain system
synchronization and to avoid clock-beat noise often
found in multiclock systems. The CPU sequentially executes instructions stored in FLASH memory.
Sensor Input
The MAX1463 provides two differential signal inputs,
INP1-INM1 and INP2-INM2. These inputs can also be
configured as four singled-ended signals. Each input
can have a common-mode range from VDD to VSS and
a programmable gain range of 0.94V/V to 240V/V. The
differential input signals are summed with the output of
the coarse offset DAC (CO DAC) for offset correction
prior to being amplified by the programmable gain
amplifier (PGA). The resulting signal is applied to the
differential input of the ADC for conversion.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
5 VDC
100Ω
VDD
VDDF
OUTnSM
INPn
OUT
MAX1463
SENSOR
0.47µF
INMn
0.1µF
100pF
VSS
GND
Figure 2. Basic Bridge Sensor Ratiometric Output Configuration
The CPU can be programmed to measure one or two
differential inputs plus the internal temperature sensor
defined in user-supplied algorithm. For example, the
differential inputs may be measured many times while
the temperature may be measured less frequently.
On-Chip Temperature Sensing
The on-chip temperature sensor is a diode that changes
-2mV/°C over the operating range. The ADC converts the
temperature sensor in a similar manner as the sensor
inputs. During an ADC conversion of the temperature
sensor, the ADC automatically uses the internal 1.25V
reference as the ADC full-scale reference. The temperature data format is 15-bit plus sign in two’s complement
format. There is no programmable gain adjustment for
the temperature sensor input. Offset compensation by
the CO DAC is provided so that the nominal temperature
measurement can be centered at the ADC output midscale value. Additional digital gain and offset correction
can be provided by the CPU.
Output Format
There are two output modules in the MAX1463—DOP1
(DAC Op Amp PWM 1) and DOP2 (DAC Op Amp PWM
2). Each of the DOP modules contains a 16-bit DAC, a
12-bit digital PWM converter, a small op amp, and a
large op amp with high-output drive capability. Each
module can be configured in several different modes to
suit a wide range of output signal requirements. Either
the DAC or the PWM can be selected as the primary
output signal. The DAC output signal must be routed to
one of the two op amps before being made available to
a device pin. See the DAC, Op Amp, PWM Modules
section for details. Additional digital outputs are available on the GPIOs; 4–20mA output format can be
accomplished by using the unrouted op amp.
Initialization
A user-defined initialization routine is required to configure the oscillator frequency and, if necessary, various analog modules, e.g., PGA gain, ADC resolution,
ADC clock settings, etc. After the initialization routine,
the CPU can start execution of the main program.
Power-On Reset
The MAX1463 contains a POR circuit to disable CPU
execution until adequate VDD voltage is available for
operation. Once the power-on state has been reached,
the MAX1463 is kept under reset condition for 250µs
before the CPU starts execution. Below the VDD threshold, all internal CPU registers are set to their POR
default state. Power-on control bits for internal modules
are reset to the OFF condition.
CPU Architecture
The CPU provides a wide range of functionality to be
incorporated in an embedded system. The CPU can
compensate nonlinear and temperature-dependent sensors, check for over/underlimit conditions, output sensor
or temperature data as an analog signal or pulse-widthmodulated digital signal, and execute control strategies.
The CPU can perform a limited amount of signal processing (filtering). A timer is included so that uniform
sampling (equally spaced ADC conversions) of the
input sensors can be performed.
______________________________________________________________________________________
13
The MAX1463 incorporates 16 CPU ports that are directly
accessible by the serial interface. All the CPU ports have
a 16-bit data-word width. The contents of the ports can
be read and written by transferring data to and from the
accumulator register (A) using the RDX and WRX instructions. No other CPU instructions act on the CPU ports.
Three CPU ports PD, PE, and PF have uniquely defined
operation for reading and writing data to and from the
peripheral modules. All CPU ports are static and volatile.
CS
DO
CPU Ports
DI
SCLK
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
SERIAL INTERFACE
CPU
P0
R0
P1
R1 ACCUMULATOR (A)
P2
R2
P1
R3 MULTIPLICAND (N)
P3
R4 MULTIPLIER (M)
P4
R5
P5
R6
P6
R7
P7
R8
P8
R9
PA
RA
PB
RB
PC
PD
PE
RC
PF
RF
CPU PORTS
POINTER (P)
ADDRESS
Modules
INDEX (I)
FLASH MEMORY
(4kB)
RD
RE
CPU REGISTERS
FLASH DATA
INSTRUCTION
ADC Module
Figure 3. CPU Architecture
The CPU registers and ports are implemented in
volatile, static memory. There are several registers contained in various peripheral modules that provide module configuration settings, control functions, and data.
These module registers are accessible through an indirect addressing scheme as described in detail in the
CPU Registers, CPU Ports, and Modules sections.
Figure 3 shows the CPU architecture.
CPU Registers
The MAX1463 incorporates a CPU with 16 internal registers. All of the CPU registers have a 16-bit data word
width. Five of the 16 registers have predefined functional operation dependent on the instruction being executed. The remaining registers are general purpose.
The CPU registers are embedded in the CPU itself and
are not all directly accessible by the serial interface.
The accumulator register (A), the pointer register (P),
and the instruction (FLASH data) can be read through
the serial interface when the CPU is halted. This
enables a single-step mode of code execution to ease
code writing and debugging. A special program
instruction sequence is required to observe the other
CPU registers. Table 1 lists the CPU registers.
14
The MAX1463 modules are the functional blocks used to
process analog and digital signals to and from the CPU.
Each module is addressed through CPU ports PD, PE,
and PF, as described in the CPU Ports section. All modules use static, volatile registers for data retention. There
are three types of module registers: configuration, data,
and control. They are used to put a module into a particular mode of operation. Configuration registers hold configuration bits that control static settings such as PGA
gain, coarse offset, etc. Data registers hold input data
such as DAC and PWM input words or output data such
as the result of an ADC conversion. Control registers are
used to initiate a process (such as an ADC conversion or
a timer) or to turn modules on and off (such as op amps,
DAC outputs, PWM outputs, etc.)
The ADC module (Figure 4) contains a 9-bit to 16-bit
sigma-delta converter with multiplexed differential and
single-ended signal inputs, a CO DAC, four reference
voltage inputs, two differential or four single-ended
external inputs, and 15 single-ended internal voltages
for measurement. The ADC output data is 16-bit two’s
complement format. The conversion channel, modes,
and reference sources are all set in ADC configuration
registers. The conversion time is a function of the
selected resolution and ADC clock frequency. The CPU
can be programmed to convert any of the inputs and
the internal temperature sensor in any desired
sequence. For example, the differential inputs may be
converted many times and conversions of temperature
performed less frequently.
The ADC uses the internal 1.25V bandgap reference
(VBG) when converting the temperature input.
For any other conversions, the ADC reference can be
selected as V DD for conversions ratiometric to the
power supply, VREF pin for conversions relative to an
external voltage, and VBGx4, which is an internally
generated “pseudo” 5.0V reference source. The ADC
voltage reference is also used by the CO DAC to maintain a signal conversion that is ratiometric to the selected reference source.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
VDD
VREF
VBG x 4
CO
DAC
REF
VBG
00h
ADC_CONTROL
INP1
INM1
INP2
M
U
X
INM2
Σ
VSS
M
U
X
VSS
NO.
TEMPERATURE
SENSOR
PGA
SINGLE ENDED
1
VBG
2
OUTnSM
3
OUTnLG
4
VDD
5
VSS
6
DACnOUT VIA OUTnSM
7
DACnOUT VIA OUTnLG
8
INPn
9
INMn
ADC
01h
ADC_DATA_1
02h
ADC_CONFIG_1A
03h
ADC_CONFIG_1B
04h
ADC_DATA_2
05h
ADC_CONFIG_2A
06h
ADC_CONFIG_2B
07h
ADC_DATA_T
08h
ADC_CONFIG_TA
09h
ADC_CONFIG_TB
Figure 4. ADC Module
The four analog inputs (INP1, INM1, INP2, INM2) and
several internal circuit nodes can be multiplexed to the
ADC for a single-ended conversion relative to VSS. The
selection of which circuit node is multiplexed to the ADC
is controlled by the ADC_Control register. The ADC can
measure each of the op-amp output nodes with gain for
converting user-defined circuits or incorporating system
diagnostic test functions. The DAC outputs can be converted by the ADC with either op amp arranged as
unity-gain buffers on the DAC outputs. The internal
power nodes, VDD and VSS, and the bandgap reference
VBG can be multiplexed to the ADC for conversion as
well. These measurement modes are defined and initiated in the ADC_Control register. See Tables 5 and 7 for
the single-ended configuration.
ADC Registers
The ADC module has 10 registers for configuration,
control, and data output. There are three conversion
channels in the ADC; channel 1, channel 2, and temperature. Channels 1 and 2 are associated with the dif-
ferential signal input pairs INP1-INM1 and INP2-INM2,
respectively. The temperature channel is associated
with the integrated temperature sensor. Each channel
has two configuration registers (ADC_Config_nA and
ADC_Config_nB where n = 1, 2, or T) for setting conversion resolution, reference input, coarse offsets, etc.
The data output from a conversion of channel 1, 2, or T
is stored in the respective data output register
ADC_Data_n where n = 1, 2, or T. Each of the channels
can be used to convert single-ended inputs as listed in
Table 7. The ADC_Control register controls which channel is to be converted and what single-ended input, if
any, is to be directed to that channel.
Conversion Start
To initiate an ADC conversion, a word is written to the
ADC_Control register with either CNVT1, CNVT2, or
CNVTT bit set to a 1 (Table 6). When an ADC conversion is initiated, the CPU is halted and all CPU and
FLASH activities cease. All CNVT1, CNVT2, and CNVTT
bits are cleared after the ADC conversion is completed.
______________________________________________________________________________________
15
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Upon completion of the conversion, the ADC result is
latched into the respective ADC_Data_n register. In
addition, the convert bits in control register 0 are all
reset to zero. The CPU clock is then enabled and program execution continues
Single-ended inputs can be converted by either channel 1 or 2 by initiating a conversion on the appropriate
channel with the SE[3:0] bits set to the desired singleended input (Table 7). Several of the single-ended signals are converted with a fixed gain of 0.94V/V or
0.7V/V. The reduced gain of 0.7V/V allows signals at or
near the supply rails to be converted without concern of
saturation. Other single-ended signals can be converted with the full-selectable PGA gain range.
Coarse-Input Offset Adjustment
Differential input signals that have an offset can be partially nulled by the input CO DAC. An offset voltage is
added to the input signal prior to gaining the signal. This
allows a maximum gain to be applied to the differential
input signal without saturating the conversion channel.
The CO signal added to the differential signal is a percentage of the full-scale ADC reference voltage as
referred to the ADC inputs. Low PGA gain settings add
smaller amounts of coarse offset to the differential input.
Large PGA gain settings enable correspondingly larger
amounts of coarse offset to be added to the input signal.
The CO DAC also applies to the temperature channel
enabling offset compensation of the temperature signal.
Programmable Gain Amplifier
The gain of the differential inputs and several singleended inputs can be set to values between 0.94V/V to
240V/V as shown in Table 14. The PGA bits are set in
ADC_Config_nA where n = 1 or 2. The temperature
channel has a fixed gain of 0.94V/V. The gain setting
must be selected prior to initiating a conversion.
Bias Current Settings
The analog circuitry within the ADC module operates
from a current bias setting that is programmable. The
programmable levels of operation are fractions of the
full bias current. The operating power consumption of
the ADC can be reduced at the penalty of increased
conversion times that may be desirable in very-lowpower applications. It is recommended operating the
ADC at full bias when possible. The amount of bias as
a fraction of full bias is shown in Table 19. The setting is
controlled by the BIASn[2:0] bits in the ADC_CONFIG_nB registers where n = 1, 2, or T.
ADC Conversion Time and Resolution
The ADC conversion time is a function of the selected
resolution, ADC clock (FADC), and system clock (fCLK).
The resolution can be selected from 9 bits to 16 bits in
the ADC_Config_nA (where n = 1, 2, or T) register by
bits RESn[2:0]. The lower resolution settings (9 bit) convert faster than the higher resolution settings (16 bit).
The ADC clock FADC is derived from the primary system clock FCLK by a prescalar divisor. The divisor can
be set from 4 to 512, producing a range of FADC from
1MHz down to 7.8125kHz when FCLK is operating at
4.0MHz. Other values of FCLK produce other scaled
values of FADC.
Systems operating with very-low power consumption
benefit from the reduced FADC clock rate. Slower clock
speeds require less operating current. Systems operating from a larger power consumption budget can use
the highest FADC clock rate to improve speed performance over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The
conversion time is calculated by the formula:
TCONVERT = (no. of FADC clocks per conversion) /
FADC
16
Reference Input Voltage Select
The ADC can use one of three different reference voltage inputs depending on the conversion channel and
REFn setting as shown in Table 20. The differential
inputs can be converted ratiometrically to the supply
voltage (VDD), converted ratiometrically to an externally
supplied voltage at pin VREF, or converted nonratiometrically using a fixed voltage source derived from the
internal bandgap voltage source. The temperature
channel is always converted using the internal bandgapderived voltage source and therefore is not selectable.
Output Sample Rate
Generally, the sensor and temperature data are converted and calculated by an algorithm in the execution loop.
The output sample rate of the data depends on the conversion time, the CPU algorithm loop time, and the time to
store the result in the DOPn_DATA register. To achieve
uniform sampling, the instruction code must be written to
provide a consistent algorithm loop time, including
branch instruction variations. This total loop time interval
should be repeatable for a uniform output rate.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
DAC, Op Amp, PWM Modules (DOPn)
There are two output modules in the MAX1463—DOP1
and DOP2 (Figure 5). Each of the DOP modules contains a 16-bit DAC, a 12-bit digital PWM converter, a
small op amp, and a large op amp with high-output
drive capability. Switches in the DOP module enable a
range of interconnectivity among the converters, op
amps, and the external pins. Either the DAC or the
PWM may be selected as the primary output signal.
The DAC output signal is routed to one of the op amps
and made available to a device pin. The signal-switching arrangement also allows the unused op amp to be
configured as an uncommitted device with all connections available to external pins.
The DAC and op amps have a power-control bit in the
power module. When power is disabled, all circuits in
the DAC and the op amp are disabled with inputs and
outputs in a three-state condition. The proper bits in the
power module must be enabled for operation of the
DAC and op amps.
The DAC input is a 16-bit two’s complement value. An
input value of 0000h produces an output voltage of one
half of the DAC reference voltage. The DAC output voltage increases for positive two’s complement numbers,
and decreases for negative two’s complement numbers.
The PWM input is a 12-bit two’s complement value. It
shares the same input register (DOPn_Data) as the
DAC, using the 12 MSBs of the 16-bit register. An input
value of 000Xh produces a 50% duty cycle waveform at
the output. The PWM output duty cycle increases for
positive two’s complement numbers, and decreases for
negative two’s complement numbers.
DOP_n Configuration Options
Each of the DOP modules can be configured in several
different modes to suit a wide range of output signal
requirements. The Functional Diagram shows the various
switch settings of the configuration and control registers.
In situations where configuration settings create a conflict in switch activation, a priority is applied to the switch
logic to prevent the conflict.
The DAC and/or the PWM can be selected as the output signal source. The DAC output signal is routed to
one of the op amps and made available to a device
pin. Selecting the large op amp as the DAC output driver device enables a robust current drive capability for
driving signals into low-impedance loads or across
long lengths of wire. The unity-gain buffer configuration
is automatically selected, and it provides the DAC output signal directly to the device pin OUTnLG. With the
large op amp selected, the small op amp can be used
as an independent device for external circuit applications when the PWM is disabled. Alternatively, the PWM
can also be enabled to drive the OUTnSM device pin,
in which case the small op amp is OFF.
Selecting the small op amp as the DAC output driver
device is useful for routing the output signal to other circuits in an embedded control system with high-impedance load connections. The unity-gain buffer configuration
is automatically selected, and it provides the DAC output
signal directly to the device pin OUTnSM. With the small
op amp selected, the large op amp can be used as an
independent device for external circuit applications when
the PWM is disabled. Alternatively, the PWM can also be
enabled to drive the OUTnLG device pin, in which case
the large op amp is OFF.
The DAC has two reference voltage sources available
by selection, VDD and VREF pin. When the external reference is selected (VREF), the actual DAC reference is
2 x VREF. This allows for some degree of flexibility in
the bit weight of the DAC. The output of the DAC is a
voltage proportional to the reference voltage selected,
where the proportionality scaling (DAC input) is set in
the data input register DOPn_Data.
The DOP module also provides a 12-bit digital PWM
output. At a nominal frequency of 4MHz, the frequency
of the PWM is 122Hz (PWM period = 8.192ms). The
DAC and the PWM share the same input register,
DOPn_Data, where the PWM uses the 12 MSBs, in
two’s-complement format. An input of 000Xh (4 LSBs
are ignored) outputs a 50% duty cycle waveform at the
selected output pin (either OUTnSM or OUTnLG). The
PWM bit weight is 2µs, at a nominal frequency of 4MHz.
The minimum duty cycle is obtained when the input is
800Xh (duty cycle is 0 / 4096 = 0), and the maximum
duty cycle at 7FFXh (duty cycle is 4095 / 4096 =
99.98%). A new PWM input word is only effective at the
end of a current PWM cycle, therefore preventing PWM
glitches on the output.
______________________________________________________________________________________
17
MAX1463
The MAX1463 has a built-in timer that can be used to
ensure that the sampling interval is uniform. The timeout value can be set such that the CPU computations
and the reading of the serial interface, if required, can
be completed before timeout. The GPIO pins can be
utilized to interrupt an external master microcontroller
when the ADC conversion is done and/or when the
CPU computations are done so that the serial interface
can be read quickly.
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
VDD
SW0
VREF X 2
SW10
SM
SW3
OUTnSM
REF
DAC
SW2
SW1
SW4
AMPnM
AMPnP
10h OR 13h
DOPn_DATA
11h OR 14h
DOPn_CONTROL
12h OR 15h
DOPn_CONFIG
30h
OPAMP_CONFIG
SW8
SW6
SW7
PWM
OUTnLG
SW9
LG
SW11
SW5
Figure 5. DOP1 and DOP2 Modules
Either the small or the large op amp in the DOP module
can also be selected as an uncommitted op amp in the
MAX1463. The op amps can be configured as a unitygain buffer, where the output is internally connected to the
negative terminal of the op amp, or a stand-alone op amp,
where both AMPnM and AMPnP can be externally connected for various analog functions. In the case of a
buffer, the device pin AMPnM is in high-impedance mode,
as the feedback loop around the op amp is connected
internally.
Every function of the DOP module can be selected individually (DAC, PWM, or op amp), or two out of the three functions of the DOP module can be selected at the same time
(PWM and op amp, or DAC and PWM, or DAC and op
amp), as there are only two output pins for the module,
OUTnSM and OUTnLG. The various configuration options
for the DOP are shown in Table 21. The PWRDAC and
PWROP bits are in the power-on control register (address
= 31h), and the remaining bits are in the DOP registers.
Timer Module
The timer module (Figure 6) comprises a 12-bit counter, a
4-bit prescalar, and control and configuration registers.
When the timer is enabled and initiated, the system master
18
clock, MCLK, is prescaled by the divisor set by PS[3:0] in
the TMR_Config register and the result applied to the 12bit upcounter. When the counter value matches the timeout value TO[11:0] in register TMR_Config, bit TMDN is set
to 1. The CPU can poll the timer done bit TMDN to check
its status.
The timer module provides a feature that enables the CPU
to be put into a low-power halt mode for the duration of the
timer interval. Setting the ENAHALT bit in the TMR_Control
register while starting the timer (setting the timer enable bit
TMEN to 1), or while the timer is already enabled and
counting halts the CPU at the present instruction until the
TMDN bit becomes set by the counter. The CPU commences execution with the next instruction. All CPU registers and ports are fully static and retain all data during the
elapsed time interval.
The time interval between TMEN being set to 1, and
TMDN being set to 1 can be computed as follows:
Time Interval = (2 / FOSC) x {(prescale value N)
x (timeout value TO[11:0]) + 1.5}
The maximum time interval given FOSC = 4MHz clock is
786ms.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
Oscillator Control
The MAX1463 has a fully integrated oscillator with a
nominal frequency of 4MHz. An external clock source
can be used when the clock select pin CKSEL = 0,
operating all internal timing functions. CKIO can also be
configured as an output source of the internal oscillator
clock. This enables synchronization of the MAX1463
with external circuits requiring a clock source.
Current-Source Module
The current-source module provides a means for exciting
resistive bridge sensors with current sourced from VDD.
The current source can also be used for general-purpose
functions that may be required in an embedded control
system. The amount of current sourced is set in the
Current Source_Control register. The current source is
referenced to the MAX1463 internal bandgap voltage reference and is independent of supply voltage changes.
Figure 7 is the current-source mode.
GPIO Module
The MAX1463 contains two general-purpose digital
input/output (GPIO) modules, GPIO1 and GPIO2, which
can be written and read by CPU control and by the serial interface. These two I/O pins operate independently
of each other. They can be configured as inputs, outputs, or one input and one output. When configured as
an input, there are two modes of sensing digital inputs;
as a voltage or logic level, or as an edge detector. In
edge-detector mode, either a rising or falling edge can
be selected for detection. A bit is set in the GPIO control register upon detection of the selected edge.
The GPIO pins have nominal 100kΩ pulldown resistors
to VSS as in Figure 6. Pulldown resistors provide a low
logic level when the pin is unconnected. The GPIO may
also serve as an input pin and its state is read from the
GPIO control register (Tables 28 and 29). When using
the GPIO pin as a general-purpose output, its output
state is defined by writing to the GPIO control register.
The GPIOn pins may be configured as an alert output
that goes low or high whenever a fault condition happens, e.g., remote sensor line disconnection, overflow
conditions in the CPU program execution, etc.
All input and output control for the GPIO1 and GPIO2
pins are contained in GPIO1_Control (address = 40h)
and GPIO2_Control (address = 41h), respectively.
Figure 8 shows the GPIO1 and GPIO2 modules.
Serial Interface Timing and Operation
The MAX1463 serial interface is a high-speed asynchronous data input and output communication port,
providing access to internal registers for calibration of
embedded control sensor systems. All the FLASH
memory is read and write accessible by the serial interface for programming of instruction code and calibration coefficients. The MAX1463 serial interface can
operate in 4-wire SPI-compatible mode or in a 3-wire
mode (default on power-up). In 3-wire mode, the DI
and DO lines can be tied together, forming a bidirectional data line. The serial interface lines consist of
chip-select (CS), serial clock (SCLK), data in (DI), and
data out (DO).
The MAX1463 serial interface is selected by asserting
CS low. The serial input clock, SCLK, is gated internally
to begin sequencing the DI input data and outputting
the output data onto DO. When CS rises, the data that
was clocked into DI is loaded into an internal register
set (IRS[7:0]). The MAX1463 chip select line CS cannot
be tied low continuously for normal operation.
The serial interface can be used both during sensor
calibration, as well as during normal operation.
Each byte of data written into the MAX1463 serial port
contains a 4-bit addresses nibble (IRSA [3:0]) and a 4bit data nibble (IRSD [3:0]). The IRS register holds both
the IRSD and IRSA nibbles as follows:
IRS [7:0] = IRSD [3:0], IRSA [3:0]
Four bytes of IRS information must be written into the
serial interface to transfer 16 bits of data through IRSD
into a MAX1463 internal register. All serial data written
into the MAX1463 is transferred through the IRS register. The DI is read in with the LSB of the IRSA nibble
first and the MSB of the IRSD nibble last. Figure 9
shows serial interface data input.
The IRSA bits are decoded to determine which register
the IRSD bits should be latched into. The IRSA bits can
address the data holding register (DHR), the
port/FLASH addresses register (PFAR), the command
register (CR), and the interface mode register (IMR).
All serial data read from the serial interface is sourced
from the 16-bit DHR. Any data to be read by the serial
interface must first be placed into the internal DHR register before being accessible for reading by the serial
interface.
______________________________________________________________________________________
19
MAX1463
Power Control
The power to various subcircuits in the MAX1463 can be
turned on and off by CPU control and by the serial interface. Unused subcircuits and modules can be turned off
to reduce power consumption. The default state after
power-on is all subcircuits and modules powered off.
This enables low-power embedded systems to turn on
only the needed modules after exiting a low-power CPU
halt timer interval. Modules can be turned on and off as
needed; however, care must be exercised to allow for
module initialization and settling prior to use.
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
TMR_CONTROL
20h
TMR_CONFIG
21h
12-BIT COUNTER
VDD
33h
ISRC_CONTROL
TIMEOUT VALUE
PRESCALER
ISRC
MCLK
Figure 6. Timer Module
The entire 16-bit content of the DHR register is read out
through the DO pin by applying 16 successive clock
pulses to SCLK while CS remains low. DHR is clocked
out MSB bit first. Figure 10 shows the 4-wire mode data
read from the DHR register
In 4-wire mode, data is transferred into DI during the
clocking of data out of DO. Therefore, the last 8 bits
clocked into the DI pin during this data transfer are
latched into the IRS register and decoded when CS
returns high.
When the MAX1463 serial interface is configured in 3wire mode, the 16-bit DHR data is read out immediately
following the command for 3-wire mode enable. Figure
11 shows the 3-wire enable command (IRS[7:0] = 19h)
clocked into DI with a subsequent 16-bit read of DHR
on DO. DO remains in high impedance (three-state)
until the 3-wire enable command is received. Then DO
goes into low-impedance drive mode during the next
low cycle of CS. As SCLK is clocked 16 times, the data
in DHR is clocked out at DO. The 3-wire enable command is the command that sets the MAX1463 ready for
output on DO on the next low cycle of CS. Following the
DHR output on the low cycle of CS, the DO line returns
to high-impedance state until the next 3-wire enable
command is received. The MAX1463 can receive an
indefinite number of inputs to DI without the need for a
3-wire enable command to be received.
When the IRSD[3:0] nibble is written to the command
register (CR), i.e., when IRSA[3:0] = 1000, the nibble is
decoded and a command operation is initiated. The
command register decoding is shown in Table 41.
When the IRSD[3:0] nibble is written to the IMR, i.e.,
when IRSA[3:0] = 1001, the nibble is decoded and a
command operation is initiated. The IMR decoding is
shown in Table 42.
20
Figure 7. Current Source Mode
GPIOn_CONTROL 40h OR 41h
EDGE OR LEVEL DETECT
GPIOn
100kΩ
THREE-STATE
BUFFER
VSS
Figure 8. GPIO1 and GPIO2 Modules
Note that after power is applied and the POR function
completes, the serial interface default is the 3-wire mode
for receiving data on DI only. The DO line is a highimpedance output until the MAX1463 receives either the
4-wire or 3-wire mode command in the IMR. In the case
of a 3-wire mode command, DO switches from a highimpedance state to a driving state only for the next cycle
of CS, returning to high-impedance afterwards.
All commands, with the exception of programming or
erasing the FLASH memory, are completed within eight
internal master clock cycles of CS returning from low to
high. This is 4µs for a 4MHz oscillator frequency or
external clock input (1 internal master clock = 2 external/internal oscillator periods). FLASH memory programming and erasing require additional time of 80µs
and 4.2ms, respectively.
FLASH Memory
There are 4096 bytes of programmable/erasable FLASH
memory for CPU program instructions and coefficients
storage. In addition, there are 128 bytes of FLASH memory accessible only by the serial interface for storage of
user information data.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
CS
SCLK
IRS0
IRSA0
DI
IRS1
IRSA1
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
Figure 9. Serial Interface Data Input
CS
SCLK
DI
DO
IRS0
IRSA0
IRS1
IRSA1
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
IRS0
IRSA0
IRS1
IRSA1
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
DHR15
DHR14
DHR13
DHR12
DHR11
DHR10
DHR9
DHR8
DHR7
DHR6
DHR5
DHR4
DHR3
DHR2
DHR1
DHR0
Figure 10. 4-Wire Mode Data Read from DHR Register
These two FLASH memory locations are separated as
partitions. The program/coefficient memory is FLASH
partition 0 and the information memory is FLASH partition 1. Each partition is accessible by the serial interface for reading, erasing, and writing data.
Program/coefficient memory partition 0 is accessible by
the CPU as read only, and partition 1 is not accessible
by the CPU. The CPU cannot erase or write data to
either of the FLASH memory partitions.
FLASH partition 0 is selected during the POR cycle.
FLASH partition 1 is selected by sending the halt CPU
command (IRS[7:0]=78h) and changing the partition
selected by sending the change partition command
(IRS[7:0]=F8h). A following halt command (IRS[7:0]=78h)
resets the selected partition to partition 0.
Modifying the FLASH Contents
The MAX1463 FLASH memory contents must be erased
(contents = FFh) before the desired contents can be written. There is no individual byte-erase command, but
either a total-erase command (IRS[7:0]=E8h) where all
the selected partition is erased (4kB for partition 0 or 128
bytes for partition 1) or a page-erase command
(IRS[7:0]=D8h), where only 64 bytes are erased, and the
page is selected by PFAR[11:6]. There are 64 pages in
FLASH partition 0, and only 2 pages in FLASH partition 1.
The programming of the MAX1463 FLASH memory
must follow the procedure below (all the commands are
to be sent through the serial interface, and are hexadecimal values of IRS[7:0]):
1) Halt the CPU:
78.
2) If partition 1 is to be modified, enter the following
command:
F8
otherwise, partition 0 is selected.
3) Enable the PWRWFL bit on the power-on control
register:
13 02 01 00
D4
08
03 02 31 10
E4
08
(write 1000h to DHR[15:0])
(write Dh to PFAR[3:0])
(write DHR, 1000h to CPU port
pointed by PFAR[3:0], port D)
(write 0031h to DHR[15:0])
(write Eh to PFAR[3:0])
(write DHR, 0031h to CPU port
pointed by PFAR[3:0], port E)
(write 8000h to DHR[15:0])
(write Fh to PFAR[3:0])
(write DHR, 8000h to CPU port
pointed by PFAR[3:0], port F)
At this point, all of the MAX1463 analog modules
are off. Only the bit that enables writing to the
FLASH is enabled.
83 02 01 00
F4
08
4) For erasing the whole partition, send the following
command:
______________________________________________________________________________________
21
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
E8
otherwise, if only a page erase is required, first write
PFAR[11:6] with the page address, as:
07 X6 X5 04
(write 0XX0h to PFAR[15:0])
Note that the 2 lower bits of PFAR[7:4] should be
zero, and only the upper 2 bits of that nibble should
be set to the desired value. Then, after writing the
page address, send the page-erase command:
D8
5) Wait at least 4.2ms before sending any other command to allow the necessary time for the
erase operation to complete.
6) Write the address of the flash byte to be written to
PFAR[15:0]:
07 X6 X5 X4
(write 0XXXh to PFAR[15:0])
7) Write the contents of the byte to DHR[7:0]:
X1 X0
(write XXh to DHR[7:0], high nibble
at DHR[7:4])
8) Send the command to execute the FLASH write:
18
9) Repeat steps 6), 7), and 8) for all the bytes to be
written. It is not necessary to send the whole
address and data for every byte that is written. Only
the nibbles that are modified in the PFAR and in the
DHR from previous values must be changed. The
time interval between successive write commands
(18h) must be at least 80µs.
10) If partition 1 was selected in step 2), and the user
wants to switch back to partition 0, send the follow
ing command:
78
At this point, partition 0 is selected. The user may
want to go back to step 4) to program partition 0, or
just continue on.
11) Disable the PWRWFL bit:
03 02 01 00
(write 0000h to DHR[15:0])
D4
08
03 02 31 10
E4
08
83 02 01 00
F4
22
(write Dh to PFAR[3:0])
(write DHR, 0000h to CPU port
pointed by PFAR[3:0], port D)
(write 0031h to DHR[15:0])
(write Eh to PFAR[3:0])
(write DHR, 0031h to CPU port
pointed by PFAR[3:0], port E)
(write 8000h to DHR[15:0])
(write Fh to PFAR[3:0])
08
(write DHR, 8000h to CPU port
pointed by PFAR[3:0], port F)
Alternatively, you can send the reset command,
which also clears the PWRWFL bit:
B8
Reading the Flash Contents
The procedure to read the flash contents is no different
from reading any other information from the MAX1463.
The flash contents must be copied to the DHR and
read through the serial interface (all the commands are
hexadecimal values of IRS [7:0]):
1) If the CPU is not halted, halt the CPU:
78
2) If partition 1 is to be read, enter the following command:
F8
otherwise, partition 0 is selected.
3) Write the address of the flash byte to be read to
PFAR[15:0]:
07 X6 X5 X4
(write 0XXXh to PFAR[15:0])
4) Copy the contents of flash addressed by PFAR to
DHR:
38
5) If the interface is configured in 3-wire mode, send
19
to enable DO on the next CS cycle. Then threestate the DI driver, and send 16 SCLK pulses on
the following CS cycle, and DO outputs DHR[15:0].
The flash data is present at DHR[7:0]. See Figure
11 for details.
If the interface is configured in 4-wire mode, there
is no need to enable the DO line, as it has already
been enabled by a previous IRS command 09h.
Send the 16 SCLK pulses and retrieve the data on
the DO line.
6) Repeat steps 3), 4), and 5) for every byte to be
read. Only the nibbles that are modified in the
PFAR register are required to be sent.
Program and Coefficient Memory
The program and coefficient memory, FLASH partition 0,
is addressed by the CPU and by the serial interface
sequentially from 0000h (0 dec) to 0FFFh (4095 dec).
Program execution by the CPU always begins at address
0000h and proceeds toward 0FFFh in 1-byte increments.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
CS
SCLK
DI
DO
1
IRSA0
0
IRSA1
0
IRSA2
1
IRSA3
1
IRSD0
0
IRSD1
0
IRSD2
0
IRSD3
DHR15 DHR14 DHR13 DHR12 DHR11 DHR10
DHR9
DHR8
DHR7
DHR6
DHR5
DHR4
DHR3
DHR2
DHR1
DHR0
Figure 11. 3-Wire Mode Data Read from DHR Register
Although both the CPU and the serial interface can
address a 16-bit field, the flash size only uses 12 bits.
Therefore, the leading 4 MSBs of the address field are
ignored. It is advisable to have all leading bits of the
16-bit address in PFAR[15:0] set to zero.
The FLASH memory in partition 0 can be erased in individual 64-byte pages using the page-erase command,
or erased in bulk using the all-erase command. The
information data memory (partition 1) is unaffected by
any operation performed on partition 0.
Information Data Memory
The information data memory, FLASH partition 1, is
addressed by bytes sequentially from 00h (0) to 7Fh
(127). The addressed byte should have all leading bits of
the 16-bit address in PFAR[15:0] set to zero.
The FLASH memory in partition 1 has only two 64-byte
pages that can be erased separately using the pageerase command, or erased together using the all-erase
command. Data in partition 0 is not affected by any
operation performed on partition 1.
MAX1463 CPU Instruction Set
The MAX1463 CPU has 16 instructions used to perform
all calculations for sensor compensation, linearization,
and signal output functions. Each instruction comprises
a 4-bit op code and a 4-bit CPU register address. The
op code describes what operation to perform; the register address describes what register, or registers, to
perform the operation on.
Instruction Format
All instructions are single-byte instructions with the
exception of load data from instruction memory. LDX
fetches the 2 following bytes of instruction memory and
loads them into a register. This is how calibration and
compensation coefficients are stored within the
MAX1463. Any number of coefficients can be stored in
instruction memory. The instruction code format is as
follows:
COMMAND OP-CODE
(BITS 7–4)
Bit 7
Bit 6
Bit 5
Bit 4
REGISTER OP CODE
(BITS 3–0)
Bit 3
Bit 2
MSB
Bit 1
Bit 0
LSB
Instruction Set Details
LDX
Op-code:
Load Register X
0000 XXXXBINARY 0Xh
Operation:
X-register ← [PC+1] : [PC+2]
PC-register ← PC + 3 (point to next instruction)
CPU Cycles required:
3 cycles
Instruction:
Loads the next 2 bytes of program memory into CPU
register X. Register X can be any of the 16 CPU registers. Program counter (PC) is incremented twice during
the fetches of the next 2 bytes and incremented a third
time to point to the next instruction in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
CLX
Clear Register X
Op-code:
0001 XXXXBINARY 1Xh
Operation:
X-register ← 0000h
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Clear the contents of register X to 0000h.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
______________________________________________________________________________________
23
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
ANX
AND Register X with Register A
Op-code:
0010 XXXXBINARY 2Xh
Operation:
A-register ← A-register AND X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit logical AND operation, bit for bit, on
the contents of the A-register and the contents of the Xregister. Store the 16-bit result back into A-register. The
previous contents of A-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is not preserved.
No branching occurs.
No other registers are affected.
ORX
Op-code:
OR Register X with Register A
0011 XXXXBINARY 3Xh
Operation:
A-register ← A-register OR X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit logical OR operation, bit for bit, on the
contents of the A-register and the contents of X-register. Store the 16-bit result back into A-register. The previous contents of A-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is not preserved.
No branching occurs.
No other registers are affected.
24
ADX
ADD Register X to Register A
Op-code:
0100 XXXXBINARY 4Xh
Operation:
A-register ← A-register + X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit arithmetic addition of the A-register
and the contents of X-register. Store the low 16 bits of
the result back into A-register. Any overflow bit resulting from the addition operation is lost.
The previous contents of A-register are overwritten and
lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
STX
Op-code:
Store Register X
0101 XXXXBINARY 5Xh
Operation:
X-register ← A-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from the A-register into
the X-register. The A-register contents are unchanged.
The previous contents of X-register are overwritten and
lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
Shift Left Register X
0110 XXXXBINARY 6Xh
SRX
Shift Right Register X
Op-code: 0111 XXXXBINARY 7Xh
Operation when X ≠ 6h:
Operation
REGISTER X
REGISTER X
0
BIT : 15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
Operation when X = 6h:
11 10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
REGISTER M: R4
BIT : 15 14 13 12
11 10
9
8
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
PC-register ← PC + 1 (point to next instruction)
REGISTER R6
BIT : 15 14 13 12
BIT : 15
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit shift-left operation on the contents of
X-register. The most significant bit, bit 15, is truncated
and lost. If register X is any CPU register other than
register R6, then a zero is appended into the LSB, bit 0.
If X is CPU register R6, then the data appended into the
LSB bit 0 is copied from the MSB of register R4. The
contents of register R4 are not affected. The operation
does not preserve the two’s complement sign bit-15.
The operation is equivalent to an arithmetic multiplication by 2 on an unsigned integer value stored in register X. The result is stored back into X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is not preserved.
No branching occurs.
No other registers are affected.
CPU Cycles required:
1 cycle
Description:
Perform a 15-bit shift-right operation on the contents of
X-register, preserving the contents of the two’s complement sign bit-15 and propagating the sign bit, bit-15,
into bit-14. The least significant bit, bit 0, is truncated
and lost. The operation is equivalent to an arithmetic
division by 2. The result is stored back into X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
INX
Op-code:
Increment Register X
1000 XXXXBINARY 8Xh
Operation:
X-register ← X-register + 1
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit increment operation on the contents of
X-register. Should the increment result in an overflow,
the overflow bit is truncated and lost. The result is
stored back into X-register.
The previous contents of X-register are overwritten
and lost.
______________________________________________________________________________________
25
MAX1463
SLX
Op-code:
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
DEX
Op-code:
Decrement Register X
1001 XXXXBINARY 9Xh
Operation:
X-register ← X-register - 1
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit decrement operation on the contents
of X-register. Should the decrement result in an underflow, the underflow bit is truncated and lost. The result
is stored back into X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
NGX
Op-code:
Negate Register X
1010 XXXXBINARY AXh
Operation:
X-register ← NOT X-register
PC-register ← PC-register + 1 (point to next
instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit logical NOT operation on the contents
of X-register. Each bit is flipped to its complementary
value. The result is stored back into X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
26
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is not preserved.
No branching occurs.
No other registers are affected.
BPX
Branch If Positive Or Zero
Op-code:
1011 XXXXBINARY BXh
Operation:
If MSB(Register I) = 0 then:
PC-register ← PC-register + X-register
Else:
PC-register ← PC + 1 (point to next
instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit check of I-register for a positive (two’s
complement) or zero value and branch the number of
instructions indicated in register-X. The test operation
checks the most significant bit, bit-15, for a 0B and, if
true, adds the contents of the X-register to the program
counter register. This causes an immediate jump to the
new program memory location. The next instruction to
execute is fetched from the program memory byte
pointed to by the new contents of the PC-register.
A 1B in bit-15 of the I-register is indicative of a negative
number (two’s complement) to which the test for positive-or-zero value fails. This causes the “else” operation
to be performed and the PC register is incremented by
one pointing to the next sequential instruction in program memory to be executed. The effect bypasses the
branch mechanism and normal, sequential, code execution results.
The next instruction to execute is fetched from the program memory byte pointed to by the new contents of
the PC-register.
The previous contents of PC-register are overwritten
and lost.
Two’s complement data format is preserved.
Branching may occur.
No other registers are affected.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
PC-register ← PC-register + X-register
Else:
PC-register ← PC-register + 1 (point to
next instruction)
CPU Cycles required:
1 cycle
RDX
Read Port X
Op-code:
1101XXXXBINARY DXh
Operation:
A-register ← port-X
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from port-X to the Aregister.
Description:
The port-X contents are unchanged.
Perform a 16-bit check of the I-register for a nonzero
condition and, if true, add the contents of the X-register
to the program pointer register. This causes an immediate jump to the new program memory location. The
next instruction to execute is fetched from the program
memory byte pointed to by the new contents of the PCregister.
A 1B in any bit of the I-register is indicative of a nonzero
number to which the test for a zero value fails. This
causes the “else” operation to be performed and the
PC-register is incremented by one pointing to the next
sequential instruction in program memory to be executed. The effect bypasses the branch mechanism and
normal, sequential, code execution results.
The next instruction to execute is fetched from the program memory byte pointed to by the new contents of
the PC-register.
The previous contents of A-register are overwritten
and lost.
The previous contents of PC-register are overwritten
and lost.
Two’s complement data format is preserved.
Branching may occur.
No other registers are affected.
The port-X can be any of the CPU ports.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
WRX
Op-code:
Write Port X
1110 XXXXBINARY EXh
Operation:
Port-X ← A-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from the A-register to
port-X.
The A-register contents are unchanged.
The previous contents of port-X are overwritten
and lost.
The port-X can be any of the CPU ports.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
______________________________________________________________________________________
27
MAX1463
BNX
Branch If Not Zero
Op-code:
1100 XXXXBINARY CXh
Operation:
If I-register ≠ 0000h then:
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
MLT Multiply
Op-code:
1111 0011BINARY F3h
Operation:
A-register | M-register ← N-register x M-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
16 cycles
Description:
Perform a 16-bit by 16-bit arithmetic multiplication of
the M-register and the N-register producing a 32-bit
result. The 32-bit result is stored in two 16-bit registers;
the A-register receives the most significant word of the
result and the M-register receives the least significant
word of the result.
The A-register must be cleared to zero (CLX A) before
executing the MLT instruction.
The previous contents of A-register are overwritten
and lost.
The previous contents of M-register are overwritten
and lost.
The contents of the N-register are not altered.
The register op code must be 3h.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
Table 1. CPU Registers
ADDRESS
REF
ALT NAME
FUNCTION
0h
R0
P
Pointer Register. This register contains the address of the instruction or data in FLASH
memory to be fetched.
1h
R1
A
Accumulator Register. This register generally contains the result of any operation
involving two or more registers. It is the accumulator for the multiregister operation
result and can be used effectively to carry data from one computation to the next. The
A-register can read and write data to and from any other CPU port or register.
2h
R2
—
General-Purpose Register. This register is used to hold intermediate calculation
results, calculation coefficients, loop counter values, event counter values, comparison
limit values, etc.
3h
R3
N
Multiplicand Register. This register has a dedicated function when executing a
multiply (MLT) instruction, but can be used as a general-purpose register otherwise.
The contents of the N-register are not modified by the MLT instruction.
M
Multiplier Register. This register has a dedicated function when executing a multiply
(MLT) instruction, but can be used as a general-purpose register otherwise. The
contents of the M-register are modified by the MLT instruction. The data contents prior
to the execution of the MLT instruction are overwritten with the LSBs resulting product,
and hence lost.
4h
28
R4
5h
R5
I
Index Register. The branch not zero (BNX) and branch positive (BPX) instructions test
the index register, I, for conditions to determine if branching should occur. If the index
register tests true for the condition to branch, then the contents of register-X are added
to the pointer register, therefore executing a branch in the program.
6h–Fh
R6–RF
—
General-Purpose Registers. Used to hold intermediate calculation results, calculation
coefficients, loop counter values, event counter values, comparison limit values, etc.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
ADDRESS
REF
0h–Ch
P0–PC
Dh
Eh
Fh
FUNCTION
General-Purpose Ports These ports, P0–PC, can be used to hold intermediate calculation results,
often-used calculation coefficients, loop counter values, event counter values, comparison limit
values, etc.
PD
Module Data Port. This port is used to transfer data to and from the various functional modules in the
MAX1463. Data loaded into PD can be transferred to the data, configuration, or control register of any
of the functional modules. The data transfer is initiated using the module control port (PF). The
contents of PD are not changed during module write operations, but are overwritten by module read
operations.
PE
Module Address Port. This port is used to address a module register. A module address is loaded
into PE prior to initiating a data-transfer or control function in the module control port. All modules in
the MAX1463 are accessed through this indirect addressing method. The contents of PE are not
changed by the read or write operations to module registers. Only the lower 8 bits are used. The
upper 8 bits are not decoded.
PF
Module Control Port. This port initiates an operation on the module addressed by PE. Data can be
written to, or read from, module registers. Specific bits are assigned in the module control port to
initiate operations on the MAX1463 modules:
Bit 15 (CTRL): 1 = Initiate action defined in bit 14, 0 = no action initiated. Autoreset to zero after
operation is completed.
Bit 14 (RD/WR): 1 = read data, 0 = write data.
Bits 13–0: Not decoded.
______________________________________________________________________________________
29
MAX1463
Table 2. CPU Ports
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 3. Module Registers
MODULE
NAME
REGISTER
NAME
ADC
DOP1
DOP2
Timer
Op Amp
Power
Oscillator
ISRC
ADDRESS
DESCRIPTION
R/W
ADC_Control
00h
Initiate conversions and select ADC input.
ADC_Data_1
01h
Result of ADC conversion on channel 1 input.
R/W
ADC_Config_1A
02h
Settings for channel 1 input and conversion.
R/W
ADC_Config_1B
03h
Settings for channel 1 input and conversion.
R/W
ADC_Data_2
04h
Result of ADC conversion on channel 2 input.
ADC_Config_2A
05h
Settings for channel 2 input and conversion.
R/W
ADC_Config_2B
06h
Settings for channel 2 input and conversion.
R/W
ADC_Data_T
07h
Result of ADC conversion on temperature input.
ADC_Config_TA
08h
Settings for temperature input and conversion.
R/W
ADC_Config_TB
09h
Settings for temperature input and conversion.
R/W
DOP1_Data
10h
Input setting for the analog DAC and digital PWM outputs.
R/W
R/W
R
R
R
DOP1_Control
11h
Enable and reference selection.
DOP1_Config
12h
Select DAC or PWM output.
R/W
DOP2_Data
13h
Input setting for the analog DAC and digital PWM outputs.
R/W
DOP2_Control
14h
Enable and reference selection.
R/W
DOP2_Config
15h
Select DAC or PWM output.
R/W
TMR_Control
20h
Initiate timer.
R/W
TMR_Config
21h
Set prescaler value and timeout value.
R/W
Opamp_Config
30h
Set op amps as unity-gain buffers.
R/W
PO_Control
31h
Turn on power to modules with power-control function.
R/W
OSC_Control
32h
Trim oscillator frequency, enable clock input/output.
R/W
CS_Control
33h
Set current source output value.
R/W
GPIO1
GPIO1_Control
40h
Enable I/O, set output value, read input value.
R/W
GPIO2
GPIO2_Control
41h
Enable I/O, set output value, read input value.
R/W
Table 4. ADC Module Registers
NAME
ADC_Control
ADDRESS
00h
DESCRIPTION
Initiate conversions and set signal source.
POR VALUE
0000h
ADC_Data_1
01h
Result of ADC conversion on channel 1 input.
0000h
ADC_Config_1A
02h
Settings for channel 1 input and conversion.
0000h
ADC_Config_1B
03h
Settings for channel 1 input and conversion.
0070h
ADC_Data_2
04h
Result of ADC conversion on channel 2 input.
0000h
ADC_Config_2A
05h
Settings for channel 2 input and conversion.
0000h
ADC_Config_2B
06h
Settings for channel 2 input and conversion.
0070h
ADC_Data_T
07h
Result of ADC conversion on temperature input.
0000h
ADC_Config_TA
08h
Settings for temperature input and conversion.
0000h
ADC_Config_TB
09h
Settings for temperature input and conversion.
0070h
30
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
Table 5. ADC_Control (Address = 00h)
BITS
NAME
15–12
—
DESCRIPTION
11–8
SE[3:0]
7–3
—
2
CNVT1
1 = Initiate conversion on channel 1 using ADC settings specified in registers ADC_Config_1A and
ADC_Config_1B. The ADC result is stored in ADC_Data_1. CPU is halted during the conversion
process. This bit is automatically reset to zero when conversion is completed.
1
CNVT2
1 = Initiate conversion on channel 2 using ADC settings specified in registers ADC_Config_2A and
ADC_Config_2B. The ADC result is stored in ADC_Data_2. CPU is halted during the conversion
process. This bit is automatically reset to zero when conversion is completed.
0
CNVTT
1 = Initiate conversion on temperature sensor using ADC settings specified in registers
ADC_Config_TA and ADC_Config_TB. The ADC result is stored in ADC_Data_T. CPU is halted during
the conversion process. The bit is automatically reset to zero when conversion is completed.
Unused.
Single-ended signal source multiplexer. SE[3] = MSB.
Unused.
Table 6. Initiate Conversion (CNVT1, CNVT2, CNVTT)
RESULT
DATA_n
CNVT1
CNVT2
CNVTT
SE[3:0]
DESCRIPTION
0
0
0
XXXX
0
0
1
0000
T
Convert the temperature sensor signal using the settings in
ADC_Config_TA and ADC_CONFIG_TB, storing the result in the
ADC_Data_T register.
0
1
X
0000
2
Convert the differential signal INP2–INM2 using the settings in
ADC_Config_2A and ADC_Config_2B, storing the result in the ADC_Data_2
register.
1
X
X
0000
1
Convert the differential signal INP1–INM1 using the settings in
ADC_Config_1A and ADC_Config_1B, storing the result in the ADC_Data_1
register.
0
0
1
bbbb*
—
Not used for any setting of SE[3:0] ≠ 0000.
0
1
X
bbbb*
2
Convert the single-sided signal indicated by SE[3:0] using the settings in
ADC_Config_2A and ADC_Config_2B, if appropriate, storing the result in
the ADC_Data_2 register.
1
X
X
bbbb*
1
Convert the single-sided signal indicated by SE[3:0] using the settings in
ADC_Config_1A and ADC_Config_1B, if appropriate, storing the result in
the ADC_Data_1 register.
No measurement.
*The value bbbb is any nonzero single-ended setting.
______________________________________________________________________________________
31
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 7. Single Ended (SE[3:0])
SE[3:0]
PGA
RANGE
ADC
+INPUT
ADC
-INPUT
DESCRIPTION
0001
0.94
VBG
VSS
Bandgap voltage
0010
0.94–240
OUTnSM
VSS
Output of small op-amp n
0011
0.94–240
OUTnLG
VSS
Output of large op-amp n
0100
0.7*
VDD
VSS
Power-supply voltage
0101
0.7*
VSS
VSS
Power-supply ground
0110
0.7*
DACn_OUT using
OUTnSM
VSS
DACn output through small op-amp n configured
as unity-gain buffer
0111
0.7*
DACn_OUT using
OUTnLG
VSS
DACn output through large op-amp n configured
as unity-gain buffer
1000
0.94–240
INPn
VSS
Single-ended input on INPn
1001
0.94–240
INMn
VSS
Single-ended input on INMn
*The PGA operates at a fixed reduced gain of 0.7V/V to enable conversion of input signals at and near VDD and VSS. This gain setting is not selectable.
Table 8. ADC_Config_1A (Address = 02h)
BIT
NAME
15–11
PGA1[4:0]
10–8
CLK1[2:0]
7
—
6-4
RES1[2:0]
3
CO1[3]
2-0
CO1[2:0]
DESCRIPTION
Programmable gain amplifier setting to use during conversion of channel 1. PGA1[4] = MSB.
ADC clock setting to use during conversion of channel 1. CLK1[2] = MSB.
Unused.
ADC resolution setting to use during conversion of channel 1. RES1[2] = MSB.
Coarse-offset sign bit.
Coarse-offset DAC setting to use during conversion of channel 1. CO1[2] = MSB.
Table 9. ADC_Config_1B (Address = 03h)
BIT
NAME
15–7
—
6–4
BIAS1[2:0]
3–2
—
1–0
REF1[1:0]
DESCRIPTION
Unused.
ADC bias setting to use during conversion of channel 1. BIAS1[2] = MSB.
Unused.
Reference select for conversion on channel 1. REF1[1] = MSB.
Table 10. ADC_Config_2A (Address = 05h)
32
BIT
NAME
15–1
PGA2[4:0]
Programmable gain amplifier to use during conversion of channel 2. PGA[4] = MSB.
10–8
CLK2[2:0]
ADC clock setting to use during conversion of channel 2. CLK2[2] = MSB.
7
—
6
RES2[2:0]
3
CO2[3]
2–0
CO2[2:0]
DESCRIPTION
Unused.
ADC resolution setting to use during conversion of channel 2. RES2[2] = MSB.
Coarse-offset DAC sign bit.
Coarse-offset DAC setting to use during conversion of channel 2. CO2[2] = MSB.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
Table 11. ADC_Config_2B (Address = 06h)
BIT
NAME
15–7
—
6–4
BIAS2[2:0]
3–2
—
1–0
REF2[1:0]
DESCRIPTION
Unused.
ADC bias setting to use during conversion of channel 2. BIAS2[2] = MSB.
Unused.
Reference select for conversion on channel 2. REF2[2] = MSB.
Table 12. ADC_Config_TA (Address = 08h)
BITS
NAME
15–1
—
10–8
CLKT[2:0]
7
—
6–4
REST[2:0]
3
COT[3]
2–0
COT[2:0]
DESCRIPTION
Unused.
ADC clock setting to use during conversion of the temperature sensor. CLKT[2] = MSB.
Unused.
ADC resolution setting to use during conversion of the temperature sensor. REST[2] = MSB.
Coarse offset DAC sign bit.
Coarse offset DAC setting to use during conversion of the temperature sensor. COT[2] = MSB.
Table 13. ADC_Config_TB (Address = 09h)
BITS
NAME
15–7
—
6–4
BIAST[2:0]
3–0
—
DESCRIPTION
Unused.
ADC bias setting to use during conversion of the temperature sensor. BIAST[2] = MSB.
Unused.
Table 14. Programmable Gain Amplifier
(PGAn[4:0], where n = 1 or 2)
Table 15. ADC Clock (CLKn[2:0],
where n = 1, 2, or T; FCLK = 4MHz)
PGAn[4:0]
GAIN (V/V)
CLKn[2:0]
DIVISOR n
00000
0.94
000
4
1M
00001
7.4
001
8
500k
00010
15
010
16
250k
00011
22
011
32
125k
00100
30
100
64
62.5 k
00101
37
101
128
31.25k
00110
44
110
256
15.625k
00111
52
111
512
7.8125k
01000
60
01010
73
01100
85
01110
95
10000
105
10100
133
11000
174
11100
182
11110
240
FADC (Hz)
______________________________________________________________________________________
33
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 16. ADC Resolution (RESn[2:0],
where n = 1, 2, or T)
RESn[2:0]
RESOLUTION (BITS)
NO. OF FADC
CLOCKS PER
CONVERSION
Table 17. ADC Conversion Time
(RESn[2:0] and CLKn[2:0], where
n = 1, 2, or T)
RESOLUTION
(BITS)
CONVERSION TIME (ms)
000
9
256
001
10
320
9
CLKn[2:0] =
000
0.256
0.320
CLKn[2:0] =
100
4.096
CLKn[2:0] =
111
32.768
5.120
40.960
010
12
512
10
011
13
640
12
0.512
8.192
65.536
0.640
10.240
81.920
100
14
800
13
101
15
1280
14
0.800
12.800
102.400
110
16
2048
15
1.280
20.480
163.840
16
2.048
32.768
262.140
Table 18. Coarse-Offset DAC (3 Bits Plus
Sign, n = 1, 2, or T)
COARSE OFFSET ADDED AS % OF ADC
REFERENCE INPUT*
COn[3:0]
0111
0110
Table 19. ADC Bias Current (BIASn[2:0],
where n = 1, 2, or T)
BIASn[2:0]
FRACTION
OF FULL
BIAS
CURRENT
MAXIMUM
ADC CLOCK
FREQUENCY
(kHz)
CLKn[2:0]
PGAn =
0.94–60
PGAn =
73–105
PGAn =
133–240
00000 TO
01000
01010 TO
10000
10100 TO
11110
000
1/8
125
011
001
2/8
250
011
+135
+266
+481
010
3/8
250
010
+410
011
4/8
500
010
5/8
500
001
+116
+229
0101
+98
+193
+341
100
0100
+79
+158
+277
101
6/8
500
001
7/8
1 MHz
000
8/8
1 MHz
000
0011
+60
+117
+210
110
0010
+42
+79
+140
111
0001
+23
+44
+76
0000
+5
+9
+8
1000
+12
+23
+33
1001
-7
-15
-36
1010
-26
-50
-100
REFn[1:0]
1011
-44
-87
-169
00
VDD
1100
-64
-130
-239
01
VREF (external)
1101
-81
-166
-305
10
VBG x 4 (pseudo 5V)
1110
-100
-202
-374
1111
-117
-238
-495
Table 20. ADC Reference Voltage Source
(REFn[1:0], where n = 1 or 2)
ADC REFERENCE
*Measured at the ADC input.
34
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
Table 21. DOPn Configuration Options
DOP CONFIGURATION
PWRDAC
PWROP
SELDAC
SELPWM
ENDAC
ENPWM
BUF
DAC OFF, PWM OFF, op amp OFF.
0
0
X
X
0
0
X
DAC OFF, PWM OFF, op amp ON.
AMPnP and AMPnM routed to LG op
amp.
0
1
0
X
0
0
0
DAC OFF, PWM OFF, op amp ON.
LG op amp configured as unity-gain
buffer.
0
1
0
X
0
0
1
DAC OFF, PWM OFF, op amp ON.
AMPnP and AMPnM routed to SM op
amp.
0
1
1
X
0
0
0
DAC OFF, PWM OFF, op amp ON.
SM op amp configured as unity-gain
buffer.
0
1
1
X
0
0
1
DAC OFF, PWM ON, op amp OFF.
PWM output on OUTnSM.
0
0
0
0
0
1
X
DAC OFF, PWM ON, op amp OFF.
PWM output on OUTnLG.
0
0
0
1
0
1
X
DAC OFF, PWM ON, op amp ON.
AMPnP and AMPnM routed to LG op
amp. PWM output on OUTnSM.
0
1
0
0
0
1
0
DAC OFF, PWM ON, op amp ON.
LG op amp configured as unity-gain
buffer. PWM output on OUTnSM.
0
1
0
0
0
1
1
DAC OFF, PWM ON, op amp ON.
AMPnP and AMPnM routed to SM op
amp. PWM output on OUTnLG.
0
1
1
1
0
1
0
DAC OFF, PWM ON, op amp ON.
SM op amp configured as unity-gain
buffer. PWM output on OUTnLG.
0
1
1
1
0
1
1
DAC ON, PWM OFF, op amp OFF.
DAC output on OUTnSM.
1
0
0
X
1
0
X
DAC ON, PWM OFF, op amp OFF.
DAC output on OUTnLG.
1
0
1
X
1
0
X
DAC ON, PWM OFF, op amp ON.
DAC output on OUTnSM. AMPnP and
AMPnM routed to LG op amp.
1
1
0
X
1
0
0
______________________________________________________________________________________
35
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 21. DOPn Configuration Options (continued)
DOP CONFIGURATION
PWRDAC
PWROP
SELDAC
SELPWM
ENDAC
ENPWM
BUF
DAC ON, PWM OFF, op amp ON.
DAC output on OUTnSM. LG op amp
configured as unity-gain buffer.
1
1
0
X
1
0
1
DAC ON, PWM OFF, op amp ON.
DAC output on OUTnLG. AMPnP and
AMPnM routed to SM op amp.
1
1
1
X
1
0
0
DAC ON, PWM OFF, op amp ON.
DAC output on OUTnLG. SM op amp
configured as unity-gain buffer.
1
1
1
X
1
0
1
DAC ON, PWM ON, op amp OFF.
DAC output on OUTnSM. PWM output
on OUTnLG.
1
X
0
1
1
1
X
DAC ON, PWM ON, op amp OFF.
DAC output on OUTnLG. PWM output
on OUTnSM.
1
X
1
0
1
1
X
Table 22. DOP Module Registers
NAME
ADDRESS
DESCRIPTION
POR VALUE
DOP1_Data
10h
DAC1/PWM1 input data.
0000
DOP1_Control
11h
Initiate DAC1 and/or PWM1 conversions.
0000
DOP1_Config
12h
DAC1/PWM1 output and DAC 1 reference selection.
0000
DOP2_Data
13h
DAC2/PWM2 input data.
0000
DOP2_Control
14h
Initiate DAC2 and/or PWM2 conversions.
0000
DOP2_Config
15h
DAC2/PWM2 output and DAC 2 reference selection.
0000
OpAmp_Config
30h
Settings for op amps in DOPn modules.
0000
Table 23. DOP1_Control (Address = 11h)
36
BIT
15–5
NAME
—
4
ENPWM1
3–1
—
0
ENDAC1
DESCRIPTION
Unused.
Enable pulse-width modulator 1: 1 = PWM1 active, 0 = PWM1 inactive.
Unused.
Enable digital-to-analog converter 1: 1 = DAC1 active, 0 = DAC1 inactive.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
Table 24. DOP1_Config (Address = 12h)
BIT
NAME
15–9
—
8
SELPWM1
7–5
—
4
SELDAC1
3–1
—
0
SELREF1
DESCRIPTION
Unused.
Select PWM1 output: 1 = OUT1LG, 0 = OUT1SM.
Unused.
Select DAC1 output: 1 = OUT1LG (large op-amp buffer), 0 = OUT1SM (small op-amp buffer).
Unused.
Select voltage reference for DAC1: 0 = VDD, 1 = 2 x VREF.
Table 25. DOP2_Control (Address = 14h)
BIT
NAME
15–5
—
4
ENPWM2
3–1
—
0
ENDAC2
DESCRIPTION
Unused.
Enable pulse width modulator 2: 1 = PWM2 active, 0 = PWM2 inactive.
Unused.
Enable digital-to-analog converter 2: 1 = DAC2 active, 0 = DAC2 inactive.
Table 26. DOP2_Config (Address = 15h)
BIT
NAME
15–9
—
8
SELPWM2
7–5
—
4
SELDAC2
3–1
—
0
SELREF2
DESCRIPTION
Unused.
Select PWM2 output: 1 = OUT2LG, 0 = OUT2SM.
Unused.
Select DAC2 output: 1 = OUT2LG (large op-amp buffer), 0 = OUT2SM (small op-amp buffer).
Unused.
Select voltage reference for DAC2: 0 = VDD, 1 = 2 x VREF.
Table 27. OpAmp_Config (Address = 30h)
BIT
NAME
DESCRIPTION
15–2
—
1
BUF2
Unused.
1 = buffer mode of both large and small op amps of DOP2, 0 = normal.
0
BUF1
1 = buffer mode of both large and small op amps of DOP1, 0 = normal.
______________________________________________________________________________________
37
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 28. GPIO1_Control (Address = 40h)
BITS
NAME
15–6
—
DESCRIPTION
5
OUT1
OUT1 value is driven onto the GPIO1 pin when the output driver is enabled.
4
EN1
Enable the output driver; 1 = enabled, 0 = disabled, and OUT three-stated.
3
IN1
When EDGE1 = 0: The value input on GPIO1 is clocked into this bit (Notes 1, 2).
When EDGE1 = 1: An edge detection on GPIO1 causes a 1 to be clocked into this bit.
2
CLR1
Clear IN1 bit; 1 = clear IN1 to 0, 0 = IN1 retains its status (Note 3).
1
INV1
When EDGE1 = 0: Invert the logic value IN1; 1 = invert input, 0 = do not invert. When EDGE1 = 1: Select
edge capture type; 1 = falling edge detect; 0 = rising edge detect.
0
EDGE1
Unused.
Select level or edge detection at IN1; 1 = detect edges, 0 = detect and track logic levels.
Note 1: A pulse or level must remain on GPIOn for four periods of FOSC to be latched into IN.
Note 2: The CLRn bit must be cleared to zero to reenable GPIO to value tracking.
Note 3: The CLRn bit must be cleared to zero to reenable GPIO edge detection.
Table 29. GPIO2_Control (Address = 41h)
BITS
NAME
15–6
—
DESCRIPTION
5
OUT2
4
EN2
Enable the output driver; 1 = enabled, 0 = disabled and OUT three-stated.
3
IN2
When EDGE2 = 0: The value input on GPIO2 is clocked into this bit. (Notes 1, 2)
When EDGE2 = 1: An edge detection on GPIO2 causes a 1 to be clocked into this bit.
2
CLR2
Clear IN2 bit; 1 = clear IN2 to 0, 0 = IN2 retains its status. [3]
1
INV2
When EDGE2 = 0: Invert the logic value IN2; 1 = invert input, 0 = do not invert. When EDGE2 = 1: Select
edge capture type; 1 = falling edge detect; 0 = rising edge detect.
0
EDGE2
Unused.
OUT2 value is driven onto the GPIO2 pin when the output driver is enabled.
Select level or edge detection at IN2; 1 = detect edges, 0 = detect and track logic levels.
Note 1: A pulse or level must remain on GPIOn for four periods of FOSC to be latched into IN.
Note 2: The CLRn bit must be cleared to zero to reenable GPIO to value tracking.
Note 3: The CLRn bit must be cleared to zero to reenable GPIO edge detection.
Table 30. TMR_Control (Address = 20h)
38
BIT
NAME
DESCRIPTION
15
TMDN
Timer done bit set by the counter; 1 = timeout value reached, 0 = timeout not reached. Read-only
bit.
14
TMEN
Timer enable bit; A 1 written to TMEN resets TMDN to zero and starts counter. TMEN is reset to
zero by the counter when timeout value is reached.
13–1
—
0
ENAHALT
Unused.
Enable CPU halt; 1 = CPU halted for duration of timer interval, 0 = CPU not halted.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
MAX1463
Table 31. TMR_Config (Address = 21h)
BIT
NAME
15–12
PS[3:0]
11–0
TO[11:0]
DESCRIPTION
Prescaler setting to use during the timing interval. PS[3 ] = MSB.
Timeout value to use during the timing interval. TO[11] = MSB.
Table 32. Timer Prescaler Settings
(PS[3:0])
Table 33. Current Source_Control
(Address = 33h)
PS[3:1]
PS[0]
PRESCALER N
000
0
1
BITS
15–3
NAME
—
DESCRIPTION
Unused.
Current source setting. ISRC[2] =
MSB.
001
0
2
2–0
ISRC[2:0]
010
0
4
011
0
8
100
0
16
101
0
32
110
0
64
ISRC[2:0]
111
0
128
000
0
-167
Table 34. Current-Source Settings
(ISRC[2:0])
ISRC (µA)
000
1
3
001
001
1
6
010
-334
010
1
12
011
-501
24
100
-668
-835
011
1
100
1
48
101
101
1
96
110
-1002
111
-1169
110
1
192
111
1
384
______________________________________________________________________________________
39
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 35. Power-On Control (Address = 31h)
BITS
NAME
15–13
—
12
PWRWFL
11–9
—
DESCRIPTION
Unused.
Power for writing and erasing FLASH memory: 1 = power enabled, 0 = disabled.
Unused.
8
PWRA2D
7–6
—
Power for ADC: 1 = power enabled, 0 = disabled.
5
PWRDAC2
4
PWRDAC1
3–2
—
1
PWROP2
Power for both large and small op amps in DOP2: 1 = power enabled, 0 = disabled, op-amp
outputs are high impedance.*
0
PWROP1
Power for both LG and SM op amps in DOP1: 1 = Power enabled, 0 = disabled, op-amp outputs
are high impedance.*
Unused.
Power for DAC2 in DOP2: 1 = power enabled, 0 = disabled.
Power for DAC1 in DOP1: 1 = power enabled, 0 = disabled.
Unused.
*Whenever the DACs are enabled, the large and/or small op amps are automatically powered-up and configured as buffers, regardless of the state of the PWROPn and BUFn bits.
Table 36. Oscillator Control (Address =
32h)
BITS
15–13
12–8
NAME
—
OSC[4:0]
7–6
—
Unused.
5–4
—
Reserved 0.
3–1
—
Unused.
0
ENCKOUT
40
DESCRIPTION
Unused.
Oscillator trim setting. OSC[4] = MSB.
Enable clock output: 1 = enable
internal clock output on CKIO based
on CKSEL pin, 0 = disable.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
OSC[4:0]
BINARY
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
DECIMAL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
% CHANGE FROM NOMINAL
CLOCK FREQUENCY (%)
+43.7
+42.2
+40.1
+38.4
+35.2
+32.8
+28.8
+25.5
+17.7
+14.1
+10.0
+8.4
+5.4
+3.6
+1.4
0
-3.4
-4.9
-7.2
-9.1
-12.6
-15.1
-18.5
-21.0
-25.3
-27.2
-29.9
-32.1
-35.8
-38.1
-40.9
-43.0
Table 38. Internal Oscillator and CKIO
Control
ENCKOUT
CKSEL
(PIN)
CKIO
DESCRIPTION
Internal oscillator is
halted. An external clock
must be supplied to
CKIO pin.
X
0
Input
0
1
High
impedance
1
1
Output
Internal oscillator is
running. CKIO output
driver is disabled.
Internal oscillator is
running. CKIO output
driver is enabled driving
clock output.
______________________________________________________________________________________
41
MAX1463
Table 37. Oscillator Trim Settings
(Two’s Complement)
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 39. Module Registers Summary
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Register 00h ADC_Control
x
x
x
x
SE[3]
SE[2]
SE[1]
SE[0]
x
x
x
X
Register 01h ADC_Data_1 (for Channel Input 1, Uncompensated, and Read Only Register)
Bit 3
Bit 2
Bit 1
Bit 0
x
CNVT1
CNVT2
CNVTT
LSB
MSB
Register 02h ADC_Config_1A (for Channel 1)
x
RES1[2] RES1[1] RES1[0] CO1[3] CO1[2] CO1[1] CO1[0]
Register 03h ADC_Config_1B (for Channel 1)
x
x
x
x
x
x
x
x
x
BIAS1[2] BIAS1[1] BIAS1[0]
x
x
REF1[1] REF1[0]
Register 04h ADC_Data_2 (for Channel Input 1, Uncompensated, and Read Only Register)
PGA1[4] PGA1[3] PGA1[2] PGA1[1] PGA1[0] CLK1[2] CLK1[1] CLK1[0]
MSB
LSB
Register 05h ADC_Config_2A (for Channel 2A)
x
RES2[2] RES2[1] RES2[0] CO2[3] CO2[2] CO2[1] CO2[0]
Register 06h ADC_Config_2B (for Channel 2B)
x
x
x
x
x
x
x
x
x
BIAS2[2] BIAS2[1] BIAS2[0]
x
x
REF2[1] REF2[0]
Register 07h ADC Data_T (for Internal Temperature Input, Uncompensated, and Read Only Register)
PGA2[4] PGA2[3] PGA2[2] PGA2[1] PGA2[0] CLK2[2] CLK2[1] CLK2[0]
MSB
LSB
Register 08h ADC_Config_TA (for Internal Temperature Input TA)
x
x
x
x
x
CLKT[2] CLKT[1] CLKT[0]
x
Register 09h ADC_Config_TB (for Internal Temperature Input TB)
x
X
X
X
X
X
X
X
X
Register 10h DOP1 Data (for DAC/PWM 1)
REST[2] REST[1] REST[0] COT[3]
BIAST[2] BIAST[1] BIAST[0]
x
COT[2]
x
COT[1] COT[0]
x
MSB
x
LSB
Register 11h DOP1 Control (for DAC/PWM 1)
x
x
x
x
x
x
x
x
x
x
x
ENPWM1
x
x
x
SELPW
M1
x
x
x
SELDA
C1
x
x
x
ENDA
C1
Register 12h DOP1 Configuration (for DAC/PWM 1)
x
x
x
x
x
x
x
SELRE
F1
Register 13h DOP2 Data (for DAC/PWM 2)
MSB
LSB
Register 14h DOP2 Control (for DAC/PWM 2)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ENPWM2
x
x
x
x
x
x
x
x
x
ENDA
C2
Register 15h DOP2 Configuration (for DAC/PWM 2)
x
x
x
x
x
x
x
x
x
x
SELPW
M2
SELDA
C2
SELRE
F2
Register 20h Timer Control
TMDN
42
TMEN
x
x
x
x
______________________________________________________________________________________
ENAHA
LT
Low-Power Two-Channel Sensor
Signal Processor
Register 21h Timer Configuration
PS[3]
PS[2]
PS[1]
PS[0]
TO[11]
Register 30h OP AMP Configuration
x
x
x
x
x
Register 31h Power On Control
x
x
x
PWRW
FL
x
TO[10]
TO[9]
TO[8]
TO[7]
TO[6]
TO[5]
TO[4]
TO[3]
TO[2]
TO[1]
TO[1]
x
x
x
x
x
x
x
x
x
BUF2
BUF1
x
x
x
X
PWRD
PWRD
x
PWRO
AC1
x
PWRO
AC2
P2
P1
x
PWRA2
D
Register 32h Oscillator Control
x
x
x
OSC[4]
Register 33h Current Source Control
x
x
x
x
x
Register 40h GPIO1 Control
x
x
x
x
x
Register 41h GPIO2 Control
x
x
x
x
x
x
ENCK
OSC[1]
OSC[0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
OUT1
EN1
IN1
CLR1
INV1
EDGE1
x
x
x
x
x
OUT2
EN2
IN2
CLR2
INV2
EDGE2
OSC[3] OSC[2]
OUT
ISRC[2] ISRC[1] ISRC[0]
Table 40. Internal Register Set Address
(IRSA) Decoding
IRSA[3:0]
REGISTER
NIBBLE
ADDRESSED
0000
DHR[3:0]
Write IRSD[3:0] to DHR[3:0]
0001
DHR[7:4]
Write IRSD[3:0] to DHR[7:4]
0010
DHR[11:8]
Write IRSD[3:0] to DHR[11:8]
0011
DHR[15:12]
Write IRSD[3:0] to DHR[15:12]
0100
PFAR[3:0]
Write IRSD[3:0] to PFAR[3:0]
0101
PFAR[7:4]
Write IRSD[3:0] to PFAR[7:4]
0110
PFAR[11:8]
Write IRSD[3:0] to PFAR[11:8]
0111
PFAR[15:12]
Write IRSD[3:0] to PFAR[15:12]
1000
CR[3:0]
1001
IMR[3:0]
1010–1111
—
DESCRIPTION
Write IRSD[3:0] to CR[3:0]
Write IRSD[3:0] to IR[3:0]
Unused
______________________________________________________________________________________
43
MAX1463
Table 39. Module Registers Summary (continued)
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Table 41. Command Register (CR) Decoding
CR
DESCRIPTION
CPU HALTED
0000
Write 16-bit DHR contents into the CPU port specified by PFAR[3:0].
No [1]
0001
Write 8-bit DHR[7:0] contents into FLASH memory location specified by PFAR[11:0]. Note 2.
0010
Read 16-bit CPU port specified by PFAR[3:0] into DHR.
0011
Read 8-bit FLASH location specified by PFAR[11:0] into DHR[7:0].
Yes
0100
Read 16-bit CPU accumulator register (A) into DHR.
Yes
0101
Read 8-bit FLASH location specified by the CPU program counter (PC) (CPU instruction or data) to
DHR[7:0].
Yes
0110
Read 16-bit CPU PC to DHR.
Yes
0111
Halt the CPU.
No
1000
Start the CPU, i.e., clear the HALT CPU bit from the current PC location.
Yes
1001
Single step the CPU. Only one CPU clock cycle is executed.
Yes
1010
Reset the PC to zero.
Yes
1011
Reset the modules, flash controller, and CPU registers D, E, F.
Yes
1100
No operation.
1101
Erase a 64-byte “page” of FLASH as specified by PFAR[11:6].
Yes
1110
Erase the entire FLASH partition (4kB, PS0, or 128 bytes, PS1).
Yes
1111
Change from FLASH partition PS0 to FLASH partition PS1 (128 byte auxiliary). A subsequent halt
CPU command resets the partition selection back to PS0.
Yes
Yes
No [1]
—
Note 1: Reading and writing the CPU ports by the serial interface is allowed while the CPU is executing its program. In the case of
simultaneous access of the ports by both the CPU and the serial interface, the CPU has priority. Although this procedure is
allowed, it is not recommended, as the serial interface may change values previously written by the CPU. If a “snapshot” of
the ports and module register contents is required while the CPU is running, halt the CPU, read the contents of the ports
and/or module registers, and restore the original port/module register values prior to starting the CPU again.
Note 2: The PWRWFL bit in the power-on control register (31h) must be enabled for a write operation to occur. See the FLASH
Memory section for further details on writing the FLASH memory.
Table 42. Interface Mode Register (IMR)
Decoding
IRSD
0000
Place the MAX1463 into a 4-wire serial
interface (DI cannot be tied to DO).
0001
Place the MAX1463 into a 3-wire serial
interface (DI can be externally tied to DO).
0010–1111
44
DESCRIPTION
Unused.
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
OP CODE (HEX)
MNEMONIC
0X
LDX
OPERATION
Load register X from program memory
TWO’S
COMP
NO. OF
REGISTERS
INVOLVED
NO. OF
CYCLES
NO. OF
BYTES
Y
1
3
3
1X
CLX
Clear X-reg
Y
1
1
1
2X
ANX
A-reg = A-reg AND X-reg
N
2
1
1
3X
ORX
A-reg = A-reg OR X-reg
N
2
1
1
4X
ADX
A-reg = A-reg ADD X-reg
Y
2
1
1
5X
STX
X-reg = A-reg
Y
2
1
1
6X
SLX
Shift left X-reg
N
1 or 2
1
1
7X
SRX
Shift right X-reg propagating sign bit
Y
1
1
1
8X
INX
X-reg = X-reg + 1
Y
1
1
1
9X
DEX
X-reg = X-reg - 1
Y
1
1
1
AX
NGX
X-reg = NOT X-reg
N
1
1
1
BX
BPX
Branch positive I-reg by amount in X-reg
Y
2
1
1
CX
BNX
Branch not zero I-reg by amount in X-reg
Y
2
1
1
DX
RDX
A-reg = CPU port-X
Y
1
1
1
EX
WRX
CPU port-X = A-reg
Y
1
1
1
F3
MLT
A-reg | M-reg = M-reg multiplied by Nreg; register op code must be 3h.
Y
3
16
1
______________________________________________________________________________________
45
MAX1463
Table 43. Instruction Set
Low-Power Two-Channel Sensor
Signal Processor
CS
DO
DI
SCLK
MAX1463
Functional Diagram
VDD
ISRC
SERIAL
INTERFACE
VDD
ISRC
INP1
CO
DAC
INM1
4kB
FLASH
MEMORY
16-BIT CPU
POWERON
RESET
VDDF
VSS
INP2
Σ
MUX
PGA
ADC
CKIO
INM2
CKSEL
DIGITAL
I/O
TEMP
SENSOR
GPIO2
DAC
2
PWM
2
GPIO1
EXTERNAL
REFERENCE
INPUT
VREF
BANDGAP
REFERENCE
OUTPUT
VBG
OUT2SM
SM
AMP2M
LG
AMP2P
OUT1SM
SM
AMP1M
OUT1LG
AMP1P
LG
PWM
1
OUT2LG
DAC
1
Chip Information
TRANSISTOR COUNT: 70,921 (not including flash)
PROCESS: CMOS
SUBSTRATE CONNECTED TO: VSS
46
______________________________________________________________________________________
INM2
INP2
INM1
INP1
VSS
TEMPERATURE
SENSOR
ISRC
M
U
X
M
U
X
VDD
VSS
DACnOUT VIA OUTnSM
DACnOUT VIA OUTnLG
INPn
INMn
5
6
7
8
9
OUTnLG
3
4
OUTnSM
2
SINGLE ENDED
VBG
1
NO.
Σ
VSS
REF
ISRC MODULE
ISRC_CONTROL
CO
DAC
ISRC
33h
PGA
ADC
VBG
ADC_CONFIG_2B
06h
09h
08h
ADC MODULE
ADC_CONFIG_TB
ADC_CONFIG_TA
ADC_DATA_T
ADC_CONFIG_2A
05h
07h
ADC_DATA_2
ADC_CONFIG_1B
ADC_CONFIG_1A
ADC_DATA_1
ADC_CONTROL
04h
03h
02h
01h
00h
VDD
VREF
VBG x 4
CPU
CS
DO
DI
SCLK
CPU PORTS
RF
PF
÷2
FLASH MEMORY
(4kB)
4MHz OUT
OSCILLATOR
FLASH DATA
ADDRESS
ENCKOUT
OSC_CONTROL
INSTRUCTION
CPU REGISTERS
MCLK
32h
RD
RE
RC
RB
RA
PC
PD
PE
PB
PA
R9
P8
P6
P7
R7
P5
R8
R6
INDEX (I)
R5
R3 MULTIPLICAND (N)
P1
R4 MULTIPLIER (M)
R2
P2
P4
R1 ACCUMULATOR (A)
P1
P3
R0
P0
POINTER (P)
SERIAL INTERFACE
EN
VDD
EXTERNAL
REFERENCE
INPUT
BANDGAP
REFERENCE
POWER-ON
RESET
CKIO
CKSEL
VREF
VBG
VSS
VDDF
VDD
Detailed Block Diagram
______________________________________________________________________________________
47
MAX1463
VDD
Low-Power Two-Channel Sensor
Signal Processor
48
OUT2LG
AMP2P
AMP2M
OUT2SM
OUT1LG
AMP1P
AMP1M
OUT1SM
SW11
SW10
SW11
SW10
SW5
SW0
SW5
SW0
LG2
SM2
LG1
SM1
SW6
SW1
SW6
SW1
SW7
SW2
SW7
SW2
SW9
SW8
SW4
SW3
SW9
SW8
SW4
SW3
REF
PWM2
DAC2
REF
PWM1
DAC1
DOP2 MODULE
OPAMP_CONFIG
DOP2_CONFIG
15h
30h
DOP2_CONTROL
DOP2_DATA
DOP1 MODULE
OPAMP_CONFIG
14h
13h
VREF X 2
VDD
30h
DOP1_CONFIG
12h
DOP1_DATA
DOP1_CONTROL
11h
10h
VREF X 2
VDD
TMR_CONFIG
TMR_CONTROL
GPION_CONTROL
GPION_CONTROL
21h
20h
THREE-STATE
BUFFER
EDGE OR LEVEL DETECT
41h
THREE-STATE
BUFFER
EDGE OR LEVEL DETECT
40h
PRESCALER
TIME OUT VALUE
12-BIT COUNTER
VSS
VSS
100kΩ
100kΩ
MCLK
GPIO2
GPIO1
MAX1463
Low-Power Two-Channel Sensor
Signal Processor
Detailed Block Diagram (continued)
______________________________________________________________________________________
Low-Power Two-Channel Sensor
Signal Processor
SSOP.EPS
2
1
INCHES
E
H
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008
0.05
0.21
B
0.010
0.015
0.25
0.38
C
D
0.20
0.09
0.004 0.008
SEE VARIATIONS
E
0.205
e
0.212
0.0256 BSC
5.20
MILLIMETERS
INCHES
D
D
D
D
D
5.38
MIN
MAX
MIN
MAX
0.239
0.239
0.278
0.249
0.249
0.289
6.07
6.07
7.07
6.33
6.33
7.33
0.317
0.397
0.328
0.407
8.07
10.07
8.33
10.33
N
14L
16L
20L
24L
28L
0.65 BSC
H
0.301
0.311
7.65
7.90
L
0.025
0∞
0.037
8∞
0.63
0∞
0.95
8∞
N
A
C
B
e
L
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
21-0056
REV.
C
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1463
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)