ETC BI2009

2 Channel Digital Amplifier
BI2009
Data Sheet
Rev.1.5, 2005.06.06
Biforst Technology Inc.
BI2009
_____________
2ch Digital Amplifier
2 Channel Digital Amplifier
BI2009
GENERAL DESCRIPTION
The BI2009 is a 2 channel stereo pure digital amplifier including Sample Rate Converter,
2-channel Speaker Driver and 2-channel Earphone Driver in 48-pin LQFP package. The BI2009 can
provide the 3 or 4-wire type earphone connection selection and 12V Speaker Driver (BD7001)
Interface. It can also support popular formats such as I2S, Left-Justified & Right-Justified formats. The
powerful Audio Volume Control includes power-on Initial volume function, 32-Level Audio Volume
Control and Mute Control. It also provides Volume Level Boost and Output Anti-Clipping function.
FEATURE
Operation Voltage:
Digital Part:3.0 ~ 3.6V
Speaker Driver:3.0 ~ 5.5V
Operation Frequency:
Accept 256xFS or 45.1584 ~ 49.152MHz For Operation
Provide On-Chip OSC Circuit For 45.1584 ~ 49.152MHz Crystal Connect
Audio Data Input Interface:
When Use Internal SRC with 49.152MHz for Operation Frequency, Accept 29 ~ 96KHz
Wide Continue Sample Rate Range
When Use External 256xFS Clock Source, Accept below 96KHz Sample Rate
Support I2S, Left-Justified & Right-Justified Format
Auto Adapt Word Length For Left & Right Channel In I2S & Left-Justified Mode
Provide 16/18/20/24 Word Length Select For Left & Right Channel In Right-Justified
Mode
Provide Left/Right Frame Select Exchange Function
Provide Serial Clock Positive or Negative Edge Latch Data Select
Provide Audio Data Input Interface In Master/Slaver Mode
Audio Volume Control:
Provide 32 Level Volume Select
Set Power-On Initial Volume Value Through External Pin ( 0/9/16/31 )
Adjust Speaker & Earphone Output Volume Through Two External Pins
Provide Volume Level Boost & Output Anti-Clipping Function Enable/Disable For Play
DVD Movie
Mute Control:
Set Mute Enable/Disable Through External Pin
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Page 2 of 19
BI2009
_____________
2ch Digital Amplifier
Provide Mute Enable LED Indication Output Pin
Speaker Driver:
Embedded 2-Channel Speaker Driver (1W @5V Per Channel)
Embedded 2-Channel Earphone Driver
Switch Speaker Driver or Earphone Driver Output Through One External Pin
Provide 3 or 4-Wire Type Earphone Connection Select
Provide 12V Speaker Driver Interface
Package Type
LQFP 48 Pin (7x7x1.4mm)
ABSOLUTE MAXIMUM RATINGS (Note 1)
SYMBOL
PARAMETER
VALUE
UNIT
VDDA
Speaker Driver Power Supply Voltage
-0.3 to 5.5
V
VDD
Digital Amplifier Kernel Power Supply Voltage
-0.3 to 3.6
V
VIN
Input Signal Voltage
-0.3 to VDD +0.3
V
Ta
Operating Temperature
-40 ~ +85
℃
Tst
Storage Temperature
-40 ~ +150
℃
Note 1: Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
VDDA
Speaker Driver Supply Voltage
3.0
VDD
Digital Part Power Supply Voltage
3.0
VIH
Input High Voltage
2.5
VIL
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
Ta
Operating Temperature
TYP
3.3
MAX
UNIT
5.5
V
3.6
V
V
0.5
VDD-0.5
V
V
-40
0.6
V
85
℃
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Ta=25℃, VDDA =5V, VDD=3.3V)
SPECIFICATION
SYMBOL
PARAMETER
TEST CONDITIONS
PSRR
Power supply rejection ratio
P VDDA =4.5V to 5.5V
|IIH|
High-level input current
P VDDA =3.3V, VI =P VDDA
1
uA
|IIL|
Low -level input current
P VDDA =3.3V, VI =0V
1
uA
IPWDN
Power Down Current
1
uA
Sysclk halt
MIN
TYP
MAX
-70
UNIT
dB
Audio output disable
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Page 3 of 19
BI2009
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2ch Digital Amplifier
OPERATING CHARACTERISTICS (Ta=25℃, VDDA =5V, VDD=3.3V, RL=8Ω; unless otherwise
specified)
SYMBOL
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
IDDA
DC Operating Current
VR or VL
320
mA
IDD
DC Operating Current
2
mA
PO
Output Power
THD = 1%, RL=4Ω
1.0
W
THD+N
Total Harmonic Distortion
PO = 1W
I2S input active
1%
plus Noise
kSVR
Supply ripple rejection ratio
SNR
Signal-to Noise Ratio
VR or VL
-71
dB
80
dB
20
μvRms
Po = 0.6 W / one channel
Vn
Noise output voltage
TYPICAL CHARACTERISTICS
EFFICIENCY vs
SUPPLY CURRENT vs
FREE-AIR TEMPERATURE
OUTPUT POWER
90
12
Ferrite Bead Filter
80
10
No Filter
IDD-Supply Current-mA
Efficiency -%
70
LC Filter
60
50
40
Class-AB
30
RL=8Ω ,Multimedia Speaker
20
vDD
=5V
0
0.2
0.4
6
4
2
10
0
8
0.6
0.8
PO-OutPower-W
1.0
1.2
1.4
0
-50
0
50
100
150
TA –Free-Air Temperature- ℃
200
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Page 4 of 19
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THD+N-Total Harmonic Distortion+Noise-%
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
2ch Digital Amplifier
TOTAL HARMONIC DISTORTION+NOISE
vs
OUTPUT POWER
THD+N-Total Harmonic Distortion+Noise-%
BI2009
10
10
5
f=20kHz
5
PO=0.5W
2
f=1kHz
2
1
1
0.5
0.5
f=20Hz
0.2
0.2
0.1
0.1
VDD=5V,
0.05
0.05
VDD=5V,
RL=8Ω
RL=8Ω
0.02
0.02
0.01
20
50
100 200
500
1K
2K
5K
10K 20K
0.01
10m
20m
50m
100m
200m
500m
1
2
PO-OutPower-W
f-Frequency-Hz
FREQUENCY
CHARACTERISTICS
[VDD=5.0V]
CROSSTALK
9
0
6
-10
3
-20
0
-30
RL=8Ω,
Class-D Crosstalk-dB
Gain-dB
VDD=5V,
-3
-6
-9
LO=10µH,
-12
CO=1µF,
-15
VDD=5V,
-18
RL=4Ω
PO=1W
-40
-50
-60
L to R
-70
-80
-90
R to L
-100
-21
50
100
1k
5k
f-Frequency-Hz
10k
50k
100k
50
100
500
1k
5k
10k 20k
f-Frequency-Hz
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Page 5 of 19
BI2009
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2ch Digital Amplifier
PIN ASSIGNMENTS, PIN LIST & DESCRIPTION
FSYNC_POL
SCLK_POL
VDD
VSS
MODE_SEL_1
MODE_SEL_0
WORD_SEL_1
CHANNEL_SEL
EAR_R_OUT_P
EAR_R_OUT_N
EAR_L_OUT_P
EAR_L_OUT_N
36
35
34
33
32
31
30
29
28
27
26
25
Pin Assignment
ERF
37
24
E_VSSA
FSYNC_IN/FSYNC_OUT
38
23
VR_N
SCLK_IN/SCLK_OUT
39
22
VR_P
SDATA_IN
40
21
E_VDDA
RESET_B
41
20
E_VDDA
SRC_EN_B
42
19
VL_P
VDD
43
18
VL_N
VSS
44
17
E_VSSA
XIN
45
16
PWM_OUTSEL
XOUT
46
15
PWM_SYNC_CLK/OSC_CLK_OUT
EXT_CLK_EN
47
14
MUTE_LED
TEST_EN
48
13
VOL_VALUE_SEL_1
7
8
9
VDD
VSS
VOL_VALUE_SEL_0
12
6
WORD_SEL_0
SPEAKER_SEL
5
DVD_VOL_EN_B
11
4
CLIP_EN_B
CHANNEL_REV_EN
3
MUTE
10
2
MASTER_EN_B
1
VOL_INC
VOL_DEC
2 Channel Digital Amplifier
BI2009
(LQFP 48 Pin, 7 x 7 x 1.4mm)
Pin List & Description
Pin No.
Pin
1
VOL_INC
2
VOL_DEC
3
MUTE
4
5
6
CLIP_EN_B
DVD_VOL_EN_B
WORD_SEL_0
I/O Pad Function
Type
Input
Audio Volume Increase Input
(3.3V)
Low Level Trigger Active
Input
(3.3V)
Input
(3.3V)
Input
(3.3V)
Input
(3.3V)
Input
(3.3V)
Audio Volume Decrease Input
Low Level Trigger Active
Mute Trigger Signal Input
Low Level Trigger Active
Speaker Output Anti-Clipping Enable
0 : Internal Speaker Output Anti-Clipping Enable
1 : Internal Speaker Output Anti-Clipping Disable
Speaker Output Volume Double Enable
0 : Double Volume Value Output Select (Loud than DVD_VOL_EN = 0)
1 : Normal Volume Value Output Select
Serial Audio Data Input Length Select (For Right-Justified Mode Only)
(WORD_SEL_1, WORD_SEL_0) = 00 : 24-bits
(WORD_SEL_1, WORD_SEL_0) = 01 : 20-bits
(WORD_SEL_1, WORD_SEL_0) = 10 : 18-bits
(WORD_SEL_1, WORD_SEL_0) = 11 : 16-bits
7
VDD
Power 3.3V Power Input
8
VSS
Power 3.3V Ground Input
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Page 6 of 19
BI2009
Pin No.
Pin
_____________
2ch Digital Amplifier
I/O Pad Function
Type
Initial Volume Value Select
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 00 : Volume 31
9
VOL_VALUE_SEL_0
Input
(3.3V)
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 01 : Volume 16
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 10 : Volume 9
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 11 : Volume 0
Digital Amplifier Receive Serial Audio Data in Master or Slave Mode
10
MASTER_EN_B
Input
(3.3V)
0 : In Master Mode, Pin 38 Switch to FSYNC_OUT function, & Pin 39
Switch to SCLK_OUT function
1 : In Slave Mode, Pin 38 Switch to FSYNC_IN function, & Pin 39 Switch
to SCLK_IN function
Speaker Driver or Earphone Driver Output Enable Select
(CHANNEL_REV_EN, CHANNEL_SEL) = 00 :
VL_P/N, VR_P/N Output Enable
11
CHANNEL_REV_EN
Input
(3.3V)
(CHANNEL_REV_EN, CHANNEL_SEL) = 01 :
EAR_L_OUT_P/N, EAR_R_OUT_P/N Output Enable
(CHANNEL_REV_EN, CHANNEL_SEL) = 10 :
EAR_L_OUT_P/N, EAR_R_OUT_P/N Output Enable
(CHANNEL_REV_EN, CHANNEL_SEL) = 11 :
12
SPEAKER_SEL
Input
(3.3V)
VL_P/N, VR_P/N Output Enable
Earphone Type Select
0 : 4 Wire Earphone Mode Select
1 : 3 Wire Earphone Mode Select
Initial Volume Value Select
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 00 : Volume 31
13
VOL_VALUE_SEL_1
Input
(3.3V)
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 01 : Volume 16
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 10 : Volume 9
(VOL_VALUE_SEL_1, VOL_VALUE_SEL_0) = 11 : Volume 0
14
15
MUTE_LED
PWM_SYNC_CLK
/OSC_CLK_OUT
Output
(3.3V)
Mute LED Indication Output
0 : Mute Disable
1 : Mute Enable
Output When TEST_EN = 0, Output System Clock for 12V Driver
(3.3V) When TEST_EN = 1, Internal Crystal OSC Clock Output Probe Point
Output
Driver Enable Signal for 12V Driver
16
PWM_OUT_SEL
17
E_VSSA
Power Speaker & Earphone Driver Ground Input
18
VL_N
Output Left Channel Negative PWM Signal Output
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
19
VL_P
Output Left Channel Positive PWM Signal Output
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
20 ~ 21 E_VDDA
(3.3V)
Power Speaker & Earphone Driver 3.3 ~ 5.0V Power Input
22
VR_P
Output Right Channel Positive PWM Signal Output
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
23
VR_N
Output Right Channel Negative PWM Signal Output
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
24
E_VSSA
Power Speaker & Earphone Driver Ground Input
25
EAR_L_OUT_N
Output Left Channel Negative PWM Signal Output for Earphone or 12V Driver
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
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Page 7 of 19
BI2009
Pin No.
Pin
_____________
2ch Digital Amplifier
I/O Pad Function
Type
26
EAR_L_OUT_P
Output Left Channel Positive PWM Signal Output for Earphone or 12V Driver
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
27
EAR_R_OUT_N
Output Right Channel Negative PWM Signal Output for Earphone or 12V Driver
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
28
EAR_R_OUT_P
Output Right Channel Positive PWM Signal Output for Earphone or 12V Driver
(Output Voltage Level Dependent On E_VDDA)
(5.0V)
Speaker Driver or Earphone Driver Output Enable Select
(CHANNEL_REV_EN, CHANNEL_SEL) = 00 :
VL_P/N, VR_P/N Output Enable
29
CHANNEL_SEL
Input
(3.3V)
(CHANNEL_REV_EN, CHANNEL_SEL) = 01 :
EAR_L_OUT_P/N, EAR_R_OUT_P/N Output Enable
(CHANNEL_REV_EN, CHANNEL_SEL) = 10 :
EAR_L_OUT_P/N, EAR_R_OUT_P/N Output Enable
(CHANNEL_REV_EN, CHANNEL_SEL) = 11 :
VL_P/N, VR_P/N Output Enable
Serial Audio Data Input Length Select (For Right-Justified Mode Only)
30
WORD_SEL_1
Input
(3.3V)
(WORD_SEL_1, WORD_SEL_0) = 00 : 24-bits
(WORD_SEL_1, WORD_SEL_0) = 01 : 20-bits
(WORD_SEL_1, WORD_SEL_0) = 10 : 18-bits
(WORD_SEL_1, WORD_SEL_0) = 11 : 16-bits
Serial Audio Data Input Format Select
31
MODE_SEL_0
Input
(3.3V)
32
MODE_SEL_1
(MODE_SEL_1, MODE_SEL_0) = 00 : I2S Format Mode Select
(MODE_SEL_1, MODE_SEL_0) = 01 : I2S Format Mode Select
(MODE_SEL_1, MODE_SEL_0) = 10 : Left-Justified Mode Select
(MODE_SEL_1, MODE_SEL_0) = 11 : Right-Justified Mode Select
33
VSS
Power 3.3V Ground Input
34
VDD
35
SCLK_POL
36
FSYNC_POL
37
ERF
Power 3.3V Power Input
Serial Audio Data Signal “SCLK_IN” Polarity Select
Input
0 : Serial Clock Negative Edge Latch Data
(3.3V)
1 : Serial Clock Positive Edge Latch Data
Serial Audio Data Signal “FSYNC_IN” Left/Right Frame Select
Input
0 : Low Level = Right Channel, High Level = Left Channel
(3.3V)
1 : Low Level = Left Channel, High Level = Right Channel
Digital Amplifier Error Flag Input
Input
ERF = 0 : Enable Digital Amplifier
(3.3V)
ERF = 1 : Disable Digital Amplifier
Serial
Audio Data Left/Right Frame Input/Output
Input/
♦
MASTER_EN_B = 1, Serial Audio Data Left/Right Frame Input
Output
♦ MASTER_EN_B = 0, Serial Audio Data Left/Right Frame Output
(3.3V)
38
39
FSYNC_IN/
FSYNC_OUT
SCLK_IN /
SCLK_OUT
40
SDATA_IN
41
RESET_B
Input/ Serial Audio Data Latch Clock Input/Output
♦ MASTER_EN_B = 1, Serial Audio Data Latch Clock Input
Output
♦ MASTER_EN_B = 0, Serial Audio Data Latch Clock Output
(3.3V)
Input
(3.3V)
Input
(3.3V)
Serial Audio Data Input
Reset Signal Input
0 : Reset Active (Must Maintain Low Level Great than 1ms)
1 : Normal Operation
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Page 8 of 19
BI2009
Pin No.
42
_____________
Pin
I/O Pad Function
Type
Input
SRC_EN_B
(3.3V)
2ch Digital Amplifier
Internal SRC Circuit Enable
0 : SRC Enable
1 : SRC Disable
43
VDD
Power 3.3V Power Input
44
VSS
45
XIN
Power 3.3V Ground Input
External Clock Input Path or Crystal Connect Point
Input
♦ EXT_CLK_EN = 0, 49.152MHz Crystal OSC Input Path
♦ EXT_CLK_EN = 1, External 49.152MHz or 256xFS Clock Input
(3.3V)
Path
46
XOUT
47
EXT_CLK_EN
Output 49.152MHz Crystal OSC Output Path
External Clock Input Enable
Input
0 : Internal Crystal OSC Enable to coporate external crystal
1 : Use 49.152MHz or 256xFS Clock to XIN Pin
Test Mode Enable
48
TEST_EN
Input
0 : Test Mode Disable
1 : Test Mode Enable
Function Description
Operation Clock Select
BI2009 requires a clock for internal circuit operation. There are two types of clocks can be
accepted. One is external input of 256xFS and the other is generated by BI2009 itself by connecting a
Crystal of 45.1584 ~ 49.152MHz.
The use and detail description is illustrated as below.
256xFS –256xFS clock is used when the system can provide the clock and this clock can
syncronally generate the input audio data. To use the clock, the external pin of BI2009
“SRC_EN_B” is set to HIGH and “EXT_CLK_EN” set to HIGH. The BI2009 will disable the
internal SRC (Sample Rate Converter) and input 256xFS clock to “XIN” for BI2009’s
operation. The setting of “SRC_EN_B” is as Table 1 and “EXT_CLK_EN” as Table 2.
(*The FS is the Sample Rate of Input Audio Data. For example, FS is 44.1KHz and 256xFS is
11.2896MHz. Table 4 lists the Operation Clock most frequently used)
Table 1. SRC_EN_B Configuration
SRC_EN_B
SRC Circuit Enable
0
SRC Enable
1
SRC Disable
Table 2. EXT_CLK_EN Configuration
EXT_CLK_EN
OSC External Clock Input Enable
0
OSC Enable
1
External Clock Input Enable
(Clock Input Through XIN Pin)
_________________________________________________________________________________________________
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Page 9 of 19
BI2009
_____________
2ch Digital Amplifier
Table 3. General BI2009 Operation Clock (256xFS) List
FS (Sample Rate)
BI2009 Operation Clock :
256xFS
32K
8.192MHz
44.1K
11.2896MHz
48K
12.288MHz
88.2K
22.5792MHz
96K
24.576MHz
Crystal – When system cannot provide 256xFS Clock to BI2009, “SRC_EN_B” must be set
to LOW and “EXT_CLK_EN” set to LOW. The BI2009 is required to connect a Crystal of
45.1584 ~ 49.152MHz, so BI2009 can generate internal clock. 49.152MHz is highly
recommended. Only directly input Audio Data to BI2009, BI2009 will automatically judge and
adjust the best condition for operation according to the input Audio Data.
Digital Audio Data Input Format Select
BI2009 is to drive speaker just by inputting the Digital Audio Data. It supports the PCM Format
from CD player, DVD decoded chip or DSP decoder such as Portable MP3 Player.
BI2009 provides two options for Master or Slaver receiving modes. The setting is through the
external pin of MASTER_EN_B. When MASTER_EN_B is set to LOW, BI2009 is in Master Mode. Pin
15 “PWM_SYNC_CLK” will be the output of Master Clock, Pin 38 “FSYNC_OUT” will be the output of
Serial Audio Data Left/Right Frame and Pin 39 “SCLK_OUT” will be the output of Serial Data Clock.
When MASTER_EN_B is set to HIGH, BI2009 is in Slaver Mode. Pin 38 “FSYNC_OUT” will be the
input of Serial Audio Data Left/Right Frame and Pin 39 “SCLK_OUT” will be the input of Serial Data
Clock. Table 4 lists the setup of MASTER_EN_B.
Table 4. Master or Slaver Mode Select
MASTER_EN_B
Pin Name
Pin Direction
1
Pin 38, FSYNC_IN
Input
1
Pin 39, SCLK_IN
Input
0
Pin 38, FSYNC_OUT
Output
0
Pin 39, SCLK_OUT
Output
BI2009 can receive Digital Audio Data input format by setting the external pins of MODE_SEL_1,
MODE_SEL_0, FSYNC_POL, SCLK_POL, WORD_SEL_1 and WORD_SEL_0. MODE_SEL_1 and
MODE_SEL_0 are to set MSB starting position of Digital Audio Data. BI2009 supports I2S,
Left-Justified and Right-Justified. Table 5 illustrates the setup list. FSYNC_POL is to adjust Serial
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Page 10 of 19
BI2009
_____________
2ch Digital Amplifier
Audio Data Left/Right Frame and SCLK_POL is to select Audio Data Signal “SCLK_IN” Polarity. Table
6 and Table 7 are the lists.
Figure 1 illustrates how the actual receiving data format relates to the pin setup. While in
Left-Justified Mode, each Audio Data’s MSB position is left aligned to Rising/Falling of
FSYNC_IN/FSYNC_OUT signal. While in Right-Justified Mode, each Audio Data’s LSB position is
right aligned to Rising/Falling of FSYNC_IN/FSYNC_OUT signal. Compared to Left-Justified Mode,
one Clock Cycle shift of SCLK_IN is occurred for each Audio Data’s MSB position under I2S Mode.
When BI2009 is set to I2S and Left-Justified Modes, BI2009 can automatically catch the data
following the signal change of FSYNC_IN/ FSYNC_OUT and SCLK_IN/SCLK_OUT. However, when
BI2009 is set to Right-Justified Mode, it is required to setup the word length of the input data format.
WORD_SEL_0 and WORD_SEL_1 are to set the audio data word length. BI2009 can accept 4 types
of length in 24/20/18/16-bits. Table 8 lists the setup. While the word length setting is greater than
actual input data word length, BI2009 will automatically stop receiving the data internally.
Table 5. Digital Audio Data Input Format Select
MODE_SEL_1
MODE_SEL_0
Audio Data Input Select
0
0
0
1
1
0
Left-Justified Audio Data Format Input
1
1
Right-Justified Audio Data Format Input
I2S Audio Data Format Input
Table 6. Digital Audio Data Left/Right Frame Select
FSYNC_POL
Digital Audio Data Left/Right Frame Select
0
FSYNC_IN = 1 : Left Channel / FSYNC_IN = 0 : Right
Channel
1
FSYNC_IN = 1 : Right Channel / FSYNC_IN = 0 : Left
Channel
Table 7. Digital Audio Data Latch Clock Select
SCLK_POL
Digital Audio Data Latch Clock Select
0
Falling Edge Latch Audio Data
1
Rising Edge Latch Audio Data
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Page 11 of 19
BI2009
_____________
2ch Digital Amplifier
Table 8. Serial Audio Data Input Length Select (Right-Justified Mode Only)
Serial Audio Data Input
Length Select
WORD_SEL_1 WORD_SEL_0
0
0
24-bits
0
1
20-bits
1
0
18-bits
1
1
16-bits
FSYNC_IN/
FSYNC_OUT
Left Channel
Right Channel
Left Channel
Right Channel
(FSYNC_POL = 0)
FSYNC_IN/
FSYNC_OUT
(FSYNC_POL = 1)
SCLK_IN/
SCLK_OUT
(SCLK_POL = 0)
SCLK_IN/
SCLK_OUT
(SCLK_POL = 1)
MSB
SDATA_IN
(I2S)
MSB
SDATA_IN
SDATA_IN
MSB
Left Channel Audio Data
(Left-Justified)
(Right-Justified)
LSB
Right Channel Audio Data
LSB
MSB
Left Channel Audio Data
LSB
MSB
LSB
LSB
MSB
Right Channel Audio Data
LSB
Left Channel 16/18/20/24 Data Length
MSB
LSB
Right Channel 16/18/20/24 Data Length
Figure 1. Digital Audio Data Input Format
Speaker & Earphone Driver
BI2009 provides two ways of connecting speakers and earphone. The first one is when the
external pin of CHANNEL_REV_ EN set to LOW; BI2009 will connect speakers and earphone using
the embedded drivers as Figure 2. The second one is when the external pin of CHANNEL_REV_ EN
set to HIGH, BI2009 will connect a 12V Speaker Driver (BD7001) using the original earphone
connection point to drive speakers. BI2009 will also drive earphone by using the original speaker
connection point. Figure 3 illustrates the detail.
Through setting external pin of CHANNEL_SEL, BI2009 will switch the driver output between
speaker and earphone. When CHANNEL_SEL is set to LOW, the driver output is set to speaker. When
CHANNEL_SEL is set to HIGH, the driver output is set to earphone. Table 9 lists the configuration of
CHANNEL_SEL. Table 10 & 11 are the setup of BI2009 for CHANNEL_REV_EN and CHANNEL_SEL
for speaker and earphone, respectively.
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BI2009
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EAR_R_OUT_P
EAR_R_OUT_N
EAR_L_OUT_P
EAR_L_OUT_N
2ch Digital Amplifier
Earphone
LPF
Earphone
Speaker
LPF
Speaker
BI2009
VR_P
VR_N
VL_P
VL_N
CHANNEL_REV_EN
Figure 2. BI2009 Speaker & Earphone Configuration When CHANNEL_REV_EN = Low
3.3V
CHANNEL_REV_EN
EAR_R_OUT_P
EAR_R_OUT_N
EAR_L_OUT_P
EAR_L_OUT_N
PWM_OUTSEL
BI2009
BD-7001
12V Speaker
Driver
Speaker
LPF
Earphone
LPF
Earphone
Speaker
PWM_SYNC_CLK
VR_P
VR_N
VL_P
VL_N
Figure 3. BI2009 Speaker & Earphone Configuration When CHANNEL_REV_EN = High
Table 9. CHANNEL_SEL Configuration
CHANNEL_SEL
Speaker Driver & Earphone Driver Select
0
Speaker Output Enable, Earphone Output Disable
1
Speaker Output Disable, Earphone Output Enable
Table 10. BI2009 Connect Pin For Speaker
CHANNEL_REV_EN CHANNEL_SEL
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Channel Map
Speaker Left
Channel +
Speaker Left
Channel Speaker Right
Channel +
Speaker Right
Channel -
Speaker Driver Output
Pin Name
VL_P
EAR_L_OUT_P
VL_N
EAR_L_OUT_N
VR_P
EAR_R_OUT_P
VR_N
EAR_R_OUT_N
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BI2009
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2ch Digital Amplifier
Table 11. BI2009 Connect Pin For Earphone
CHANNEL_REV_EN CHANNEL_SEL
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
Earphone Driver Output
Pin Name
Channel Map
EAR_L_OUT_P
VL_P
EAR_L_OUT_N
VL_N
EAR_R_OUT_P
VR_P
EAR_R_OUT_N
VR_N
Earphone Left Channel
+
Earphone Left Channel
Earphone Right
Channel +
Earphone Right
Channel -
Further, BI2009 requires Low Pass Filter and the optional circuit in between the Speaker Driver &
Earphone Driver and Speakers. Please refer to BI2009 Application Note Schematic Drawing for detail
Low Pass Filer and optional circuit design.
The Earphone Driver of BI2009 can be set through SPEAKER_SEL to output from 3-wire or
4-wire. Table 12 lists the configuration.
Table 12. SPEAKER_SEL Configuration
SPEAKER_SEL
Earphone Type
0
4-Wire
1
3-Wire
Power-On Initial Volume Configuration
BI2009 provides the function to setup the initial volume value when power-on. The setup is via
external pins of VOL_VALUE_SEL_0 and VOL_VALUE_SEL_1 to determine the initial volume value.
There are 4 values for setup of BI2009: 0 (Mute)、9、16 and 31 (Max Volume). Table 13 is the
corresponding list for setup. Besides, the setup is only valid when RESET_B signal changes from Low
to High. The change of ERF signal cannot trigger this function.
Table 13. VOL_VALUE_SEL Configuration
VOL_VALUE_SEL_1 VOL_VALUE_SEL_0
Initial Volume Value
0
0
31 (Max Volume)
0
1
16
1
0
9
1
1
0 (Mute)
Volume Control Configuration
BI2009 has 32-Level digital volume control by setup pins of VOL_INC and VOL_DEC,. The
Earphone volume is controlled by Left & Right Channel. VOL_INC is used for the increase of the
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BI2009
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2ch Digital Amplifier
volume and VOL_DEC for decrease of the volume.
VOL_INC, VOL_DEC and VOL_ADJ_SEL are to input Low Pulse to activate the action. Figure 4
is the Timing Diagram of input signal. The minimum low pulse is 200µs, and so is the interval. When
VOL_INC & VOL_DEC set to LOW over 1 second, BI2009 will auto increase or decrease the volume
level.
min : 200µs
min : 200µs
min : 200µs
VOL_INC
VOL_DEC
Figure 4. VOL_INC & VOL_DEC Input Timing Diagram
Mute Configuration
BI2009 provides Mute trigger pin for Left & Right Channel while Earphone is controlled together
with Left & Right Channel. To activate the mute action is by inputting the Low Pulse from external pin of
MUTE. Figure 5 illustrates the Timing Diagram of input signal. The minimum low pulse is 200µs, and
so is the interval. BI2009 also provides external pin of MUTE_LED to indicate the mute status for Left
& Right Channel. When MUTE_LED output to HIGH, the mute function of Left & Right Channel is
turned on. When MUTE_LED output to LOW, the mute function of Left & Right Channel is turned off.
Table 14 lists the configuration of MUTE. Further, when mute function is activated and then
deactivated, the previous volume value will not be changed.
min : 200µs
min : 200µs
min : 200µs
MUTE
Figure 5. MUTE Input Timing Diagram
Table 14. MUTE Configuration
MUTE
MUTE_LED
Mute Control Status
Initial Value
0
Left & Right Channel Mute Disable
Low Pulse (1)
1
Left & Right Channel Mute Enable
Low Pulse (2)
0
Left & Right Channel Mute Disable
Volume Boost & Output Anti-Clipping Enable Configuration
BI2009 provides Volume Boost Enable and Output Anti-Clipping Enable functions through
external pin of DVD_VOL_EN_B to control enable/disable of Volume Boost and CLIP_EN_B for
Output Anti-Clipping. The setups are listed in Table 15 and 16.
The function of Volume Boost is to double the output volumes of BI2009. For example, if volume
set to 9 and DVD_VOL_EN_B is set to High, BI2009 will actually output the volume of 9. When
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BI2009
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2ch Digital Amplifier
DVD_VOL_EN_B is set to Low, BI2009 will actually output the volume of 18 to enhance the auditory
sensation.
The function of Output Anti-Clipping is to control the wow effect when output signal is over the
maximum amplitude. For example, when CLIP_EN_B is set to High, BI2009 will automatically control
and decrease the wow effect by internal circuit design to eliminate sound of clip. When CLIP_EN_B is
set to LOW, BI2009 will allow the wow effect and hear the sound of clip. Therefore, it is highly
recommended to set both High for DVD_VOL_EN_B and CLIP_EN_B when play DVD Movie, set to
High when listening to CD for better performance of auditory sensation.
Table 15. DVD_VOL_EN_B Configuration
DVD_VOL_EN_B
Volume Boost Enable
0
Enable
1
Disable
Table 16. CLIP_EN_B Configuration
CLIP_EN_B
Output Anti-Clipping Enable
0
Enable
1
Disable
ERF Configuration
The external pin of ERF is to control the emergency shut down of BI2009. ERF pin setting lists in
Table 17.
When ERF is set to High, BI2009 will emergency shut down the internal Digital Amplifier and set
all of the Speaker Drivers to Low. Only after ERF input back to Low, BI2009’s internal Digital Amplifier
will re-operate. Also, when ERF is activated, BI2009 will remain the internal setting of volume but will
not be clear as the initial volume values setup.
Table 17. ERF Configuration
ERF
Error Flag Input
0
BI2009 Digital Amplifier Normal Operation
1
BI2009 Digital Amplifier Shut-Down,
All Driver Output Low Level
Reset
RESET_B pin of BI2009 is the Global Reset for all internal circuit. Table 18 is the setup of
RESET_B. When reset BI2009, RESET_B must be set to Low, and remain Low at least 1ms.Then
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BI2009
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2ch Digital Amplifier
return to High to complete the process of Reset. Therefore, it is recommended to discharge RC in the
application circuit and design a simple Power On Reset to stable BI2009 after power on.
Table 18 RESET_B Configuration
RESET_B
BI2009 Status
0
Reset
1
Normal Operation
Crystal Connection
In previous section mentioned that BI2009 can connect a Crystal of 45.1584 ~ 49.152MHz to
generate the clock for internal operation. Figure 6 is the recommend application circuit to connect a
49.152MHz Crystal. In Figure 6, to set external pin of EXT_CLK_EN to Low and TEST_EN to High, the
Crystal oscillation status can be monitored by switching Pin 15 to OSC_CLK_OUT. Notice: Because
the specifications and characteristics of various Crystal, the surrounding optional circuit should be
tuned accordingly.
Further, if no connecting to Crystal, EXT_CLK_EN can be set to High and input Clock of 45.1584
~ 49.152MHz via “XIN”. Figure 7 illustrates the example of application circuit of BI2009 and
49.152MHz OSC.
OSC_CLK_OUT
3.3V
BI2009
EXT_CLK_EN
TEST_EN
XIN
XOUT
10M
5pF
49.152MHz
680nH
10pF
1nF
Figure 6. 49.152MHz Crystal Application Circuit
3.3V VDD
BI2009
TEST_EN
EXT_CLK_EN
3.3V VDD
XIN
XOUT
49.152MHz
OSC Clock Unit
Figure 7. 49.152MHz OSC Application Circuit
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BI2009
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2ch Digital Amplifier
Pin 15 - PWM_SYNC_CLK / OSC_CLK_OUT
Table 19 illustrates the configuration of switching the output of PWM_SYNC_CLK or OSC_CLK_
OUT by Pin 15”TEST_EN”.
Table 19. BI2009 Pin 15 Configuration
TEST_EN
BI2009 Pin 15 Configuration
0
PWM_SYNC_CLK
1
OSC_CLK_OUT
While TEST_EN is set to High, Pin 15 is to monitor the status of BI2009 internal OSC circuit.
When TEST_EN is set to Low, Pin 15 is the output of BI2009 internal System Clock to either external
system syncronally use or connect BD7001, 12V 6 Channel Speaker Driver. Table 20 illustrates the
Output Clock Frequency when PWM_SYNC_CLK is under different setup of SRC_EN_B. While
SRC_EN_B is set to High, Pin 15 is output the Clock frequency the same as the input pin of XIN. While
SRC_EN_B is set to Low, Pin 15 will change the output frequency accordingly to the Sample Rate of
Audio Data. If XIN is input the Clock Frequency of 49.152MHz and the Sample Rate of Audio Data is
greater than 64KHz, Pin 15 will output the frequency of XIN Input Clock Frequency divided by 2
(24.576MHz). When the Sample Rate is less than 64KHz, Pin 15 will then output the frequency of XIN
Input Clock Frequency divided by 4 (12.288MHz).
Table 20. BI2009 Pin 15 – PWM_SYNC_CLK Configuration
SRC_EN_B
BI2009 Pin 15 – PWM_SYNC_CLK Configuration
0
When Input Audio Data’s Sample Rate > 64KHz,
PWM_SYNC_CLK Output Frequency = XIN Input Clock Frequency/2
When Input Audio Data’s Sample Rate > 64KHz,
PWM_SYNC_CLK Output Frequency = XIN Input Clock Frequency/4
1
PWM_SYNC_CLK Output Clock Frequency = XIN Input Clock Frequency
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BI2009
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2ch Digital Amplifier
PACKAGE DIMENSION
LQFP48
CONTACT INFORMATION
Biforst Technology Inc.
8F-3, No.26, Tai Yuen St., Jubei City, Hsin-Chu, Taiwan, R.O.C.
Tel: 886-3-552-6521; Fax: 886-3-552-6558; Email: sales@biforst.com.tw
Version History
Version
Date
Page
Description
1.0
2005.01.17
1.1
2005.01.27
2-5
Update Pin Assignment & List
1.2
2005.02.02
2-10
Add Feature and Update Pin Assignment & List
1.3
2005.02.21
8
1.4
2005.04.13
3-15
1.5
2005.06.06
First Release
Update ERF Pin Description
Delete BI2009AP2 and Add Function Description
3-5, 12, 18 Add Data of Device Characteristics & Update Figure 1
Add Function Description of Pin15
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Page 19 of 19