PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single chip 2.4 GHz Transceiver FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • • • • • • True single chip GFSK transceiver Complete OSI Link Layer in hardware Enhanced ShockBurst™ Auto ACK & retransmit Address and CRC computation On the air data rate 1 or 2Mbps Digital interface (SPI) speed 0-10 Mbps 125 RF channel operation Short switching time enable frequency hopping Fully RF compatible with nRF24XX 5V tolerant signal input pads 20-pin package (QFN20 4x4mm) Uses ultra low cost +/- 60 ppm crystal Uses low cost chip inductors and 2-layer PCB Power supply range: 1.9 to 3.6 V Wireless mouse, keyboard, joystick Keyless entry Wireless data communication Alarm and security systems Home automation Surveillance Automotive Telemetry Intelligent sports equipment Industrial sensors Toys GENERAL DESCRIPTION nRF24L01 is a single chip radio transceiver for the world wide 2.4 - 2.5 GHz ISM band. The transceiver consists of a fully integrated frequency synthesizer, a power amplifier, a crystal oscillator, a demodulator, modulator and Enhanced ShockBurst™ protocol engine. Output power, frequency channels, and protocol setup are easily programmable through a SPI interface. Current consumption is very low, only 9.0mA at an output power of -6dBm and 12.3mA in RX mode. Built-in Power Down and Standby modes makes power saving easily realizable. QUICK REFERENCE DATA Parameter Minimum supply voltage Maximum output power Maximum data rate Supply current in TX mode @ 0dBm output power Supply current in RX mode @ 2000 kbps Temperature range Sensitivity @ 1000 kbps Supply current in Power Down mode Value Unit 1.9 0 2000 11.3 12.3 -40 to +85 -85 900 V dBm kbps mA mA °C dBm nA Table 1 nRF24L01 quick reference data Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 1 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Type Number Description Version nRF24L01 nRF24L01 IC nRF24L01-EVKIT 20 pin QFN 4x4, lead free (green) Bare Dice Evaluation kit (2 test PCB, 2 configuration PCB, SW) A A 1.0 Table 2 nRF24L01 ordering information VSS=0V VSS=0V VSS=0V VDD VDD VDD DVDD BLOCK DIAGRAM XC1 VSS=0V Enhanced ShockBurstTM IRQ CSN Clock Recovery, DataSlicer ADDR Decode CRC Code/Decode FIFO In/Out IF BPF DEMOD CE XC2 VDD_PA=1.8V LNA Frequency Synthesiser ANT1 SCK MISO GFSK Filter 100+j175 Ω PA ANT2 MOSI IREF 22kΩ Figure 1 nRF24L01 with external components. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 2 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver PIN FUNCTIONS Pin Name Pin function Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CE CSN SCK MOSI MISO IRQ VDD VSS XC2 XC1 VDD_PA ANT1 ANT2 VSS VDD IREF VSS VDD DVDD VSS Digital Input Digital Input Digital Input Digital Input Digital Output Digital Output Power Power Analog Output Analog Input Power Output RF RF Power Power Analog Input Power Power Power Output Power Chip Enable Activates RX or TX mode SPI Chip Select SPI Clock SPI Slave Data Input SPI Slave Data Output, with tri-state option Maskable interrupt pin Power Supply (+3V DC) Ground (0V) Crystal Pin 2 Crystal Pin 1 Power Supply (+1.8V) to Power Amplifier Antenna interface 1 Antenna interface 2 Ground (0V) Power Supply (+3V DC) Reference current Ground (0V) Power Supply (+3V DC) Positive Digital Supply output for de-coupling purposes Ground (0V) Table 3 nRF24L01 pin function PIN ASSIGNMENT CE VSS DVDD VDD VSS IREF 20 19 18 17 16 1 15 VDD 14 VSS nRF24L01 CSN 2 QFN20 4x4 SCK 3 13 ANT2 MOSI 4 12 ANT1 MISO 5 11 VDD_PA 6 7 8 9 10 IRQ VDD VSS XC2 XC1 Figure 2 nRF24L01 pin assignment (top view) for a QFN20 4x4 package. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 3 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver ELECTRICAL SPECIFICATIONS Conditions: VDD = +3V, VSS = 0V, TA = - 40ºC to + 85ºC Symbol Parameter (condition) Notes Min. Typ. Max. Units 1.9 -40 3.0 +27 3.6 +85 V ºC 0.7VDD VSS 5.25 0.3VDD V V VDD- 0.3 VSS VDD 0.3 V V 2525 MHz MHz kHz kHz kbps MHz MHz Operating conditions VDD TEMP Supply voltage Operating Temperature Digital input pin VIH VIL 1 HIGH level input voltage LOW level input voltage Digital output pin VOH VOL HIGH level output voltage (IOH=-0.5mA) LOW level output voltage (IOL=0.5mA) General RF conditions fOP fXTAL ∆f1M ∆f2M RGFSK FCHANNEL FCHANNEL 2 Operating frequency Crystal frequency Frequency deviation @ 1000kbps Frequency deviation @ 2000kbps Data rate ShockBurst™ Channel spacing @ 1000kbps Channel spacing @ 2000kbps 2400 16 ±160 ±320 >0 2000 1 2 Transmitter operation PRF PRFC PRFCR PBW PRF1 PRF2 IVDD IVDD IVDD IVDD IVDD Maximum Output Power RF Power Control Range RF Power Accuracy 20dB Bandwidth for Modulated Carrier (2000kbps) 1st Adjacent Channel Transmit Power 2MHz 2nd Adjacent Channel Transmit Power 4MHz Supply current @ 0dBm output power Supply current @ -18dBm output power Average Supply current @ -6dBm output power, Enhanced ShockBurst™ Supply current in Standby-I mode Supply current in power down 3 16 4 5 0 18 +4 20 ±4 2000 dBm dB dB kHz -20 -50 11.3 7.0 0.05 dBm dBm mA mA mA 32 900 µA nA 1 All digital inputs handle up to 5.25V signal inputs. Keep in mind that the VDD of the nRF24L01 must match the VIH of the driving device for output pins. 2 Usable band is determined by local regulations 3 Antenna load impedance = 100Ω+j175Ω 4 Antenna load impedance = 100Ω+j175Ω. Effective data rate 1000kbps or 2000 kbps 5 Antenna load impedance = 100Ω+j175Ω. Effective data rate 10kbps and full packets Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 4 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Receiver operation IVDD IVDD RXSENS RXSENS C/ICO C/I1ST C/I2ND C/I3RD C/ICO C/I1ST C/I2ND C/I3RD Supply current one channel 2000kbps Supply current one channel 1000kbps Sensitivity at 0.1%BER (@2000kbps) Sensitivity at 0.1%BER (@1000kbps) C/I Co-channel 1st Adjacent Channel Selectivity C/I 2MHz 2nd Adjacent Channel Selectivity C/I 4MHz 3rd Adjacent Channel Selectivity C/I 6MHz C/I Co-channel 1st Adjacent Channel Selectivity C/I 1MHz 2nd Adjacent Channel Selectivity C/I 2MHz 3rd Adjacent Channel Selectivity C/I 3MHz 12.3 11.8 -82 -85 57/128 0/5 -21/-19 -27/-27 710/1411 6/10 -22/-20 -30/-25 6 9 mA mA dBm dBm dB dB dB dB dB dB dB dB Table 4 nRF24L01 RF specifications 6 Data rate is 2000kbps for the following C/I measurements 7 According to ETSI EN 300 220-1 V1.3.1 (2000-09) page 36 nRF24L01 equal modulation on interfering signal 8 9 Data rate is 1000kbps for the following C/I measurements 10 11 According to ETSI EN 300 220-1 V1.3.1 (2000-09) page 36 nRF24L01 equal modulation on interfering signal Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 5 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver PACKAGE OUTLINE nRF24L01 uses the QFN20 4x4 package, with matt tin plating. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 6 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Package Type Saw QFN20 (4x4 mm) Min Typ. Max A 0.80 0.85 0.95 A1 0.00 0.02 0.05 A3 K D/E e 0.20 REF. 0.20 min 4.0 BSC12 0.5 BSC D2/E2 2.50 2.60 2.70 L 0.35 0.40 0.45 L1 0.15 max Figure 3 nRF24L01 Package Outline. 12 BSC: Basic Spacing between Centers, ref. JEDEC standard 95, page 4.17-11/A Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 7 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 b 0.18 0.25 0.30 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Package marking: n D Y R F B D D D D Y W W L X D L Abbreviations: DDDDDD – Product number, e.g. 24L01 B – Build Code, i.e. unique code for production sites, package type and test platform X – "X" grade, i.e. Engineering Samples (optional) YY – 2 digit Year number WW – 2 digit Week number LL – 2 letter wafer lot number code Absolute Maximum Ratings Supply voltages VDD............................- 0.3V to + 3.6V VSS .................................................. 0V Input voltage VI .................................. - 0.3V to 5.25V Output voltage VO ..................................... VSS to VDD Total Power Dissipation PD (TA=85°C) ............................. 60mW Temperatures Operating Temperature…. - 40°C to + 85°C Storage Temperature….… - 40°C to + 125°C Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device. ATTENTION! Electrostatic Sensitive Device Observe Precaution for handling. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 8 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Glossary of Terms Term Description ACK ART CE CLK CRC CSN ESB GFSK IRQ ISM LNA LSB LSByte Mbps MCU MISO MOSI MSB MSByte PCB PER PID PLD PRX PTX PWR_DWN PWR_UP RX RX_DR SPI TX TX_DS Acknowledgement Auto Re-Transmit Chip Enable Clock Cyclic Redundancy Check Chip Select NOT Enhanced ShockBurst™ Gaussian Frequency Shift Keying Interrupt Request Industrial-Scientific-Medical Low Noise Amplifier Least Significant Bit Least Significant Byte Megabit per second Micro Controller Unit Master In Slave Out Master Out Slave In Most Significant Bit Most Significant Byte Printed Circuit Board Packet Error Rate Packet Identity Bits Payload Primary RX Primary TX Power Down Power Up Receive Receive Data Ready Serial Peripheral Interface Transmit Transmit Data Sent Table 5 Glossary Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 9 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver FUNCTIONAL DESCRIPTION Modes of operation The nRF24L01 can be set in the following main modes depending on the level of the following primary I/Os and configuration registers: Mode RX mode TX mode TX mode PWR_UP register PRIM_RX register CE FIFO state 1 1 1 1 0 0 1 1 10 1 1 0 0 - 1 0 - Data in TX FIFO Stays in TX mode until packet transmission is finished TX FIFO empty No ongoing packet transmission - Standby-II Standby-I Power Down Table 6 nRF24L01 main modes An overview of the nRF24L01 I/O pins in different modes is given in Table 7. Pin functions in the different modes of nRF24L01 Pin Name CE CSN SCK MOSI MISO IRQ Direction Input Input Input Input Tri-state Output Output TX Mode High Pulse >10µs RX Mode Standby Modes High Low SPI Chip Select, active low SPI Clock SPI Serial Input SPI Serial Output Power Down - Interrupt, active low Table 7 Pin functions of the nRF24L01 Standby Modes Standby-I mode is used to minimize average current consumption while maintaining short start up times. In this mode, part of the crystal oscillator is active. In Standby-II mode some clock buffers are active. Standby-II occurs when CE is held high on a PTX device with empty TX FIFO. The configuration word content is maintained during Standby modes. SPI interface may be activated. For start up time see Table 13. Power Down Mode In power down nRF24L01 is disabled with minimal current consumption. When entering this mode the device is not active, but all registers values available from the SPI interface are maintained during power down and the SPI interface may be activated (CSN=0). For start up time see Table 13. The power down is controlled by the PWR_UP bit in the CONFIG register. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 10 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Packet Handling Methods nRF24L01 has the following Packet Handling Methods: • ShockBurst™ (compatible with nRF2401, nRF24E1, nRF2402 and nRF24E2 with 1Mbps data rate, see page 24) • Enhanced ShockBurst™ ShockBurst™ ShockBurst™ makes it possible to use the high data rate offered by nRF24L01 without the need of a costly, high-speed microcontroller (MCU) for data processing/clock recovery. By placing all high speed signal processing related to RF protocol on-chip, nRF24L01 offers the application microcontroller a simple SPI compatible interface, the data rate is decided by the interface-speed the micro controller itself sets up. By allowing the digital part of the application to run at low speed, while maximizing the data rate on the RF link, ShockBurst™ reduces the average current consumption in applications. In ShockBurst™ RX, IRQ notifies the MCU when a valid address and payload is received respectively. The MCU can then clock out the received payload from an nRF24L01 RX FIFO. In ShockBurst™ TX, nRF24L01 automatically generates preamble and CRC, see Table 12. IRQ notifies the MCU that the transmission is completed. All together, this means reduced memory demand in the MCU resulting in a low cost MCU, as well as reduced software development time. nRF24L01 has a three level deep RX FIFO (shared between 6 pipes) and a three level deep TX FIFO. The MCU can access the FIFOs at any time, in power down mode, in standby modes, and during RF packet transmission. This allows the slowest possible SPI interface compared to the average datarate, and may enable usage of an MCU without hardware SPI. Enhanced ShockBurst™ Enhanced ShockBurst™ is a packet handling method with functionality that makes bidirectional link protocol implementation easier and more efficient. In a typical bidirectional link, one will let the terminating part acknowledge received packets from the originating part in order to make it possible to detect data loss. Data loss can then be recovered by retransmission. The idea with Enhanced ShockBurst™ is to let nRF24L01 handle both acknowledgement of received packets and retransmissions of lost packets, without involvement from the microcontroller. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 11 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver TX3 TX4 TX2 Pi pe ta TX6 Da 2 Da ta 5 Data P pe Pi Pipe 3 Data ta Da TX1 ipe 4 TX5 Pip e1 Data e0 Pip RX Frequency Channel N Figure 4: nRF24L01 in a star network configuration An nRF24L01 configured as primary RX (PRX) will be able to receive data trough 6 different data pipes, see Figure 4. A data pipe will have a unique address but share the same frequency channel. This means that up to 6 different nRF24L01 configured as primary TX (PTX) can communicate with one nRF24L01 configured as PRX, and the nRF24L01 configured as PRX will be able to distinguish between them. Data pipe 0 has a unique 40 bit configurable address. Each of data pipe 1-5 has an 8 bit unique address and shares the 32 most significant address bits. All data pipes can perform full Enhanced ShockBurst™ functionality. nRF24L01 will use the data pipe address when acknowledging a received packet. This means that nRF24L01 will transmit ACK with the same address as it receives payload at. In the PTX device data pipe 0 is used to received the acknowledge, and therefore the receive address for data pipe 0 has to be equal to the transmit address to be able to receive the acknowledge. See Figure 5 for addressing example. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 12 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver TX RX _AD _A DR DD : R_ P0 0x :0 B3 xB B4 3B B5 4B B6 5B 0F 60 F A3 B6 3 B5 B4 5B6A B3 0x 3B4B B 0x R: DD _P0: _A TX ADDR RX_ 2 Pi ta Da pe Pi pe 5 ta Da Figure 5: Example on how the acknowledgement addressing is done An nRF24L01 configured as PTX with Enhanced ShockBurst™ enabled, will use the ShockBurst™ feature to send a packet whenever the microcontroller wants to. After the packet has been transmitted, nRF24L01 will switch on its receiver and expect an acknowledgement to arrive from the terminating part. If this acknowledgement fails to arrive, nRF24L01 will retransmit the same packet until it receives an acknowledgement or the number of retries exceeds the number of allowed retries given in the SETUP_RETR_ARC register. If the number of retries exceeds the number of allowed retries, this will show in the STATUS register bit MAX_RT and gives an interrupt. Whenever an acknowledgement is received by an nRF24L01 it will consider the last transmitted packet as delivered. It will then be cleared from the TX FIFO, and the TX_DS IRQ source will be set high. With Enhanced ShockBurst™ nRF24L01 offers the following benefits: • Highly reduced current consumption due to short time on air and sharp timing when operating with acknowledgement traffic • Lower system cost. Since the nRF24L01 handles all the high-speed link layer operations, like re-transmission of lost packet and generating acknowledgement to received packets, it is no need for hardware SPI on the system microcontroller to interface the nRF24L01. The interface can be done by using general purpose IO pins on a low cost microcontroller where the SPI is emulated in firmware. With the nRF24L01 this will be sufficient speed even when running a bi-directional link. • Greatly reduced risk of “on-air” collisions due to short time on air • Easier firmware development since the link layer is integrated on chip Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 13 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Enhanced ShockBurst™ Transmitting Payload: 1. The configuration bit PRIM_RX has to be low. 2. When the application MCU has data to send, the address for receiving node (TX_ADDR) and payload data (TX_PLD) has to be clocked into nRF24L01 via the SPI interface. The width of TX-payload is counted from number of bytes written into the TX FIFO from the MCU. TX_PLD must be written continuously while holding CSN low. TX_ADDR does not have to be rewritten if it is unchanged from last transmit. If the PTX device shall receive acknowledge, data pipe 0 has to be configured to receive the acknowledge. The receive address for data pipe 0 (RX_ADDR_P0) has to be equal to the transmit address (TX_ADDR) in the PTX device. For the example in Figure 5 the following address settings have to be performed for the TX5 device and the RX device: TX5 device: TX_ADDR = 0xB3B4B5B605 TX5 device: RX_ADDR_P0 = 0xB3B4B5B605 RX device: RX_ADDR_P5 = 0xB3B4B5B605 3. A high pulse on CE starts the transmission. The minimum pulse width on CE is 10 µs. 4. nRF24L01 ShockBurst™: • Radio is powered up • 16 MHz internal clock is started. • RF packet is completed (see the packet description) • Data is transmitted at high speed (1 Mbps or 2 Mbps configured by MCU). 5. If auto acknowledgement is activated (Auto retransmit counter not equal zero, ENAA_P0=1) the radio goes into RX mode immediately. If a valid packet has been received in the valid acknowledgement time window, the transmission is considered a success. The TX_DS bit in the status register is set high and the payload is removed from TX FIFO. If a valid acknowledgement is not received in the specified time window, the payload is resent (if auto retransmit is enabled). If the auto retransmit counter (ARC_CNT) exceeds the programmed maximum limit (ARC), the MAX_RT bit in the status register is set high. The payload in TX FIFO is NOT removed. The IRQ pin will be active when MAX_RT or TX_DS is high. To turn off the IRQ pin, the interrupt source must be reset by writing to the status register (see Interrupt chapter). If no acknowledgement is received for a packet after the maximum number of retries, no further packets can be sent before the MAX_RX interrupt is cleared. The packet loss counter (PLOS_CNT) is incremented at each MAX_RT interrupt. I.e. ARC_CNT counts the number of retries that was required to get a single packet through. PLOS_CNT counts the number of packets that did not get through even after maximum number of retries. 6. The device goes into Standby-I mode if CE is low. Otherwise next payload in TX FIFO will be sent. If TX FIFO is empty and CE is still high, the device will enter Standby-II mode. 7. If the device is in Standby-II mode, it will go to Standby-I mode immediately if CE is set low. Enhanced ShockBurstTM Receive Payload: 1. RX is selected by setting the PRIM_RX bit in the configuration register to high, and then setting CE high. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 14 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver 2. After 130µs nRF24L01 is monitoring the air for incoming communication. 3. When a valid packet has been received (matching address and correct CRC), the payload is stored in the RX-FIFO, and the RX_DR bit in status register is set high. The IRQ pin will be active when RX_DR is high. RX_P_NO in status register will indicate what data pipe the payload has been received in. 4. If auto acknowledgement is enabled, an acknowledgement is sent back. 5. MCU sets the CE pin low to enter Standby-I mode (low current mode). 6. MCU can clock out the payload data at a suitable rate via the SPI interface. 7. The device is now ready for entering TX or RX mode or power down mode. Auto Acknowledgement (RX) The auto acknowledgement function reduces the load of the external microcontroller, and may remove the need for dedicated SPI hardware in a mouse/keyboard or comparable systems, and hence reduce cost and average current consumption. Auto acknowledgement can be configured individually for each data pipe via the SPI interface. If auto acknowledgement is enabled and a valid packet (correct data pipe address and CRC) is received, the device will enter TX mode and send an acknowledgement packet. After the device has sent the acknowledgement packet, normal operation resumes, and the mode is determined by the PRIM_RX register and CE pin. Auto Re-Transmission (ART) (TX) An auto retransmission function is available. It will be used at the TX side in an auto acknowledgement system. In the SETUP_RETR register it will be possible to state how many times the data in the data register will be resent if data is not acknowledged. After each sending, the device will enter RX mode and wait a specified time period for acknowledgement. When the acknowledgement packet is received, the device will return to normal transmit function. If there is no more unsent data in the TX FIFO and the CE pin is low, the device will go into Standby-I mode. If the acknowledgement is not received, the device will go back to TX mode and resend the data. This will continue until acknowledgment is received, or a time out occurs (i.e. the maximum number of sending is reached). The only way to reset this is to set the PWR_UP bit low or let the auto retransmission finish. A packet loss counter will be incremented each time a packet does not succeed to reach the destination before time out. (Time out is indicated by the MAX_RT interrupt.) The packet loss counter is reset when writing to the RF channel register. Packet Identity (PID) and CRC used by Enhanced ShockBurstTM Each packet contains a two bit wide PID field to detect if the received packet is new or resent. The PID will prevent that the PRX device presents the same payload more than once to the microcontroller. This PID field is incremented at the TX side for each new packet received via the SPI interface. The PID and CRC field is used by the PRX device to determine whether a packet is resent or new. When several data is lost on the link, the PID fields may in some cases become equal to last received PID. If a packet has the same PID as the previous packet, nRF24L01 will compare the CRC sums from both packets. If they also are equal, the last received packet is considered as a copy of the previous and is discarded. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 15 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver 1: PRX device: The PRX device compares the received PID with the last PID. If the PID fields are different, the packet is considered to be new. If the PID is equal to last received PID, the received packet might be the same as last time. The receiver must check if the CRC is equal to the previous CRC. If the CRC is equal to the previous one, the packet is probably the same, and will be discarded. 2: PTX device: The transmitter increments the PID field each time it sends a new packet. TX side functionality RX side functionality Start New packet from MCU? Start PID equal last PID? Yes Yes CRC equal last CRC? Yes increment PID No No No New packet is valid for MCU Discard packet as a copy End End Figure 6 PID generation/detection The length of the CRC is configurable through the SPI interface. It is important to notice that the CRC is calculated over the whole packet including address, PID and payload. No packet is accepted as correct if the CRC fails. This is an extra requirement for packet acceptance that is not illustrated in the figure above. Stationary Disturbance Detection – CD Carrier Detect (CD) is set high when an in-band RF signal is detected in RX mode, otherwise CD is low. The internal CD signal is filtered before presented to CD register. The internal CD signal must be high for at least 128µs. In Enhanced ShockBurst™ it is recommended to use the Carrier Detect functionality only when the PTX device does not succeed to get packets through, as indicated by the MAX_RT interrupt for single packets and by the packet loss counter (PLOS_CNT) if several packets are lost. If the PLOS_CNT in the PTX device indicates too high rate of packet losses, the device can be configured to a PRX device for a short time (Tstbt2a + CD-filter delay = 130µs+128µs = 258µs) to check CD. If CD was high (jam situation), the frequency channel should be changed. If CD was low Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 16 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver (out of range), it may continue on the same frequency channel, but perform other adjustments. (A dummy write to the RF_CH will clear the PLOS_CNT.) Data Pipes nRF24L01 configured as PRX can receive data addressed to 6 different data pipes in one physical frequency channel. Each data pipe has its own unique address and can be configured to have individual behavior. The data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. The address for each data pipe is configured in the RX_ADDR_Px registers. Always ensure that none of the data pipes have the exact same address. Data pipe 0 has a unique 40 bit configurable address. Data pipes 1-5 share the 32 most significant address bits and have only the LSByte unique for each data pipe. Figure 7 shows an example of how data pipes 0-5 are addressed. All pipes can have up to 40 bit address, but for pipe 1-5 only the LSByte is different. Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Data pipe 0 (RX_ADDR_P0) 0xE7 0xD3 0xF0 0x35 0x77 Data pipe 1 (RX_ADDR_P1) 0xC2 0xC2 0xC2 0xC2 0xC2 Data pipe 2 (RX_ADDR_P2) 0xC2 0xC2 0xC2 0xC2 0xC3 Data pipe 3 (RX_ADDR_P3) 0xC2 0xC2 0xC2 0xC2 0xC4 Data pipe 4 (RX_ADDR_P4) 0xC2 0xC2 0xC2 0xC2 0xC5 Data pipe 5 (RX_ADDR_P5) 0xC2 0xC2 0xC2 0xC2 0xC6 Figure 7: Addressing data pipes 0-5 When a packet has been received at one of the data pipes and the data pipe is setup to generate acknowledgement, nRF24L01 will generate an acknowledgement with an address that equals the data pipe address where the packet was received. Some configuration settings are common to all data pipes and some are individual. The following settings are common to all data pipes: • CRC enabled/disabled (CRC always enabled when ESB is enabled) • CRC encoding scheme • RX address width • Frequency channel • RF data rate • LNA gain • RF output power Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 17 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver DEVICE CONFIGURATION All configuration of nRF24L01 is defined by values in some configuration registers. All these registers are writable via the SPI interface. SPI Interface The SPI interface is a standard SPI interface with a maximum data rate of 10Mbps. Most registers are readable. SPI Instruction Set The available commands to be used on the SPI interface are shown below. Whenever CSN is set low the interface expects an instruction. Every new instruction must be started by a high to low transition on CSN. In parallel to the SPI instruction word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin. The serial shifting SPI commands is on the format: <Instruction word: MSBit to LSBit (one byte)> <Data bytes: LSByte to MSByte, MSBit in each byte first> See Figure 8 and Figure 9. Instruction Name Instruction # Data Operation Format Bytes [binary] R_REGISTER 000A AAAA W_REGISTER 001A AAAA R_RX_PAYLOAD 0110 0001 W_TX_PAYLOAD 1010 0000 1 to 32 LSByte first FLUSH_TX FLUSH_RX 1110 0001 1110 0010 0 0 REUSE_TX_PL 1110 0011 0 1111 1111 0 NOP 1 to 5 LSByte first 1 to 5 LSByte first 1 to 32 LSByte first Read registers. AAAAA = 5 bit Memory Map Address Write registers. AAAAA = 5 bit Memory Map Address Executable in power down or standby modes only. Read RX-payload: 1 – 32 bytes. A read operation will always start at byte 0. Payload will be deleted from FIFO after it is read. Used in RX mode. Used in TX mode. Write TX-payload: 1 – 32 bytes. A write operation will always start at byte 0. Flush TX FIFO, used in TX mode Flush RX FIFO, used in RX mode Should not be executed during transmission of acknowledge, i.e. acknowledge package will not be completed. Used for a PTX device Reuse last sent payload. Packets will be repeatedly resent as long as CE is high. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission No Operation. Might be used to read the STATUS register Table 8 Instruction set for the nRF24L01 SPI interface. The W_REGISTER and R_REGISTER may operate on single or multi-byte registers. When accessing multi-byte registers one will read or write MSBit of LSByte first. The Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 18 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver writing can be terminated before all bytes in a multi-byte register has been written. In this case the unwritten MSByte(s) will remain unchanged. E.g. the LSByte of RX_ADDR_P0 can be modified by writing only one byte to the RX_ADDR_P0 register. The content of the status register will always be read to MISO after a high to low transition on CSN. Interrupt The nRF24L01 has an active low interrupt pin (IRQ). The interrupt pin is activated when TX_DS, RX_DR or MAX_RT is set high in status register. When MCU writes '1' to the interrupt source, the IRQ pin will go inactive. The interrupt mask part of the CONFIG register is used to mask out the interrupt sources that are allowed to set the IRQ pin low. By setting one of the MASK bits high, the corresponding interrupt source will be disabled. By default all interrupt sources are enabled. SPI Timing The interface supports SPI. SPI operation and timing is given in Figure 8 to Figure 10 and in Table 9 and Table 10. The device must be in one of the standby modes or power down mode before writing to the configuration registers. In Figure 8 to Figure 10 the following notations are used: Cn – SPI Instruction Bit Sn – Status Register Bit Dn – Data Bit (note: LSByte to MSByte, MSBit in each byte first) CSN SCK MOSI C7 C6 C5 C4 C3 C2 C1 C0 MISO S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 D1 2 D13 D12 D11 D1 1 D1 0 D9 D8 Figure 8 SPI read operation. CSN SCK MOSI C7 C6 C5 C4 C3 C2 C1 C0 MISO S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D10 D9 D8 Figure 9 SPI write operation. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 19 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Tcwh CSN Tcc Tch Tcl Tcch SCK Tdh Tdc MOSI C7 C6 Tcsd MISO C0 Tcd Tcdz S7 S0 Figure 10 SPI NOP timing diagram. PARAMETER Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z SYMBOL Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz MIN 2 2 MAX 33 52 40 40 0 10 tbd 2 2 50 33 UNITS ns ns ns ns ns ns MHz ns ns ns ns ns Table 9 SPI timing parameters (Cload = 5pF). PARAMETER Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z SYMBOL Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz MIN 2 2 MAX 38 54 40 40 0 10 tbd 2 2 50 38 UNITS ns ns ns ns ns ns MHz ns ns ns ns ns Table 10 SPI timing parameters (Cload = 10pF). Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 20 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Memory Map All undefined bits in the table below are redundant. They will be read out as '0'. Address (Hex) Mnemonic 00 01 02 03 04 Bit Reset Value Type Description CONFIG Reserved MASK_RX_DR 7 6 0 0 R/W R/W MASK_TX_DS 5 0 R/W MASK_MAX_RT 4 0 R/W EN_CRC 3 1 R/W CRCO 2 0 R/W PWR_UP PRIM_RX 1 0 0 0 R/W R/W Configuration Register Only '0' allowed Mask interrupt caused by RX_RD 1: Interrupt not reflected on the IRQ pin 0: Reflect RX_DR as active low interrupt on the IRQ pin Mask interrupt caused by TX_DS 1: Interrupt not reflected on the IRQ pin 0: Reflect TX_DS as active low interrupt on the IRQ pin Mask interrupt caused by MAX_RT 1: Interrupt not reflected on the IRQ pin 0: Reflect MAX_RT as active low interrupt on the IRQ pin Enable CRC. Forced high if one of the bits in the EN_AA is high CRC encoding scheme '0' - 1 byte '1' – 2 bytes 1: POWER UP, 0:POWER DOWN 1: PRX, 0: PTX EN_AA Enhanced ShockBurst™ Reserved ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 7:6 5 4 3 2 1 0 00 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Enable ‘Auto Acknowledgment’ Function Disable this functionality to be compatible with nRF2401, see page 25 Only '00' allowed Enable auto ack. data pipe 5 Enable auto ack. data pipe 4 Enable auto ack. data pipe 3 Enable auto ack. data pipe 2 Enable auto ack. data pipe 1 Enable auto ack. data pipe 0 EN_RXADDR Reserved ERX _P5 ERX _P4 ERX _P3 ERX _P2 ERX _P1 ERX _P0 7:6 5 4 3 2 1 0 00 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W Enabled RX Addresses Only '00' allowed Enable data pipe 5. Enable data pipe 4. Enable data pipe 3. Enable data pipe 2. Enable data pipe 1. Enable data pipe 0. SETUP_AW Reserved AW 7:2 1:0 000000 11 R/W R/W SETUP_RETR ARD 7:4 0000 R/W Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 21 of 38 Setup of Address Widths (common for all data pipes) Only '000000' allowed RX/TX Address field width '00' - Illegal '01' - 3 bytes '10' - 4 bytes '11' – 5 bytes LSByte will be used if address width below 5 bytes Setup of Automatic Retransmission Auto Re-transmit Delay - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Address (Hex) 05 06 Mnemonic Bit Type ARC 3:0 0011 R/W RF_CH Reserved RF_CH 7 6:0 0 0000010 R/W R/W RF_SETUP Reserved PLL_LOCK RF_DR 7:5 4 3 000 0 1 R/W R/W R/W RF_PWR 2:1 11 R/W 0 1 R/W LNA_HCURR 07 Reset Value Description ‘0000’ – Wait 250+86uS ‘0001’ – Wait 500+86uS ‘0010’ – Wait 750+86uS …….. ‘1111’ – Wait 4000+86uS (Delay defined from end of transmission to start of next transmission) Auto Retransmit Count ‘0000’ –Re-Transmit disabled ‘0001’ – Up to 1 Re-Transmit on fail of AA …… ‘1111’ – Up to 15 Re-Transmit on fail of AA RF Channel Only '0' allowed Sets the frequency channel nRF24L01 operates on RF Setup Register Only '000' allowed Force PLL lock signal Data Rate ‘0’ – 1 Mbps ‘1’ – 2 Mbps Set RF output power in TX mode '00' – -18 dBm '01' – -12 dBm '10' – -6 dBm '11' – 0 dBm Setup LNA gain STATUS Status Register (In parallel to the SPI instruction word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin) Only '0' allowed Data Ready RX FIFO interrupt. Set high when new data arrives RX FIFO13. Reserved RX_DR 7 6 0 0 R/W R/W TX_DS 5 0 R/W Data Sent TX FIFO interrupt. Set high when packet sent on TX. If AUTO_ACK is activated, this bit will be set high only when ACK is received. MAX_RT 4 0 R/W Maximum number of TX retries interrupt Write 1 to clear bit. Write 1 to clear bit. Write 1 to clear bit. If MAX_RT is set it must be cleared to enable further communication. RX_P_NO 3:1 111 R TX_FULL 0 0 R Data pipe number for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty TX FIFO full flag. 1: TX FIFO full. 0: 13 The Data Ready interrupt is set by a new packet arrival event. The procedure for handling this interrupt should be: 1) read payload via SPI, 2) clear RX_DR interrupt, 3) read FIFO_STATUS to check if there are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from 1). Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 22 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Address (Hex) Mnemonic Bit Reset Value Type Description Available locations in TX FIFO. 08 OBSERVE_TX PLOS_CNT 7:4 0 R ARC_CNT 3:0 0 R CD Reserved CD 7:1 0 000000 0 R R 0A RX_ADDR_P0 39:0 0xE7E7E7E7E7 R/W 0B RX_ADDR_P1 39:0 0xC2C2C2C2C2 R/W 0C RX_ADDR_P2 7:0 0xC3 R/W 0D RX_ADDR_P3 7:0 0xC4 R/W 0E RX_ADDR_P4 7:0 0xC5 R/W 0F RX_ADDR_P5 7:0 0xC6 R/W 10 TX_ADDR 39:0 0xE7E7E7E7E7 R/W Transmit address. Used for a PTX device only. (LSByte is written first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX device with Enhanced ShockBurst™ enabled. See page 14. 11 RX_PW_P0 Reserved RX_PW_P0 7:6 5:0 00 0 R/W R/W Only '00' allowed Number of bytes in RX payload in data pipe 0 (1 to 32 bytes). 0 Not Legal 1 = 1 byte … 32 = 32 bytes RX_PW_P1 Reserved RX_PW_P1 7:6 5:0 00 0 R/W R/W Only '00' allowed Number of bytes in RX payload in data pipe 1 (1 to 32 bytes). 0 Not Legal 1 = 1 byte … 32 = 32 bytes RX_PW_P2 Reserved RX_PW_P2 7:6 5:0 00 0 R/W R/W Only '00' allowed Number of bytes in RX payload in data pipe 2 (1 to 32 bytes). 09 12 13 Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 23 of 38 Transmit observe register Packet Loss Counter. The register is reset by writing to RF_CH. The counter restarts after 15 lost packets. See page 14 and 16. Current value on resent counter. The counter is reset when transmission of a new packet starts. See page 14. Carrier Detect. See page 16. Receive address data pipe 0. 5 Bytes maximum length. (LSByte is written first) Receive address data pipe 1. 5 Bytes maximum length. (LSByte is written first) Receive address data pipe 2. Only LSB. MSBytes will be equal to RX_ADDR_P1[39:8] Receive address data pipe 3. Only LSB. MSBytes will be equal to RX_ADDR_P1[39:8] Receive address data pipe 4. Only LSB. MSBytes will be equal to RX_ADDR_P1[39:8] Receive address data pipe 5. Only LSB. MSBytes will be equal to RX_ADDR_P1[39:8] - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Address (Hex) Mnemonic Bit Reset Value Type Description 0 Not Legal 1 = 1 byte … 32 = 32 bytes 14 15 16 17 RX_PW_P3 Reserved RX_PW_P3 7:6 5:0 00 0 R/W R/W Only '00' allowed Number of bytes in RX payload in data pipe 3 (1 to 32 bytes). 0 Not Legal 1 = 1 byte … 32 = 32 bytes RX_PW_P4 Reserved RX_PW_P4 7:6 5:0 00 0 R/W R/W Only '00' allowed Number of bytes in RX payload in data pipe 4 (1 to 32 bytes). 0 Not Legal 1 = 1 byte … 32 = 32 bytes RX_PW_P5 Reserved RX_PW_P5 7:6 5:0 00 0 R/W R/W Only '00' allowed Number of bytes in RX payload in data pipe 5 (1 to 32 bytes). 0 Not Legal 1 = 1 byte … 32 = 32 bytes FIFO_STATUS Reserved TX_REUSE 7 6 0 0 R/W R TX_FULL 5 0 R TX_EMPTY 4 1 R 3:2 1 00 0 R/W R 0 1 R Reserved RX_FULL RX_EMPTY N/A TX_PLD 255:0 X W N/A RX_PLD 255:0 X R FIFO Status Register Only '0' allowed Reuse last sent data packet if set high. The packet will be repeatedly resent as long as CE is high. TX_REUSE is set by the SPI instruction REUSE_TX_PL, and is reset by the SPI instructions W_TX_PAYLOAD or FLUSH TX TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. TX FIFO empty flag. 1: TX FIFO empty. 0: Data in TX FIFO. Only '00' allowed RX FIFO full flag. 1: RX FIFO full. 0: Available locations in RX FIFO. RX FIFO full flag. 1: RX FIFO empty. 0: Data in RX FIFO. Written by separate SPI command TX data payload register 1 - 32 bytes. This register is implemented as a FIFO with 3 levels. Used in TX mode only Written by separate SPI command RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with 3 levels. All receive channels share the same FIFO Table 11 Memory map of nRF24L01 Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 24 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Configuration for compatibility with nRF24XX How to setup nRF24L01 to receive from an nRF2401/nRF2402/nRF24E1/nRF24E2: • Use same CRC configuration as the nRF2401/nRF2402/nRF24E1/nRF24E2 uses • Set the PRIM_RX bit to 1 • Disable auto acknowledgement on the data pipe that will be addressed • Use the same address width as the PTX device • Use the same frequency channel as the PTX device • Select data rate 1Mbit/s on both nRF24L01 and nRF2401/nRF2402/nRF24E1/nRF24E2 • Set correct payload width on the data pipe that will be addressed • Set PWR_UP and CE high How to setup nRF24L01 to transmit to an nRF2401/nRF24E1: • Use same CRC configuration as the nRF2401/nRF2402/nRF24E1/nRF24E2 uses • Set the PRIM_RX bit to 0 • Set the Auto Retransmit Count to 0 to disable the auto retransmit functionality • Use the same address width as the nRF2401/nRF2402/nRF24E1/nRF24E2 uses • Use the same frequency channel as the nRF2401/nRF2402/nRF24E1/nRF24E2 uses • Select data rate 1Mbit/s on both nRF24L01 and nRF2401/nRF2402/nRF24E1/nRF24E2 • Set PWR_UP high • Clock in a payload that has the same length as the nRF2401/nRF2402/nRF24E1/nRF24E2 is configured to receive • Pulse CE to send the packet Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 25 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver PACKET DESCRIPTION An Enhanced ShockBurst™ packet with payload (1-32 bytes). Preamble 1 byte Address 3-5 byte 9 bit CRC 0/1/2 byte Payload 1 - 32 byte flag bits. A ShockBurst™ packet compatible to nRF2401/nRF2402/nRF24E1/nRF24E2 devices. Preamble 1 byte Address 3-5 byte Preamble • Address • • • Flags Payload CRC • • • • • • • • • CRC 0/1/2 byte Payload 1 - 32 byte Preamble is used to detect 0 and 1 levels. It is stripped off (RX) and added (TX) by nRF24L01. The preamble is 8 bits long. The address field contains the receiver address. The address can be 3, 4 or 5 bytes wide The address fields can be individually configured for all RX channels and the TX channel Address is automatically removed from received packets.14 PID: Packet Identification. 2 bits that is incremented for each new payload 7 bits reserved for packet compatibility with future products Not used when compatible to nRF2401/nRF24E1 1 - 32 bytes wide. The CRC is optional. 0-2 bytes wide CRC The polynomial for 8 bits CRC check is X8 + X2 + X + 1 The polynomial for 16 bits CRC check is X16+ X12 + X5 + 1. Table 12 Data packet description 14 Suggested use of addresses. In general more bits in the address gives less false detection, which in the end may give lower data Packet-Error-Rate (PER). A. The address made by (5, 4, or 3) equal bytes are not recommended because it in general will make the packet-error-rate increase. B. Addresses where the level shift only one time (i.e. 000FFFFFFF) could often be detected in noise that may give a false detection, which again may give raised packet-error-rate. C. Addresses as a continuation of the preamble (hi-low toggling) will raise the Packet-Error-Rate (PER). Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 26 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver IMPORTANT TIMING DATA The following timing applies for operation of nRF24L01. nRF24L01 Timing Information nRF24L01 timing Max. Power Down Standby mode Standby modes TX/RX mode Minimum CE high Delay from CE pos. edge to CSN low 1.5ms 130µs Min. Name Tpd2stby Tstby2a Thce Tpece2csn 10µs 4µs Table 13 Operational timing of nRF24L01 When the nRF24L01 is in power down it must always settle in Standby for 1.5ms before it can enter one of the TX or RX modes. Note that the configuration word will be lost if VDD is turned off and that the device then must be configured before going to one of the TX or RX mode. Enhanced ShockBurst™ timing 0us 250us 1 2 1 byte payload with ACK (339 us ) ESB cycle CE high minimum 10 us PTX: CE PTX: IRQ (TX_DS) 2 us PTX: Mode STBY I TX RX TX 6 us ACK (33 us ) Payload (33 us + 4 us /byte) 128 us Antenna 1 0 PRX: CE 6 us SPI: IRQ Clear PRX: IRQ (RX_D R) 128 us PRX: Mode STBY I RX TX RX Pac ket: A ddres s : 5 by tes CRC: 1 by te Pay load: 1 by te Figure 11 Timing of Enhanced ShockBurst™ for one packet upload (2Mbps). Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 27 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver In Figure 11 the sending of one packet and the acknowledgement of this packet is shown. The loading of payload to the PTX device is not shown in the figure. The PRX device is turned into RX mode (CE=1), and the PTX device is set into TX mode (CE=1 for minimum 10 µs). After 130 µs the transmission starts and is finished after another 37 µs (1 byte payload). The transmission ends, and the PTX device is automatically turned around to RX mode to wait for the acknowledgement from the PRX device. After the PTX device has received the acknowledgement it gives an interrupt to the MCU (IRQ (TX_DS) =>TX-data sent). After the PRX device has received the packet it gives an interrupt to the MCU (IRQ (RX_DR) =>RX-data ready). Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 28 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver PERIPHERAL RF INFORMATION Antenna output The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD, either via a RF choke or via the center point in a dipole antenna. A load of 100Ω+j175Ω is recommended for maximum output power (0dBm). Lower load impedance (for instance 50 Ω) can be obtained by fitting a simple matching network. Output Power adjustment SPI RF_SETUP (RF_PWR) RF output power DC current consumption 11 0 dBm 11.3 mA 10 -6 dBm 9.0 mA 01 -12 dBm 7.5 mA 00 -18 dBm 7.0 mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 100Ω+j175Ω. Table 14 RF output power setting for the nRF24L01. Crystal Specification Frequency accuracy includes initial accuracy (tolerance) and stability over temperature and aging. Frequency CL ESR max C0max Frequency accuracy 16MHz 12pF 100 Ω 7.0pF ±60ppm Table 15 Crystal specification of the nRF24L01 To achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. Specifying CL=12pF is OK, but it is possible to use up to 16pF. Specifying a lower value of crystal parallel equivalent capacitance, C0 will also work, but this can increase the price of the crystal itself. Typically C0=1.5pF at a crystal specified for C0max=7.0pF. nRF24L01 sharing crystal with a micro controller. When using a micro controller to drive the crystal reference input XC1 of the nRF24L01 transceiver some rules must be followed. Crystal parameters: When the micro controller drives the nRF24L01 clock input, the requirement of load capacitance CL is set by the micro controller only. The frequency accuracy of ±60 ppm is still required to get a functional radio link. The nRF24L01 will load the crystal by 0.5pF at XC1 in addition to the PBC routing. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 29 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Input crystal amplitude & Current consumption The input signal should not have amplitudes exceeding any rail voltage, but any DCvoltage within this is OK. Exceeding rail voltage will excite the ESD structure and the radio performance is degraded below specification. If testing the nRF24L01 with a RF source with no DC offset as the reference source, the input signal will go below the ground level, which is not acceptable. XO_OUT Buffer: Sine to full swing Amplitude controlled current source Current starved inverter: XOSC core Vdd Vdd Vss Vss ESD ESD XC1 Figure 12 XC2 Principle of crystal oscillator The nRF24L01 crystal oscillator is amplitude regulated. To achieve low current consumption and also good signal-to-noise ratio when using an external clock, it is recommended to use an input signal larger than 0.4 V-peak. When clocked externally, XC2 is not used and can be left as an open pin. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 30 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver PCB layout and de-coupling guidelines A well-designed PCB is necessary to achieve good RF performance. Keep in mind that a poor layout may lead to loss of performance, or even functionality, if due care is not taken. A fully qualified RF-layout for the nRF24L01 and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.no. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The nRF24L01 DC supply voltage should be de-coupled as close as possible to the VDD pins with high performance RF capacitors, see Table 16. It is preferable to mount a large surface mount capacitor (e.g. 4.7µF tantalum) in parallel with the smaller value capacitors. The nRF24L01 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the nRF24L01 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. At least one via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 31 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver APPLICATION EXAMPLE nRF24L01 with single ended matching network crystal, bias resistor, and decoupling capacitors. C7 33nF 0402 C8 1nF 0402 1 2 3 4 5 CE CSN SCK MOSI MISO nRF24L01 15 14 13 12 11 VDD VSS ANT2 ANT1 VDD_PA C5 L3 50ohm, RF I/O 3,9nH 0402 L1 6,8nH 0402 IRQ VDD VSS XC2 XC1 CE CSN SCK MOSI MISO U1 VSS DVDD VDD VSS IREF C9 10nF 0402 R2 22K 0402 20 19 18 17 16 VDD 1,5pF 0402 C6 1,5pF 0402 L2 3.3nH 0402 6 7 8 9 10 NRF24L01 IRQ C3 2.2nF 0402 X1 C4 4.7pF 0402 16 MHz R1 1M C1 22pF 0402 C2 22pF 0402 Figure 13 nRF24L01 schematic for RF layouts with single ended 50Ω RF output. Part 22pF15 15 22pF 2.2nF 4.7pF 1.5pF 1,5pF 33nF 1nF 10nF 6,8nH 3.3nH 3,9nH 1M 22K nRF24L01 16MHz Designator C1 C2 C3 C4 C5 C6 C7 C8 C9 L1 L2 L3 R1 R2 U1 X1 Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN20 4x4 Description NPO, +/- 2%, 50V NPO, +/- 2%, 50V X7R, +/- 10%, 50V NPO, +/- 0.25 pF, 50V NPO, +/- 0.1 pF, 50V NPO, +/- 0.1 pF, 50V X7R, +/- 10%, 50V X7R, +/- 10%, 50V X7R, +/- 10%, 50V chip inductor +/- 5% chip inductor +/- 5% chip inductor +/- 5% +/-10% +/- 1 % +/-60ppm, Cl=12pF15 Table 16 Recommended components (BOM) in nRF24L01 with antenna matching network 15 C1 and C2 must have values that match the crystals load capacitance, Cl. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 32 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver PCB layout examples Figure 14 shows a PCB layout example for the application schematic in Figure 13. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. Top overlay Top layer Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 33 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Bottom layer Figure 14 nRF24L01 RF layout with single ended connection to PCB antenna and 0603 size passive components The nest figure (Figure 15) is for the SMA output to have a board for direct measurements at a 50Ω SMA connector. Top Overlay Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 34 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Top Layer Bottom Layer Figure 15 Module with OFM crystal and SMA connector Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 35 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver DEFINITIONS Data sheet status Objective product specification Preliminary product specification Product specification This data sheet contains target specifications for product development. This data sheet contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. This data sheet contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Table 17. Definitions Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Preliminary Product Specification: Revision Date: 11.11.2005. Data sheet order code: 111105-nRF24L01 All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 36 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver YOUR NOTES Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 37 of 38 - Phone +4772898900 - Fax +4772898989 November 2005 PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single Chip 2.4 GHz Radio Transceiver Nordic Semiconductor ASA – World Wide Distributors For Your nearest dealer, please see http://www.nordicsemi.no Main Office: Vestre Rosten 81, N-7075 Tiller, Norway Phone: +47 72 89 89 00, Fax: +47 72 89 89 89 Visit the Nordic Semiconductor ASA website at http://www.nordicsemi.no Nordic Semiconductor ASA Revision: 1.1 - Vestre Rosten 81, N-7075 Tiller, Norway Page 38 of 38 - Phone +4772898900 - Fax +4772898989 November 2005