PYRAMID P1757ME

PACE1757M/ME
COMPLETE EMBEDDED CPU SUBSYSTEM
FEATURES
Implements complete MIL-STD-1750A ISA including
optional MMU, MFSR, and BPU functions.
Two throughput options:
P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz
P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz
All MIL-STD-1750A data formats and address
types implemented.
P1757ME includes additional matrix and vector
instructions to enhance throughput in
navigation, DSP transcendental and other
complex alorithms.
Error detection and correction and parity bit
provided.
Separate high drive external address & data
busses.
Programmable memory and I/O data wait
state generation permits up to four different
memory speeds in the same system.
Programmable address wait states.
Sixteen levels of interrupts are provided per
MIL-STD-1750A. Interrupts can be either
edge- or level-sensitive.
Fault detection and handling
Programmable detection of unimplemented
memory or illegal I/O addresses.
Full implementation of MIL-STD-1750A fault
register.
External address error detection.
Testability and diagnostics.
10MHz data rate at 40MHz CPU clock
First falling address and data registers.
System support functions included:
Built in test - runs automatically at power on
and after each reset. All hardware blocks
and external busses examined. Hardware
pass/fail for catastrophic failures. Status
register indicates failed test.
Arbitrator for use in tightly coupled
multiprocessor design. Bus control provided
to aid in implementation of multi-processor
systems.
MIL-STD-1750A timers A & B, programmable
watch dog timer and programmable bus timeout function.
Start up ROM support per MIL-STD-1750A.
DMA support for logical and physical memory
addresses.
Console operating mode which allows
operator to examine and change contents of
registers within the CPU, any system
memory location, or the I/O subsystems.
Single 144-pin Quad straight lead or Gullwing
1.5 square inches of board surface.
Operating temperature range -55 to +125°C;
single 5V ± 10% VCC power supply; power
dissipation < 1.9W (worst case at 40 MHz).
GENERAL DESCRIPTION
All functions required for a complete MIL-STD-1750A
embedded CPU subsystem are in this single VLSI
microcircuit occupying 1.5 square inches of board space
with less than 1.9 watts of power dissipation at 40 MHz.
Pyramid's P1757M/ME is a complete, single package, 3.6
MIPS subsystem solution to embedded processor
requirements.
The PACE 1757M uses the application-proven PACE
1750A microprocessor, the PACE 1753, and the PACE
1754. The PACE1757ME uses the enhanced PACE
1750AE microprocessor, which has additional instructions
that provide high throughput for transcendental functions,
navigational algorithms, and DSP functions. The PACE
1750AE is an architectural enhancement of the PACE
1750A.
Document # MICRO-10 REV B
Revised August 2005
PACE 1757 M/ME
Document # MICRO-10 REV B
Page 2 of 34
PACE 1757 M/ME
AC/DC ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
(Above which the useful life may be impaired)
Storage Temperature
-65°C to +150°C
Ambient Temperature with Power
-55°C to +125°C
VCC Pin Potential to Ground Pin
-0.5V to 7.0V
Input Voltage
-0.5V to VCC + 0.5V
Input Current
-30 mA to 5 mA
Voltage Applied to Inputs
-0.5V to VCC + 0.5V
Current Applied to any Output
100 mA
Power Dissipation
2.5 Watts
θJA
35°C/W
RECOMMENDED OPERATING CONDITIONS
Grade
Case Temperature
GND
VCC
Military
-55°C to +125°C
0V
5.0V ± 10%
DC ELECTRICAL SPECIFICATIONS
(Over recommended operating conditions)
Symbol
Parameter
Input HIGH Level
VIH
VIL
VCD
Input LOW Level2
Input clamp diode voltage
Min
2.0
-0.5
Typ.
Max
VCC +0.5
0.8
Unit
V
-1.2
V
Conditions
V
IIN =-18mA
VCC =Min
VOH
Output HIGH Voltage
2.4
V
IOH =-8mA
VCC -0.2
V
IOH =-300µA
VCC =Min
VOL
Output LOW Voltage
Except A0-A15,
0.5
V
IOL=8mA
EXT ADR0-EXT ADR7
0.2
V
IOL=300µA
VCC =Min
Output LOW Voltage
A0-A15,
0.5
V
IOL=20mA
EXT ADR0-EXT ADR7
0.2
V
IOL=300µA
VCC =Min
IIH
Input HIGH Current except
IB0-IB15, EDC0-EDC5, BUS
BUSY, BUS LOCK,
EXT ADR0-EXT ADR7
10
Input HIGH Current IB0-IB15,
50
EDC0-EDC5, BUS BUSY,
BUS LOCK,
EXT ADR0-EXT ADR7
Document # MICRO-10 REV B
µA
VIN =VCC
VCC =Max
µA
VIN =VCC
VCC =Max
Page 3 of 34
PACE 1757 M/ME
DC ELECTRICAL SPECIFICATIONS (Continued)
(Over recommended operating conditions)
Symbol
Parameter
Input LOW current except IB0-IB15, EDC0IIL
Min
Typ.
EDC5, BUS BUSY, BUS LOCK,
Max
Unit
-10
µA
Conditions
VIN=GND
VCC=Max
EXT ADR0-EXT ADR7, TEST ON
IOZH
IOZL
ICCQC
Input LOW current TEST ON
Input LOW current IB0-IB15, EDC0-EDC5,
BUS BUSY, BUS LOCK,
EXT ADR0-EXT ADR7
Output 3-state current Except SINGERR,
STRBA
Output 3-state current SINGERR, STRBA
Output 3-state current Except STRBD
-500
Output 3-state current STRBD
-500
-50
50
-50
Quiescent Power Supply Current
(TTL Levels)
210
f=20 MHz
f=30 MHz
f=35 MHz
f=40 MHz
ICCD
Dynamic Power Supply Current
f=20 MHz
f=30 MHz
f=35 MHz
f=40 MHz
COUT
µA
VCC=Max
VOUT=0.5V
VCC=Max
VIN < 0.2V or
Dynamic Power Supply Current
CIN
VCC=Max
VOUT=2.4V
µA
Quiescent Power Supply Current
(CMOS Input Levels)
ICCD
TTL
IOS
µA
500
80
ICCQT
VIN=V CC
Output Short Circuit Current1
(one output shorted at a time)
3
Input Capacitance
280
310
325
340
150
180
195
210
-25
mA
VIN=3.4V, All inputs,
f=0Hz
mA
Outputs open
VCC=Max
VIN < 0.8V or > 3.4V,
Outputs open
mA V =Max
CC
VIN < 0.2V or
mA
mA
5
pF
9
pF
3
Output Capacitance
> VCC -0.2V, f=0Hz
Outputs open
VCC=Max
> VCC -0.2V
Outputs open,
VCC=Max
VOUT=GND
VCC=Max
Inputs Only
Outputs (includes I/O
Buffers)
Note 1: Duration of the short should not exceed one second.
Note 2: VIL=-3.0V for pulse widths less than or equal to 20ns.
Note 3: This parameter is set by design and not tested.
Document # MICRO-10 REV B
Page 4 of 34
PACE 1757 M/ME
TIMING GENERATOR STATE DIAGRAMS
Two separate and almost independent state diagrams
may be used to describe the PACE1757M machine
cycle.
The Execution Unit performs according to a cycle of
three state represented by Diagram A (the A machine)
and the External Bus Unit follows a minimum cycle of
four states, indicated in Diagram B (the B machine).
Referring to Diagram A, the paths are defined as
follows for the Execution Unit:
(0) External Reset true
(1) External Reset false
(2) ALU wait or Bus wait.
(3) ALU Branch false
(4) ALU Branch true
Diagram A
Diagram B defines the paths for the External Bus as
follows:
(0) External Reset false
(8) Bus Req. false
(9) Bus Req. true and Bus Av. true
(10) Bus Req. true and Bus Av. false
(11) Bus Av. false
(12) Bus Av. true
(13) RDYA false
(14) RDYA true
(16) RDYD false
(17) RDYD true and Bus Req. true and Bus Av. true
Diagram B
(18) RDYD true and Bus Req. false
(19) RDYD true and Bus Req. true and Bus Av. false
(20) Bus Req. true and Bus Av. true
NOTE:
Bus AV = Bus grant and Bus not busy and Bus not locked.
Document # MICRO-10 REV B
Page 5 of 34
PACE 1757 M/ME
DIFFERENCES BETWEEN THE PACE1757M AND PACE1757ME
The PACE1757ME, which uses the P1750AE CPU, achieves a 41% boost in performance (in clock cycles) over the
PACE1757M, which uses the P1750A CPU. This reduction in clocks per instruction is because of three architectural
enhancements:
1. The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2. A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU's peripheral
chips).
3. Branch calculation logic.
The table below shows how the MAC improves all multiply operations - both integer and floating point - by 477% to 760%
PACE1750AE
Instruction
Integer Add/Sub
Double Precision Integer Add/Sub
Integer Multiply
Double Precision Integer Add/Sub
Floating Add/Sub
Extended Floating Add/Sub
Floating Multiply
Extended Floating Point Multiply
Branch (Taken)
Branch (Not Taken)
Flt'g' Point Polynomial Step (Mul+Add/Sub)
Ext Flt'g' Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
Clocks
4
6
4
9
18
34
9
17
8
4
27
51
⎯
PACE1750A
Execution
Time
(40 MHz)
100ns
150ns
100ns
225ns
450ns
850ns
225ns
425ns
200ns
100ns
675ns
1275ns
3.56
Clocks
4
9
23
69
28
51
43
96
12
4
71
147
⎯
Execution
Time
(40 MHz)
100ns
225ns
575ns
1725ns
700ns
1225ns
1075ns
2400ns
300ns
100ns
1775ns
3675ns
2.52
Gain
# Clocks
(%)
⎯
50
575
760
55
50
477
564
50
⎯
263
2400
41/59
PACE1757ME BUILT-IN FUNCTIONS
A core set of additional instructions have been included in the PACE1757ME. These instructions use the Built-In Function (BIF)
opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application areas
such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BIFs and their
execution times (N = the number of elements in the vector being processed).
Instruction
Memory Parametric Dot Product - Single
Memory Parametric Dot Product - Double
3 x 3 Register Dot Product
Double Precision Multiply Accumulate
Polynomial POLY
Clear Accumulator CLAC
Store Accumulator (32-Bit)
Store Accumulator (48-Bit)
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
Load Timer A Reset Register
Load Timer B Reset Register
Document # MICRO-10 REV B
Mnemonic
Address
Mode
Number of
Clocks
VDPS
VDPD
R3DP
MACD
4F06
4F00
STA
STAL
LAC
LACL
MMPG
LTAR
LTBR
4F3(RA)
4F1(RA)
4F03
4F02
7 • N -2
4
4F08
4F04
4F05
4F07
4F0F
4F0D
4F0E
10 + 8 • N
10 + 16 • N
6
8
7
11
9
9
16 + 8 • N
4
4
Notes
Interruptable
Interruptable
Priveleged
Page 6 of 34
PACE 1757 M/ME
TIMING GENERATOR STATE DIAGRAMS
Two separate and almost independent state diagrams
may be used to describe the PACE1757ME machine
cycle.
The Execution Unit performs according to a cycle of
three states represented by Diagram A (the A machine)
and the External Bus Unit follows a minimum cycle of
four states, indicated in Diagram B (the B machine).
Referring to Diagram A, the paths are defined as
follows for the Execution Unit:
(0) External Reset true
(1) External Reset false
(2) ALU wait or Bus wait.
(3) ALU Branch false
(4) ALU Branch true
Diagram A
Diagram B defines the paths for the External Bus as
follows:
(0) External Rest false
(1) No Internal Bus Req.
(2) Internal Bus Req.
(3) Bus Busy or No Bus Grant
(4) Bus Grant and Not Busy or
Bus Locked by CPU
(5) RDYA false
(6) RDYA true
(7) RDYD false
(8) RDYD true, and no Internal Bus Request
(9) RDYD true, Internal Bus Request pending
(10) Bus Locked by CPU and No Internal Request
Diagram B
(11) Bus Locked by CPU Internal Req.
NOTE:
Bus AV = Bus grant and Bus not busy and Bus not locked.
Document # MICRO-10 REV B
Page 7 of 34
PACE 1757 M/ME
SIGNAL PROPAGATION DELAYS
Symbol
Description
TC(BR)L
TC(BR)H
TBGV(C)
TC(BG)X
TC(BB)L
TC(BB)H
TBBV (C)
TC(BB)X
TC(BL) L
TC(BL) H
TBLV (C)
TC(BL) X(IN)
TC(ST) V
BUS REQUEST
TC(ST) X
TC(SA)H
TC(SA)L
TSA L(IBA)X
TRA V(C)
TC(RA)X
TC(SDW)L
TC(SD)H
TFC(SDR)L
TIBDX (SDR) H
TSDWH(IBD)X
TSDL(SD)H(Write)
TRD(RD)X
TC(RD)X
TC(IBA)V
TFC(IBA)X
TIBDRV (C)
TC(IBD)X (Read)
TC(IBD)X (Write)
TFC(IBD) V
TC(SNW)
TFC(TGO)
TRSTL(DMA EN)L
TC(DME)
TFC(NPU)
TC(ER)
TRSTL(NPU)
TREQV (C)
TC(REQ)X
TFV(BB)H
TBBH(F)X
TIRV (C)
TC(IR)X
TRSTL(TRSTH)
TC(XX)Z
20 MHz
MIN
MAX
33
33
BUSGRANT - Setup
BUSGRANT - Hold
BUS BUSY
5
5
BUS BUSY - Setup
BUS BUSY - Hold
BUS LOCK
5
5
BUS LOCK - Setup
BUS LOCK - Hold
M/IO
R/W
AS0:AS3, AK0:AK3, D/I
M/IO, R/W , AS0:AS3, AK0:AK3, D/I
STRBA
5
5
Address Hold from STRBA(L)
RDYA - Setup
RDYA - Hold
STRBD
5
5
5
RDYD - Setup
RDYD - Hold
IB0:IB15
- Setup
- Hold
DATAVALID (OUT)
LEVEL SENSITIVE FAULTS
IOL 1/2 INT. USR INT (0:5) - Setup
PWRDN INT, LEVEL SENSITIVE - HOLD
RESET PULSE WIDTH
CLK TO TRI-STATE
5
5
24
20
30
30
17
17
17
30
0
10
5
5
0
10
25
22
5
5
5
23
25
26
26
35
35
35
50
40
20
0
5
5
0
23
24
24
33
33
33
47
35
0
10
5
5
0
10
18
17
14
14
14
0
17
20
5
5
0
5
5
0
0
10
5
5
0
10
20
16
16
16
16
16
25
30
30
30
40
40
40
60
50
0
0
21
23
5
5
0
5
5
0
20
20
20
16
16
5
5
5
0
25
26
5
5
0
5
5
0
5
5
0
5
5
5
21
17
23
23
20
17
17
22
22
22
5
5
5
5
0
20
17
23
19
25
25
20
22
22
0
30
40
5
5
22
18
25
20
30
30
25
22
22
5
5
5
5
5
5
40 MHz
MIN
MAX
22
22
5
5
5
5
0
35 MHz
MIN
MAX
25
25
25
25
SNEW
TRIGO RST
DMA ENABLE
NORMAL POWER-UP
CLK TO MAJER (UNRCV ER)
RESET
CON REQ
30 MHz
MIN
MAX
20
22
22
30
30
30
45
30
0
10
5
5
0
10
15
15
13
Note 1: Units = ns
Document # MICRO-10 REV B
Page 8 of 34
PACE 1757 M/ME
SIGNAL PROPAGATION DELAYS (cont'd)
Symbol
Description
TD/I(EXT ADR) V
TSTRBD(EXT ADR ER)
TIBDV(EDC GEN) V
TC(GNT)
TC(RDYA)
TIBDIN(MEM PAR ER)
TC(MEM PRT ER)
TSTRBD (WR PROT)
TC(WR PROT)I
TD/I(PROT FLAG)
TD/I(PROT FLAG)
TC(PROT FLAG)
TC(PROT FLAG)
TC(EXT ADR) V
TFC(IB OUT) V
TEX RDY1(RDYD)
TEX RDY(RDYD)
TC (RDYD)V
TSTRBAh(A) V
TIBA V (A) V
TFC (R) L
TSTRBDH(R) H
TSTRBDH(W) L
TSTRBDL(W) H
TSTRBD(STRTROM)
TC(TIM CLK)
TEXT AD(FC B3)
TF(F), TI(I)
tr, tf
MMU Cache Hit
External Address Error
Error Correction Write Cycle
Arbiter Priority Transition
Address Ready
Parity Mode
Memory Protect Error
Write Protect Cache Hit
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT Address Valid (Miss)
Clock to EXT Address Valid (Miss)
Ready Data
Ready Data
Ready Data
Address Valid
Address Valid
Read Strobes
Read Strobes
Write Strobes
Write Strobes
Start-Up ROM
Timer Clock
Extended Address Set-Up
Edge Sensitive Pulse Width
Clock Rise and Fall Time
20 MHz
MIN
MAX
30 MHz
MIN
MAX
25
25
30
35
30
34
50
25
25
40
40
25
25
32
30
28
16
28
29
31
24
24
26
26
26
30
10
5
40 MHz
MIN
MAX
23
18
24
22
21
28
43
18
20
42
33
33
20
27
25
23
12.5
19
20
21
15
15
18
18
18
23
23
16
23
18
17
25
40
16
18
40
30
30
20
23
25
21
11.5
16
19
20
12
12
15
15
15
20
23
20
25
25
25
30
45
20
22
45
35
35
20
30
25
24
13
22
21
22
18
18
20
20
20
25
10
5
5
35 MHz
MIN
MAX
10
5
5
10
5
5
5
Units = ns
Note
All timing parameters are composed of Three elements. The first "T" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "E" or the falling edge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Document # MICRO-10 REV B
Page 9 of 34
PACE 1757 M/ME
MINIMUM WRITE BUS CYCLE TIMING DIAGRAM
Document # MICRO-10 REV B
Page 10 of 34
PACE 1757 M/ME
MINIMUM READ BUS CYCLE TIMING DIAGRAM
Document # MICRO-10 REV B
Page 11 of 34
PACE 1757 M/ME
MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM
Document # MICRO-10 REV B
Page 12 of 34
PACE 1757 M/ME
ADDRESS BUS AND STROBES
Note:
All time measurements on active signals relative to 1.5V levels.
Document # MICRO-10 REV B
Page 13 of 34
PACE 1757 M/ME
RDYD TIMING
TEST END TIMING1
Notes:
1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the IOW bus cycle, the
XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the
processor. As from the end of STRBD in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two
fetch cycles from the "old PC" (from addresses XXXX & XXXX +1). The data will be taken from system memory (because TEST END is
asserted) but both the address and data are irrelevant. Following that, IC will start filling the pipe from address 0000 hex and 0001 hex, now
from the system memory to start user's program execution.
2. All time measurements on active signals relate to 1.5V levels.
Document # MICRO-10 REV B
Page 14 of 34
PACE 1757 M/ME
STRT ROM
IB Bus Output (0:15)
EX AD ER
Extended Addresses (0:1)
Error Correction (Write Cycle)
Memory Protect Error
Error Correction (Read Cycle)
Ready Address
Note:
All time measurements on active signals relative to 1.5V levels.
Document # MICRO-10 REV B
Page 15 of 34
PACE 1757 M/ME
MMU Cache Hit
External Address Error
Note:
All time measurements on active signals relative to 1.5V levels.
Document # MICRO-10 REV B
Page 16 of 34
PACE 1757 M/ME
MMU Cache Miss Cycle (WA = 0)
MMU Cache Miss Cycle (WA > 0)
* The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT GLAG. (See BPU Description). T = 1 Clock Period.
Note: All time measurements on active signals relate to 1.5V levels.
Document # MICRO-10 REV B
Page 17 of 34
PACE 1757 M/ME
TRIGO RST Discrete Timing
DMA EN Discrete Timing
Normal Power Up Discrete Timing
XIO Operations
Document # MICRO-10 REV B
SNEW Discrete Timing
Page 18 of 34
PACE 1757 M/ME
External Faults and Interrupts Timing
Edge-sensitive interrupts and faults (SYSFLT0,
SYSFLT1) min. pulse width
Level-sensitive interrupts
Note: tC(IR)X max = 35 clocks
Level-sensitive faults
CON REQ
Note:
All time measurements on active signals relative to 1.5V levels.
Document # MICRO-10 REV B
Page 19 of 34
PACE 1757 M/ME
Low Priority to High Priority Transition
Bus Arbitrator High Priority to Low Priority Transition
Note:
All time measurements on active signals relative to 1.5V levels.
Document # MICRO-10 REV B
Page 20 of 34
PACE 1757 M/ME
BUS ACQUISITION
Note:
A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is asserted and the BUS is not locked (BUS
LOCK is HIGH).
SWITCHING TIME TEST CIRCUITS
Standard Output (Non-Three-State)
Parameter
Three-State
VO
VMEA
tPLZ
≥ 3V
0.5V
tPHZ
0V
VCC – 0.5V
tPXL
VCC/2
1.5V
tPXH
VCC/2
1.5V
Document # MICRO-10 REV B
Page 21 of 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
Description
CPU CLK
CPU clock
A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty
cycle. This is a common input to all 3 devices.
RESET
Reset
An active LOW input that initializes the device. Input to the P1750A/AE,
P1753 and P1754.
CON REQ
Console request
An active LOW input that initiates console operations after completion of
the current instruction. Input to the CPU.
INTERRUPT INPUTS
Mnemonic
Name
Description
PWRDN INT
Power down interrupt
An interrupt request input that cannot be masked or disabled. This signal
is active on the positive going edge or the high level, according to the
interrupt mode bit in the configuration register of the P1750A/AE.
USR0INT USR5INT
User interrupt
Interrupt request input signals that are active on the positive going edge
edge or the high level, according to the interrupt mode bit in the configuration
register of the P1750A/AE.
IOL1INT IOL2INT
I/O Level Interrupts
Active HIGH interrupt requests that can be used to expand the number
of user interrupts. Inputs to the P1750A/AE interrupt register.
Mnemonic
Name
Description
UNRCV ER
Unrecoverable error
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable. A signal from the CPU.
MAJ ER
Major error
An active HIGH output that indicates the occurrence of an error classified
as major. A signal from the CPU.
ERROR CONTROL
DISCRETE CONTROL
Mnemonic
Name
Description
NML PWRUP
Normal power up
An active HIGH output that is set when the CPU has successfully
completed the built-in self test in the initialization sequence. It can be reset
by the I/O command RNS.
SNEW
Start new
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle. This signal is issued by the CPU.
TRIGO RST
Trigger-go reset
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
STRT ROM
Start Up Rom
An output follow the execution of the ESUR and DSUR, I/O commands as
defined in MIL-STD-1750A. It will be at the logical level "1" after executing
ESUR and at the logical "0" level after executing DSUR. Initially, it defaults
to a "1" on the P1754.
DMA EN
Direct memory
Access enable
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
Document # MICRO-10 REV B
Page 22 of 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL
Mnemonic
Name
Description
TEST ON
System Test Enable
An active-LOW input, used to enable the execution of the System Test
built into the P1754, immediately after completetion of the PACE 1750 A/
AE initialization and before fetching any instructions from the user's
program.
TEST END
System Test End
An active-HIGH output indicating whether the PACE 1754 System Test
has been completed. Whenever the System Test is disabled by the TEST
ON signal, the TEST END output will be at a logical "1" immediately after
reset is removed.
SC0-SC4
System Configuration
Inputs
Inputs which are buffered onto IB0-IB4 when executing an I/O Read
from I/O address 8410 (hex).
D/I
Data or instruction
An output signal that indicates whether the current bus cycle access is for
Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not
assigned to the CPU. This line can be used as an additional memory
address bit for systems that require separate data and program memory.
R/W
Read or write
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOW indicates a write or output operation. The signal is three-state during
bus cycles not assigned to the CPU.
M/IO
Memory or I/O
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to the CPU.
RDYA_IN
Address ready In
An active HIGH input to the CPU that can be used to extend the address
phase of a bus cycle. When RDYA_IN is not active, wait states are
inserted by the P1750A/AE to accomodate slower memory or I/O devices.
This line is usually connected to RDYA_OUT unless the memory interface
logic requires the two RDYA signals remain discrete as an input and
output.
RDYA_OUT
Address Ready Out
An active HIGH output from the COMBO that indicates that there are no
wait states requested when STRBA is active. Wait states are inserted
when this signal becomes inactive during STRBA. Up to 3 wait states can
be inserted by programming an internal register. Three wait states are
inserted after reset (default).
RDYD
Data ready
An active HIGH signal to the CPU from the PIC that extends the data
phase of a bus cycle. When RDYD is not active, wait states are inserted
by the P1750A/AE to accomodate slower memory or I/O devices.
Document # MICRO-10 REV B
Page 23 of 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
BUS ARBITRATION
Mnemonic
Name
Description
BUS REQ
Bus request
An active LOW output that indicates the CPU requires the bus. It
becomes inactive when the CPU has acquired the bus and started the
bus cycle.
BUS GNT
Bus grant
An active LOW input from an external arbiter that indicates the CPU
currently has the highest priority bus request. If the bus is not used and
not locked, the CPU may begin a bus cycle, commencing with the next
CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), threestating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA,
STRBD), and all the other lines that go three-state when this CPU does
not have the bus.
BUS BUSY
Bus busy
An active LOW, bidirectional signal used to establish the beginning and
end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used
for sampling bits into the fault register. It is three-state in bus cycles not
assigned to this CPU. However, the CPU monitors the BUS BUSY line
for latching non-CPU bus cycle faults into the fault register.
BUS LOCK
Bus lock
An active low, bi-directional signal used to lock the bus for successive
bus cycles. During non-locked bus cycles, the BUS LOCK signal mimics
the BUS BUSY signal. It is three-state during bus cycles not assigned to
the CPU. The following instructions will lock the bus: INCM, DECM, SB,
RB, TSB, SRM, STUB and STLB.
BUS GNT0 BUS GNT3
Bus Grant
Active-LOW outputs from the PIC indicating which master was granted
the BUS. It remains active during BUS LOCK unless a higher master
request occurs, which resets it. However, the higher master will be
granted the BUS only after the current master's BUS LOCK releases the
BUS.
BUS REQ0 BUS REQ3
Bus Request
Active-LOW inputs to the PIC that indicate a requirement for the BUS
from the 4 masters on the bus. The master assigned to pin BUS REQ0
has the highest priority. The master assigned to pin BUS REQ3 has the
lowest priority.
Document # MICRO-10 REV B
Page 24 of 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
FAULTS AND FLAGS
Mnemonic
Name
Description
MEM PRT ER
Memory Protect Error
An active-LOW input generated by the MMU or BPU, or both, during
attempted writes to protected memory. It is sampled by the BUS BUSY
signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus
cycle). The error is generated in one of the following conditions: a
mismatch in the access keys in the MMU page, an access to an execution
protected page during instruction cycles, an access to a write protected
page during data cycles or an access to a page write protected by the
BPU.
MEM PAR ER
Memory Parity Error
An active LOW signal which is sampled by the BUS BUSY signal into bit
2 of the CPU's Fault Register. It signals an error on the Data Bus during
a memory cycle. Two detection modes can be selected by programming
the control register of the MMU/COMBO: EDAC mode (6 Hamming code
parity bits) or single bit parity mode (even or odd parity). The signal is
inactive when none of the above modes are selected (default after reset).
EXT ADR ER IN
External Address
Error In
An active-LOW input sampled by the BUS BUSY signal into the CPU
Fault Register (bit 5 or 8) depending on the cycle (memory or I/O).
EXT ADR ER OUT External Address
Error Out
An active LOW output which signals to the CPU and memory interface
logic that an unimplemented memory or illegal I/O access has taken
place.
SYSFLT0 SYSFLT1
System Fault 0,
System Fault 1
Asynchronous, positive edge sensitive inputs that set bit 7 (SYSFLT0)
or bits 13 and 15 (SYSFLT1) in the P1750A/AE Fault Register.
EX AD ER /
SING ERR
Illegal Address Error /
Single Error
An active LOW output from the PIC indicating an illegal address error
when referencing memory or I/O. It becomes an active HIGH input called
SINGLE ERROR for handshaking with the P1753 when the PIC is
programmed to support EDAC. Default state after reset is high impedance.
WR PROT /
PROT FLAG
Write Protected /
Protection Flag
Either an active LOW output (WR PROT, following STRBD timing)
during legal memory write cycles when no protection occurs, or an active
high (PROT FLAG) signal indicating a protection error in a write cycle.
Either mode can be selected by programming the COMBO control
register. Default mode after reset is Write Protected.
ME PA ER /
RAMDIS
Memory Parity Error
An active LOW output indicating a Parity error when reading from
memory. It becomes an active HIGH output called RAM DISABLE for
handshaking with the P1753 when the PIC is programmed to support
EDAC.
TC
Terminal Count
An active HIGH output from the PIC indicating a bus time out or a
watchdog trigger.
Document # MICRO-10 REV B
Page 25 of 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
STATUS BUS
Mnemonic
Name
Description
AK0 - AK3
Access key
Active HIGH outputs corresponding to the AK field of the processor status
word used to match the Access Lock in the MMU for memory accesses
(a mismatch will cause the MMU to pull the MEM PRT ER signal LOW),
and also indicate the processor state (PS). Priveledged instructions can
be executed with PS=0 only. These signals are tri-state for bus cycles not
assigned to this CPU
AS0 - AS3
Address state
Active HIGH outputs corresponding to the AS field of the processor status
word that selects the page register group in the MMU. In the DMA physical
demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant
bits of the physical address for use in the BPU function. These signals are
tri-state in bus cycles not assigned to this CPU.
INFORMATION BUS
Mnemonic
Name
Description
IB0 - IB15
Information bus
A bi-directional time-multiplexed address/data BUS. IB0 is the most
significant bit.
EDC0-EDC5
Error Detection /
Correction Bus
An active HIGH output BUS used for detection of errors on the data BUS
(IB0-IB15) and correction of single errors. When working in parity mode
EDC0 is the parity bit. EDC1-EDC5 are undefined in this case.
A(0:1) /
EXT ADR(0:1)
A(2:15)
Address Bus
An active HIGH output BUS from the PIC. Contains the address of the
current bus cycle as latched by the end of STRBA. In system configurations
including the MMU function, the only active lines during memory cycles
are A(4:15). In this example, A(2:3) are high impedance (don't care) and
A(0:1) turn into inputs called Extended Addresses, EXT AD (0:1). In this
situation, these two lines, supplied by the MMU, will be used to operate the
programmable ready generation during bus cycles.
EXT ADR0 EXT ADR7
Extended Address
Bus
A bi-directionaly active HIGH BUS. In CPU cycles, it is an output BUS
that is used to select one of 256 pages, 4K words each, expanding the
direct addressing space to 1M word. In DMA cycles, indicated by DMAACK being active, it is also an output BUS except when programmed for
the physical demultiplexed DMA mode. In this example, it becomes an
input to receive the eight most significant bits of the DMA physical address
for use in the BPU function.
Document # MICRO-10 REV B
Page 26 of 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
BUS STROBES AND QUALIFIERS
Mnemonic
Name
Description
STRBA (note 1)
Address Strobe
An active HIGH output that can be used to externally latch the contents
of IB(0:15) into the address latches of the PIC and MMU at the HIGH to
LOW transition of the strobe. The signal is tristate during bus cycles not
assigned to this CPU. It is issued by the CPU and input to the MMU and
PIC.
STRBD (note 2)
Data Strobe
An active LOW output used to read or write data from the PIC as well as
to strobe data in memory and XIO cycles. This signal is tri-state during
bus cycles not assigned to this CPU. It is interconnected in the same
manner as STRBA.
MEMW
Memory Write
Strobe
An active LOW output produced in memory write cycles by the PIC.
MEMR
Memory Read Strobe
An active LOW output produced by the P1754 in memory read cycles.
IOW
I/O Write Strobe
An active LOW output produced by the P1754 in output write cycles.
IOR
I/O Read Strobe
An active LOW output produced by the P1754 during input read cycles.
STRB EN
Strobe Enable
An active LOW input, enabling the active state of the address outputs of
the P1754 and the MEMR, MEMW, IOR and IOW outputs. When a logic
"1" (if enabled by bits EST and EAD of the control register) it will
correspondingly tri-state the above signals.
INTA
Interrupt Acknowledge An active LOW output produced during any interrupt sequence
Strobe
corresponding to an output write to address 1000 (Hex).
DMA ACK
DMA Acknowledge
An active HIGH input from the DMA controller to the P1753 which
indicates a DMA cycle. Used to select the DMA table in the BPU memory
for protection. For example, this could allow the DMA channel to update
the program which could be write protected from the processor. In the
physical DMA mose, it will cause the Extended Address Liones (EXT
ADR0-7) to become inputs providing BPU protection of the DMA transfers.
EX RDY
External Data Ready
An active HIGH output from the MMU that indicates no wait states are
requested. It becomes inactive for one clock (inserting one wait state)
whenever a memory page different than the current one is accessed (e.g.
a cache miss).
EX RDY1
External Data
Ready 1
An active LOW input to the PIC from the memory interface logic which at
a logical "1" overrides the internal RDYD generation and forces it to a
logical "0".
Note 1: One internal pulldown resistor is provided at the STRBA input. The nominal value is 40K Ohm and the maximum range is 20K Ohm to
80K Ohm. In designs with TTL devices loading STRBA, an additional external resistor may be required.
Note 2: One internal pullup is provided at the STRBD input. The nominal value is 40K Ohms and the maximum range is 20K-80K Ohms.
Document # MICRO-10 REV B
Page 27 of 34
PACE 1757 M/ME
COMBO REGISTER MAP
CONTROL REGISTER (1F50/9F50)
0
1
2
3
4
QR1
QR2
QR3
QR4
ODD
CONTROL REGISTER 1 (1F51/9F51)
0
1
2
3
4
WA0
WA1
SPI
RES* PEG
5
6
7
8
9
10
11
12
13
14
15
EEI
EED
EPR
SPD
WPT
EB1
EB2
EIO
GPT
DMX
DLP
5
6
7
8
9
10
11
12
13
14
15
12
13
14
15
13
14
15
13
14
15
14
15
IDL
RESERVED
UNIMPLEMENTED MEMORY REGISTER 1 (1F55/9F55)
0
1
2
3
4
5
6
7
8
9
10
BL1 LO
BL1 HI
UNIMPLEMENTED MEMORY REGISTER 2 (1F56/9F56)
0
1
2
3
4
5
6
7
8
9
10
BL2 LO
X
X
X
X
X
X
X
X
X
12
9
10
11
12
LAST SEQUENTIAL PIO OUTPUT COMMAND
FIRST UNIMPLEMENTED INPUT COMMAND (1F58/9F58)
0
1
2
3
4
5
6
7
X
11
BL2 HI
FIRST UNIMPLEMENTED OUTPUT COMMAND (1F57/9F57)
0
1
2
3
4
5
6
7
8
X
11
X
8
9
10
11
12
13
LAST SEQUENTIAL PIO INPUT COMMAND
FIRST FAILING ADDRESS REGISTER (9F59)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
14
15
14
15
FIRST FAILING PHYSICAL ADDRESS - PADR (4:19)
FIRST FAILING DATA REGISTER (9F5A)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
10
11
12
13
FIRST FAILING DATA WORD
MEMORY FAULT STATUS REGISTER (A00D)
0
1
2
3
4
5
6
LPA
7
RESERVED
8
9
ID
AS
* Reserved
Document # MICRO-10 REV B
Page 28 of 34
PACE 1757 M/ME
COMBO REGISTER MAP DEFINITIONS
CONTROL REGISTER (1F50/9F50)
(Default = 00C6H)
QR1
Enable error detection/correction or parity
checking/generation for memory addresses
00000H-3FFFFH.
QR2
Enable error detection/correction or parity
checking/generation for memory addresses
40000H-7FFFFH
QR3
Enable error detection/correction or parity
checking/generation for memory addresses
80000H-BFFFFH.
QR4
Enable error detection/correction or parity
checking/generation for memory addresses
C0000H-FFFFFH.
ODD Enable odd parity, 1 = ODD, 0 = EVEN
EEI
Enable error detection/correction (EDAC) on
instruction fetch only.
EED
Enable error detection/correction (EDAC) on
operand (data) fetch only.
EPR
Enable parity detection function. (If both
EPR and either EEI or EED are enabled, EEI
or EED will take preference.)
SPD
Enable 1 wait state on MMU cache miss
cycle (1 = 1 WAIT, 0 = NO WAIT).
WPT Enable protected write strobe (WR PROT
PIN).
1: WR PROT = write protected strobe
0: WR PROT = write protect level
(1 = write protect memory)
EB1
Enable block 1 of unimplemented memory
(as defined in unimplemented memory
register 1).
EB2
Enable block 2 of unimplementd memory (as
defined in unimplemented memory register
2).
EIO
Enable illegal PIO detection (as defined in
last implemented input and output registers,
and MIL-STD-1750A reserved I/O space).
GPT
Enable global memory protect (Set by
RESET, and reset by I/O command 4003).
DMX Demultiplexed Address/data Bus in DMA
cycles.
DLP
Logical/Physical DMA (1 = LOGICAL, 0 =
Physical).
CONTROL REGISTER 1 (1F51)
(Default = C3FFH)
WA0/ Number of WAIT STATES on RDYA
WA1
SPI
Enable illegal PIO detection for MILSTD1750A spare I/O spaces.
PEG
Determines what is generated when both
EDAC and parity checks are disabled.
IDL
Enables/disables the genertion of an idle
cycle betwee BUS REQ and BUS GNT,
during read cycles, allowing for one
additional clock cycle to release the IB.
UNIMPLEMENTED MEMORY REGISTER 1 (1F55)
BL1 LO Low boundary of unimplemented block 1 of
memory.
BL1 HI High boundary of unimplemente block 1 of
memory.
UNIMPLEMENTED MEMORY REGISTER 2 (1F56)
BL2 LO Low boundary of unimplemented block 2 of
memory.
BL2 HI High boundary of unimplemented block 2 of
memory.
FIRST UNIMPLMENTED OUTPUT COMMAND
REGISTER (1F57)
BITS 0:5
BITS 6:15
Not used.
First unused sequential PIO output
command.
FIRST UNIMPLMENTED INPUT COMMAND
REGISTER (1F58)
BITS 0:5
BITS 0:6
Not used.
First unused sequential PIO input
command.
FIRST FAILING ADDRESS REGISTER (1F59)
PADR (4:19) 16 LSB of the physical address of the
first failure.
FIRST FAILING DATA REGISTER (1F5B)
BITS 0:15
"1" indicates the position of the wrong/
corrected bit in the data word.
MEMORY FAULT STATUS REGISTER (A00D)
LPA
ID
AS
Document # MICRO-10 REV B
Page address within the group.
Instruction/data
Group address.
Page 29 of 34
PACE 1757 M/ME
PIC REGISTER MAP
CONTROL REGISTER (1F40, 9F40)
0
1
2
3
4
PR1
PR2
PR3
PR4
STATUS REGISTER (9F41)
0
1
2
3
CPU
CMB
PIC
5
6
7
8
9
10
11
12
13
14
15
ODD
EST
EAD
EXR
SPI
CNF
EB1
EB2
EIO
LIO
LME
0
4
5
6
7
8
9
10
11
12
13
14
15
STB
ADR
TWD
TBT
RESERVED
MEMORY READY PROGRAM REGISTER (1F42, 9F42)
0
1
2
3
4
5
6
7
MEM Q1
8
MEM Q2
I/O READY PROGRAM REGISTER (1F43, 9F43)
0
1
2
3
4
5
6
IO Q1
RESERVED
9
5
CLOCK FREQUENCY (MHZ)
WATCH DOG TIMER (1F45, 9F45)
0
1
2
3
4
5
11
12
MEM Q3
7
8
9
IO Q2
PROGRAM REGISTER (1F44, 9F44)
0
1
2
3
4
10
10
7
8
EBT
SBT
6
7
9
10
11
9
14
15
12
13
14
15
IO Q4
11
EWD SWD
8
13
MEM Q4
IOQ3
6
IFL
12
13
14
15
RESERVED
10
11
12
13
14
15
10
11
12
13
14
15
WATCHDOG SETUP COUNT
UNIMPLEMENTED MEMORY REGISTER (1F46, 9F46)
0
1
2
3
4
5
6
7
BL1 LO
8
BL1 HI
BL2 LO
FIRST UNIMPLEMENTED OUTPUT COMMAND (1F47, 9F47)
0
1
2
3
4
5
6
7
8
X
X
X
X
X
X
X
X
X
X
9
10
BL2 HI
11
12
13
14
15
14
15
14
15
FIRST UNIMPLEMENTED OUTPUT COMMAND
FIRST UNIMPLEMENTED INPUT COMMAND (1F48, 9F48)
0
1
2
3
4
5
6
7
X
9
X
8
9
10
11
12
13
FIRST UNIMPLEMENTED INPUT COMMAND
FIRST FAILING ADDRESS REGISTER (9F49)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
FIRST FAILING ADDRESS
Document # MICRO-10 REV B
Page 30 of 34
PACE 1757 M/ME
PIC REGISTER MAP DEFINITIONS
CONTROL REGISTER (Default = 0000)
PR1
Enable Parity Checking/Generation for
Memory Addresses 0000-3FFF.
PR2
Enable Parity Checking/Generation for
Memory Addresses 4000-7FFF.
PR3
Enable Parity Checking/Generation for
Memory Addresses 8000-BFFF.
PR4
Enable Parity Checking/Generation for
Memory Addresses C000-FFFF.
ODD Enable ODD Parity.
EST
Enable Three State Control on PIC
Generated Strobes: IOR, IOW, MEMR,
MEMW.
EAD
Enable Three State Control on PIC
Generated Address: A0-A15.
EXR
Extends ready generation over the full I/O
space when = 1. (Default = 0)
SPI
Enables IILEGAL PIO detection for MIL-STD1750A spare I/O spaces. 1 = Spare I/O legal,
0 = Default = spare I/O illegal.
CNF
EDAC Function on MMU/COMBO; 1 = used,
0 = not used.
EB1
Enable Block 1 of Unimplemented Memory,
as Defined in the Unimplemented Memory
Register.
EB2
Enable Block 2 of Unimplemented Memory,
as Defined in the Unimplemented Memory
Register
EIO
Enable illegal PIO Detection, as defined in
Last Implemented Input and Output
Registers.
LIO
Enable Long I/O Ready Generation, 1ms to
15ms, I/O Addresses 0000-00FF, 800080FF.
LME
Enable Long Memory Ready Generation,
1ms to 15ms, Addresses 0000-3FFF.
STATUS REGISTER (Default = 0000)
CPU
CPU Passed PIC System Test.
CMB COMBO Chip Passed PIC System Test.
PIC
PIC Chip Passed PIC System Test.
STB
Reserved.
ADR
Reserved.
TWD Watch Dog reached terminal count.
TBT
Bus Time-out reached terminal count.
IFL
Interrupt Flag-Shows the last interrupt I/O
command implemented in the software.
I/O READY PROGRAM REGISTER
(Default = Undefined)
IO Q1
Lower section number of wait states.
IO Q2
Second section number of wait states.
IO Q3
Third section number of wait states.
IO Q4
Upper section number of wait states.
PROGRAM REGISTER (Default = 0000)
CFB
0:5, Clock Frequency Bits (MHz).
EBT
Enable Bus Time-out Function.
SBT
Select Bus Time-out Limit; 1 = 128
Cycles, 0 = 64 Cycles.
EWD
Enable Watch Dog Function.
SWD
Select Watch Dog Clock, 1 = 1KHz, 0 =
1MHz.
WATCH DOG TIMER REGISTER (Default = 0000)
BITS
0:15, Watch Dog set-up Count.
UNIMPLEMENTED MEMORY REGISTER
(Default = Undefined)
BL1 LO
BL1 HI
BL2 LO
BL2 HI
Low boundary of unimplemented block
1 of memory.
High boundary of unimplemented block
1 of memory.
Low boundary of unimplemented block
2 of memory.
High boundary of unimplemented block
2 of memory.
FIRST UNIMPLEMENTED OUTPUT COMMAND
REGISTER (Default = Undefined)
BITS 0:5
Not used.
BITS 6:15 First unused sequential PIO output
command.
FIRST UNIMPLEMENTED INPUT COMMAND
REGISTER (Default = Undefined)
BITS 0:5
Not used.
BITS 6:15 First unused sequential PIO input
command.
FIRST FAILING REGISTER (Default = Undefined)
BITS 0:15 16 LSB of the physical address of the
first failure.
MEMORY READY PROGRAM REGISTER
(Default = FFFF)
MEM Q1
Lower Block number of wait states.
MEM Q2
Second Block number of wait states.
MEM Q3
Third Block number of wait states.
MEM Q4
Upper Block number of wait states.
Document # MICRO-10 REV B
Page 31 of 34
PACE 1757 M/ME
PACKAGE OUTLINE
Document # MICRO-10 REV B
Page 32 of 34
PACE 1757 M/ME
1757M/ME 144-LEAD QUAD FLATPACK OUTLINE
Straight Leads
A
130
A1
N/A
± 10
Gullwing Leads
175
± 20
25
±5
b
8
±2
8
±2
c
6
±2
6
±1
D
1750
± 15
1450
± 10
D1
1150
± 12
1150
± 12
D2
875
REF
875
REF
E
1750
±5
1450
± 10
E1
1150
± 12
1150
± 12
E2
875
REF
875
REF
L1
N/A
75
± 15
L2
N/A
25
±5
L
300
150
± 10
R1
N/A
25
±2
R2
N/A
25
±2
O1
N/A
0°
7°
O2
N/A
0°
7°
G
8
8
±4
N
144
144
±5
±4
ORDERING INFO
Document # MICRO-10 REV B
Page 33 of 34
PACE 1757 M/ME
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
MICRO-10
PACE1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
ORIG
May-89
RKK
New Data Sheet
A
Jul-04
JDB
Added Pyramid logo
B
Sep-05
JDB
Re-created electronic version
Document # MICRO-10 REV B
DESCRIPTION OF CHANGE
Page 34 of 34