HV2701 Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors Features General Description ► ► ► ► ► ► ► ► ► ► ► ► ► The Supertex HV2701 is a low charge injection, 16-channel, high voltage, analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. HVCMOS technology for high performance Integrated bleed resistors on the outputs 16 Channels of high voltage analog switch 3.3V input logic level compatible 20MHz data shift clock frequency Very low quiescent power dissipation-10µA Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages Input data is shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Applications ► ► ► ► Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Optical MEMS modules The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Latches DIN CLK 16-Bit Shift Register DOUT VDD GND LE CL Level Shifters Output Switches D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW14 D LE CL SW15 VNN VPP RGND HV2701 Pin Configuration Ordering Information 48 Package Options DEVICE 1 48-Lead LQFP (FG) (7x7x1.4mm body, 0.50mm pitch) HV2701 HV2701FG-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings 48-Lead LQFP Package (FG) Parameter VDD Logic supply -0.5V to +7V VPP-VNN differential supply VPP Positive supply VNN Negative supply Logic input voltage 220V -0.5V to VNN+200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP Analog signal range Peak analog signal current/channel Storage temperature 3.0A -65°C to 150°C Power dissipation 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Recommended Operation Conditions Symbol (top view) Value Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-topeak VNN+10V to VPP- 0V TA Operating free air temperature 0°C to 70°C -40V to –160V Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powereddown last. 2. VSIG must be within VNN and VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 2 Product Marking Top Marking YYWW HV2701FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 48-Lead LQFP Package (FG) HV2701 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) 0°C Sym RONS +25°C +70°C Parameter Small signal switch on-resistance Units Conditions Min Max Min Typ Max Min Max - 30 - 26 38 - 48 ISIG = 5.0mA - 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 Ω ISIG = 5.0mA VPP = +100V VNN = -100V - 18 - 18 24 - 27 - 23 - 20 25 - 30 ISIG = 5.0mA - 22 - 16 25 - 27 ISIG = 200mA Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch on-resistance - - - 15 - - - Ω VSIG= VPP -10V, ISIG = 1.0A RINT Value of output bleed resistor - - 20 35 50 - - KΩ Output Switch to RGND IRINT = 0.5mA ISOL Switch off leakage per switch* - 5.0 - 1.0 10 - 15 µA VSIG = VPP -10V and VNN +10V DC offset switch off* - 300 - 100 300 - 300 mV DC offset switch on* - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1% fSW Output switching frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.5 - 5.5 ∆RONS VOS IPP INN Average VPP supply current Average VNN supply current ISIG = 200mA VPP = +40V VNN = -160V VPP = +160V VNN = -40V No Load Duty cycle = 50% VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V - 4.0 - - 5.0 - 5.5 VPP = +160V VNN = -40V - 6.5 - - 7.0 - 8.0 VPP = +40V VNN = -160V - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 mA VPP = +100V VNN = -100V All output switches are turning On and Off at 50KHz with no load. VPP = +160V VNN= -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD-0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 - - 10 - 10 pF --- * See Test Circuits on page 5 3 HV2701 AC Electrical Characteristics (over recommended operating conditions, VDD= 5.0V, tR = tF ≤ 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted) Sym Parameter tSD Set up time before LE rises tWLE Time width of LE tDO Clock delay time to data out tWCL Time width of CL tSU Set up time data to clock tH Hold time data from clock fCLK Clock frequency tR,tF 0°C +25°C +70°C Min Max Min Typ Max Min Max 25 - 25 - - 25 - 56 - - 56 - 56 - 12 - - 12 - 12 - 50 100 50 78 100 50 100 15 40 15 30 40 15 40 55 - 55 - - 55 - 21 - - 21 - 21 - 7 - - 7 - 7 - 2 - 2 - - 2 - - 8 - - 8 - 8 Units ns ns ns ns ns ns Conditions --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD= 5.0V --VDD= 3.0V VDD= 5.0V VDD= 3.0 or 5.0V VDD= 3.0V - 20 - - 20 - 20 MHz Clock rise and fall times - 50 - - 50 - 50 ns ---- TON Turn ON time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP-10V, RLOAD = 10KΩ TOFF Turn OFF time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP-10V, RLOAD = 10KΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 - - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle dv/dt Maximum VSIG slew rate KO Off isolation* KCR Switch crosstalk* IID Output switch isolation diode current VDD= 5.0V VPP = +40V, VNN = -160V v/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB f = 5.0MHz, 1KΩ//15pF load f = 5.0MHz, 50Ω load CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz - - - - 150 - - - - - - 150 - - - - - - 150 - - VPP = +160V, VNN = -40V, RLOAD = 50Ω - - - 820 - - - VPP= +40V, VNN= -160V, VSIG= 0V - - - 600 - - - - - - 350 - - - +VSPK -VSPK +VSPK -VSPK Output voltage spike* +VSPK -VSPK QC Charge injection* * See Test Circuits on page 5 4 VPP = +40V, VNN = -160V, RLOAD = 50Ω mV pC VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP= +100V, VNN= -100V, VSIG= 0V VPP= +160V, VNN= -40V, VSIG= 0V HV2701 HV2701 Test Circuits VPP-10V VPP-10V Open PP RGND PP RGND PP DD RGND PP DD PP DC Offset Switch ON/OFF Switch Off Leakage per Switch PP DD TURN (TON/TOFF) ON/OFF TIME RGND RGND RGND PP PP PP DD PP PP DD OFF Isolation Output Switch Isolation Diode Current PP Switch Crosstalk RGND RGND PP PP PP DD Q = 1000pF x ΔVOUT Charge Injection PP DD Output Voltage Spike 5 DD HV2701 Logic Function Table D0 D1 L D7 D8 D15 LE CL SW0 SW1 SW7 SW8 - - - - L L OFF - - - - H - - - - L L ON - - - - - L - - - L L - OFF - - - - H - - - L L - ON - - - - - - - - L L - - - - - - - - - - L L - - - - - - - L - - L L - - OFF - - - - H - - L L - - ON - - - - L - L L - - - OFF - - - H - L L - - - ON - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - L L L - - - - OFF - - - - H L L - - - - ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Notes: 1. 2. 3. 4. 5. 6. ... ... ... ... ... ... The 16 switches operate independently. Serial data is clocked in on the L to H transition of the CLK. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. DOUT is high when data in the shift register 15 is high. Shift registers clocking has no effect on the switch states if LE is high. The CL clear input overrides all other inputs. Logic Timing Waveforms DN DN+1 DATA IN 5 0% LE 50% DN -1 50% 50% t WLE t SD 50% CLOCK t SU 50% th t DO DATA O UT 50% t OFF V OUT (TYP ) OFF 90% 1 0% ON CLR t ON 5 0% 5 0% t WCL 6 ... ... SW15 - HV2701 Pin Configuration 48-Lead LQFP (FG) Pin # Function Pin # Function Pin # Function Pin # Function 1 NC 13 VNN 25 SW15B 37 SW10B 2 NC 14 NC 26 SW15A 38 SW10A 3 SW4B 15 VPP 27 SW14B 39 SW9B 4 SW4A 16 NC 28 SW14A 40 SW9A 5 SW3B 17 GND 29 SW13B 41 SW8B 6 SW3A 18 VDD 30 SW13A 42 SW8A 7 SW2B 19 DIN 31 SW12B 43 SW7B 8 SW2A 20 CLK 32 SW12A 44 SW7A 9 SW1B 21 LE 33 SW11B 45 SW6B 10 SW1A 22 CLR 34 SW11A 46 SW6A 11 SW0B 23 DOUT 35 NC 47 SW5B 12 SW0A 24 RGND 36 NC 48 SW5A NC = No Internal Connection 7 HV2701 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.4mm height (min), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) Gauge Plane L2 48 L 1 Seating Plane θ L1 b e Top View View B View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) A A1 A2 b D D1 E E1 1.40 0.05 1.35 0.17 8.80 6.80 8.80 6.80 NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 MAX 1.60 0.15 1.45 0.27 9.20 7.20 9.20 7.20 e L L1 L2 1.00 REF 0.25 BSC 0O 0.45 0.50 BSC 0.60 0.75 θ 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2701 B060707 8