STMICROELECTRONICS M41T80M6F

M41T80
Serial access Real Time Clock with alarm
Feature summary
■
Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■
32KHz crystal oscillator integrating load
capacitance (12.5pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■
Serial interface supports I2C bus (400kHz)
■
2.0 to 5.5V clock operating voltage
■
32KHz square wave on power-up to drive a
microcontroller in low power mode
■
Programmable (1Hz to 32KHz) square wave
■
Programmable Alarm and Interrupt function
■
Low operating current of 200µA
■
Operating temperature of –40 to 85°C
■
ECOPACK® package available
August 2006
8
1
SO8 (M)
8-pin SOIC
Rev 3
1/25
www.st.com
1
Contents
M41T80
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
3
2-Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Full-time 32kHz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Preferred power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
M41T80
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Preferred power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SO8 – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . 22
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
List of figures
M41T80
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
4/25
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO8 – 8 lead plastic small outline, 150 mils body width, package mechanical drawing. . . 22
M41T80
1
Summary description
Summary description
The M41T80 is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal
controlled). Eight registers (see Table 3: Clock register map on page 14) are used for the
clock/calendar function and are configured in binary coded decimal (BCD) format. An
additional 12 registers provide status/control of Alarm, 32kHz output, and Square Wave
functions. Addresses and data are transferred serially via a two line, bi-directional I2C
interface. The built-in address register is incremented automatically after each WRITE or
READ data byte.
Functions available to the user include a time-of-day clock/calendar, Alarm interrupts, 32kHz
output, and programmable Square Wave output. The eight clock address locations contain
the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second
in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41T80 is supplied in an 8-pin SOIC.
Figure 1.
Logic diagram
VCC
XI
IRQ/OUT/SQW
XO
M41T80
F32k
SCL
SDA
VSS
AI07005
Table 1.
Signal names
XI
Oscillator input
XO
Oscillator output
IRQ/OUT/SQW
Interrupt / output driver / square wave (open drain)
SDA
Serial data input/output
SCL
Serial clock input
F32k
32kHz square wave output (open drain)
VCC
Supply voltage
VSS
Ground
5/25
Summary description
Figure 2.
M41T80
8-pin SOIC connections
XI
XO
F32k(1)
VSS
1
2
3
4
M41T80
8
7
6
5
VCC
IRQ/OUT/SQW(1)
SCL
SDA
AI07006
1. open drain output.
Figure 3.
Block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
32KHz
OSCILLATOR
RTC W/ALARM
AF
IRQ/OUT/SQW(1)
SDA
SCL
I2C
INTERFACE
SQUARE WAVE
F32k(1)
AI07007
1. Open drain output
6/25
M41T80
2
Operation
Operation
The M41T80 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 Bytes
contained in the device can then be accessed sequentially in the following order:
2.1
●
1st Byte: tenths/hundredths of a second register
●
2nd Byte: seconds register
●
3rd Byte: minutes register
●
4th Byte: century/hours register
●
5th Byte: day register
●
6th Byte: date register
●
7th Byte: month register
●
8th Byte: year register
●
9th Byte: control register
●
10th Byte: 32kE bit
●
11th - 16th Bytes: alarm registers
●
17th - 19th Bytes: reserved
●
20th Byte: square wave register
2-Wire bus characteristics
The bus is intended for communication between different IC’s. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is High.
●
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
7/25
Operation
2.1.4
M41T80
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 4.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
8/25
M41T80
Operation
Figure 5.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
8
MSB
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
Figure 6.
Bus timing requirements sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
9/25
Operation
M41T80
Table 2.
AC characteristics
Parameter(1)
Sym
Min
Typ
Max
Units
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
600
ns
0
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:DAT(2)
Data setup time
100
ns
tHD:DAT
Data hold time
0
µs
tSU:STO
STOP condition setup time
600
ns
Time the bus must be free before a new
transmission can start
1.3
µs
tBUF
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where
noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of
the falling edge of SCL.
2.2
READ mode
In this mode the master reads the M41T80 slave after setting the slave address (Figure 8:
READ mode sequence). Following the WRITE Mode Control Bit (R/W=0) and the
Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ Mode Control Bit
(R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an Acknowledge
Bit to the slave transmitter. The address pointer is only incremented on reception of an
Acknowledge Clock. The M41T80 slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a Stop Condition or when the
pointer increments to any non-clock address (08h-13h).
Note:
This is true both in READ Mode and WRITE Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41T80
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 9: Alternative READ mode sequence).
10/25
M41T80
Figure 7.
Operation
Slave address location
R/W
SLAVE ADDRESS
1
A
LSB
MSB
START
1
0
1
0
0
0
AI00602
R/W
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
BUS ACTIVITY:
S
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
READ mode sequence
START
Figure 8.
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
R/W
SLAVE
ADDRESS
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
STOP
Alternative READ mode sequence
START
Figure 9.
AI00895
11/25
Operation
2.3
M41T80
WRITE mode
In this mode the master transmitter transmits to the M41T80 slave receiver. Bus protocol is
shown in Figure 10: WRITE mode sequence on page 12. Following the START condition
and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed
device that word address “An” will follow and is to be written to the on-chip address pointer.
The data word to be written to the memory is strobed in next and the internal address
pointer is incremented to the next address location on the reception of an acknowledge
clock. The M41T80 slave receiver will send an acknowledge clock to the master transmitter
after it has received the slave address see Figure 7: Slave address location on page 11 and
again after it has received the word address and each data byte.
SLAVE
ADDRESS
12/25
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. WRITE mode sequence
AI00591
M41T80
3
Clock operation
Clock operation
The M41T80 is driven by a quartz-controlled oscillator with a nominal frequency of
32,768Hz. The accuracy of the Real Time Clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The 20-byte Register Map (see Table 3: Clock register map on page 14) is used to both set
the clock and to read the date and time from the clock, in a binary coded decimal format.
Tenths/Hundredths of Seconds Minutes, and Hours are contained within the first four
registers.
Note:
A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain
the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month
and Years. The ninth clock register is the Control Register. Bit D7 of Register 01h contains
the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is
expected to spend a significant amount of time on the shelf, the oscillator may be stopped to
reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically
one second).
The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
3.1
Clock registers
The M41T80 offers 20 internal registers which contain Clock, Alarm, 32kHz, Flag, Square
Wave, and Control data. These registers are memory locations which contain external (user
accessible) and internal copies of the data (usually referred to as BiPORT™ cells). The
external copies are independent of internal functions except that they are updated
periodically by the simultaneous transfer of the incremented internal copy. The internal
divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a Stop Condition or when
the pointer increments to any non-clock address (08h-13h).
Clock and Alarm Registers store data in BCD. Control, 32kHz, and Square Wave Registers
store data in Binary Format.
13/25
Clock operation
M41T80
Clock register map(1)
Table 3.
Addr
D7
00h
D6
D5
D4
0.1 seconds
D2
D1
D0
0.01 seconds
10s/100s
of seconds
00-99
01h
ST
10 seconds
Seconds
Seconds
00-59
02h
0
10 minutes
Minutes
Minutes
00-59
03h
CEB
CB
Hours (24 hour format)
Century/
hours
0-1/00-23
04h
0
0
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 hours
0
0
0
10 date
0
Day of week
10M
10 years
08h
OUT
0
0
0
0
0
0
0
Control
09h
32kE
0
0
0
0
0
0
0
32kHz
0Ah
AFE
SQWE
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
0
AF
0
0
0
0
0
0
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
0
0
0
0
SQW
Alarm month
Al month
01-12
AI 10 date
Alarm date
Al date
01-31
AI 10 hour
Alarm hour
Al hour
00-23
Alarm 10 minutes
Alarm minutes
Al min
00-59
Alarm 10 seconds
Alarm seconds
Al sec
00-59
1. Keys:
ST = Stop Bit
0 = Must be set to '0'
32kE = 32kHz Enable Bit
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
RPT1-RPT5 = Alarm Repeat Mode Bits
AF = Alarm Flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
14/25
D3
Function/range BCD
format
M41T80
3.2
Clock operation
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second or repeat every
year, month, day, hour, minute, or second.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 4: Alarm repeat
modes shows the possible configurations. Codes not listed in the table default to the once
per second mode to quickly alert the user of an incorrect alarm setting.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set
(and SQWE is '0.'), the alarm condition activates the IRQ/OUT/SQW pin.
Note:
If the address pointer is allowed to increment to the Flag Register address, an alarm
condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a
different address. It should also be noted that if the last address written is the “Alarm
Seconds,” the address pointer will increment to the Flag address, causing this situation to
occur.
The IRQ/OUT/SQW output is cleared by a READ to the Flags Register as shown in Figure
Figure 11. A subsequent READ of the Flags Register is necessary to see that the value of
the Alarm Flag has been reset to '0.'
Figure 11. Alarm interrupt reset waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/OUT/SQW
AI07021
Table 4.
Alarm repeat modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
Once per second
1
1
1
1
0
Once per minute
1
1
1
0
0
Once per hour
1
1
0
0
0
Once per day
1
0
0
0
0
Once per month
0
0
0
0
0
Once per year
15/25
Clock operation
M41T80
Table 5.
Square wave output frequency
Square wave bits
3.3
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
-
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
Full-time 32kHz square wave output
The M41T80 offers the user a special 32kHz square wave function which defaults to output
on the F32k pin (Pin 3) as long as VCC is valid, and the oscillator is running (ST Bit = '0'). This
function is available within four seconds of initial power-up and can only be disabled by
setting the 32kE Bit to '0' or the ST Bit to '1.' If not used, the F32k pin should be disconnected
and allowed to float.
Note:
The F32k pin is an open drain which requires an external pull-up resistor.
3.4
Century bit
Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
16/25
M41T80
3.5
Clock operation
Output driver pin
When the AFE Bit and SQWE Bit are not set, the IRQ/OUT/SQW pin becomes an output
driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT
Bit) of address location 08h is a '0,' then the IRQ/OUT/SQW pin will be driven low.
Note:
The IRQ/OUT/SQW pin is an open drain which requires an external pull-up resistor.
3.6
Preferred power-on default
When powering the device up from ground (0V), the following register bits are set to a '0'
state: ST; AFE; and SQWE. The following bits are set to a '1' state: OUT and 32kE (see
Table 6: Preferred power-on default values on page 17).
Table 6.
Preferred power-on default values
Condition
Power-up(1)
ST
Out
AFE
SQWE
32kE
0
1
0
0
1
1. If VCC falls to a voltage, 0V < VCC < 2.0V, these bits should be rewritten by the user.
17/25
Maximum rating
4
M41T80
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 7.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature (VCC off, oscillator off)
VCC
Supply voltage
TSLD
(1) (2)
VIO
Lead solder temperature for 10 seconds
Input or output voltages
Value
Unit
–55 to 125
°C
–0.3 to 7
V
260
°C
–0.3 to Vcc+0.3
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total
thermal budget not to exceed 180°C for between 90 to 150 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total
thermal budget not to exceed 245°C for greater than 30 seconds).
18/25
M41T80
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Operating and AC measurement conditions (1)
Table 8.
Parameter
M41T80
Supply voltage (VCC)
2.0 to 5.5V
Ambient operating temperature (TA)
–40 to 85°C
Load capacitance (CL)
100pF
Input rise and fall times
≤50ns
Input pulse voltages
0.2VCC to 0.8 VCC
Input and output timing ref. voltages
0.3VCC to 0.7 VCC
1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC measurement I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 9.
Capacitance
Parameter(1) (2)
Symbol
CIN
COUT
tLP
(3)
Min
Max
Unit
Input capacitance
7
pF
Output capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
19/25
DC and AC parameters
Table 10.
DC characteristics
Symbol
Test condition(1)
Parameter
ILI
Input leakage current
ILO
Output leakage current
ICC1
Supply current
Min
Typ
Max
Unit
0V ≤VIN ≤VCC
±1
µA
0V ≤VOUT ≤VCC
±1
µA
3.0V
30
µA
5.5V
200
µA
3.0
µA
35
µA
2.4
µA
31
µA
Switch freq (SCL) = 400kHz
All inputs = VCC – 0.2V
Switch freq (SCL) = 0Hz
Supply current
(standby)
ICC2(2)
M41T80
32KE = 1 3.0V
or
SQWE = 1 5.5V
1.8
32KE = 0 3.0V
and
SQWE = 0 5.5V
1.5
VIL
Input low voltage
–0.3
0.3VCC
V
VIH
Input high voltage
0.7VCC
VCC + 0.3
V
VOL
Output low voltage
IOL = 3.0mA
0.4
V
Output low voltage
(open drain)(3)
IOL = 10mA
0.4
V
IRQ/out/SQW, F32k
5.5
V
Pull-up supply voltage
(open drain)
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).
2. At 25°C.
3. For IRQ/FT/OUT, RST, and 32kHz pins (Open Drain)
Table 11.
Sym
Crystal electrical characteristics
Parameter(1) (2)
fO
Resonant frequency
RS
Series resistance
CL
Load capacitance
Min
Typ
Max
32.768
Units
kHz
60
12.5
kΩ
pF
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning
Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS
can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T80. Circuit board layout considerations for the 32.768kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
20/25
M41T80
6
Package mechanical information
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
21/25
Package mechanical information
M41T80
Figure 13. SO8 – 8 lead plastic small outline, 150 mils body width, package
mechanical drawing
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 12.
SO8 – 8 lead plastic small outline, 150 mils body width, package
mechanical data
millimetres
inches
Symbol
Typ
Min
A
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
22/25
Max
1.04
0.041
M41T80
7
Part numbering
Part numbering
Table 13.
Ordering information scheme
Example:
M41T
80
M
6
E
Device type
M41T
Supply voltage and write protect voltage
80 = VCC = 2.0 to 5.5V
Package
M = SO8
Temperature range
6 = –40°C to 85°C
Shipping method
E = ECOPACK® package, standard package
F = ECOPACK® package, tape & reel 24mm packing
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
23/25
Revision history
8
M41T80
Revision history
Table 14.
Revision history
Date
Version
October 2002
1.0
First issue
15-Jun-04
2.0
Reformatted; add Lead-free information; update characteristics
(Table 7, Table 10, Table 13)
29-Aug-2006
24/25
3
Revision details
Changed document to new template; added new features in Feature
summary on page 1; updated Package mechanical data in
Section 6: Package mechanical information; small text changes for
entire document, ecopack compliant
M41T80
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
25/25