tel:13798484366 13798484366 TLC TLC156 EPROM/ROM-Based 8-Bit Microcontroller Series Devices Included in this Data Sheet: • TLC154/155/156/157 : EPROM devices • TLC154/155/156/157 : Mask ROM devices FEATURES • Only 42 single word instructions • All instructions are single cycle except for program branches which are two-cycle • 13-bit wide instructions • 8-bit wide data path • 5-level deep hardware stack • Operating speed: DC-20 MHz clock input DC-100 ns instruction cycle Device Pins # I/O # EPROM/ROM (Byte) RAM (Byte) TLC154 18 12 512 49 TLC155 28 20 512 48 TLC156 18 12 1K 49 28 TLC157 20 2K 96 • Direct, indirect addressing modes for data accessing • 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler • Internal Power-on Reset (POR) • Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR) • Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST) • On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog enable/disable control • Three I/O ports IOA, IOB and IOC with independent direction control • Soft-ware I/O pull-high/pull-down or open-drain control • One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change • Wake-up from SLEEP by INT pin or Port B input change • Power saving SLEEP mode • Programmable Code Protection • Selectable oscillator options: - RC: Resistor/Capacitor Oscillator - XT: Crystal/Resonator Oscillator - HF: High Frequency Crystal/Resonator Oscillator - LF: Low Frequency Crystal Oscillator • Wide-operating voltage range: - EPROM : 2.3V to 5.5V - ROM : 2.3V to 5.5V This datasheet contains new product inform99032685ation. TLC reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. Rev0.95 Nov 20, 2003 P.1/TLC156 TLC TLC156 GENERAL DESCRIPTION The TLC156 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces development time significantly. The TLC156 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. The TLC154 and TLC155 address 512×13 of program memory, the TLC156 address 1K×13 of program memory, and the TLC157 address 2K×13 of program memory. The TLC156 can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. BLOCK DIAGRAM Oscillator Circuit 5-level STACK Watchdog Timer Program Counter FSR SRAM ALU EPROM / ROM Instruction Decoder PORTA PORTB Interrupt Control Timer0 Accumulator PORTC Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 PIN CONNECTION PDIP, SOP IOA2 IOA3 T0CKI RSTB Vss IOB0/INT IOB1 IOB2 IOB3 SSOP 1 2 3 4 5 6 7 8 9 TLC154 TLC156 18 17 16 15 14 13 12 11 10 IOA1 IOA0 OSCI OSCO Vdd IOB7 IOB6 IOB5 IOB4 PDIP, SOP T0CKI Vdd NC Vss NC IOA0 IOA1 IOA2 IOA3 IOB0/INT IOB1 IOB2 IOB3 IOB4 IOA2 IOA3 T0CKI RSTB Vss Vss IOB0/INT IOB1 IOB2 IOB3 1 2 3 4 5 6 7 8 9 10 TLC154 TLC156 20 19 18 17 16 15 14 13 12 11 IOA1 IOA0 OSCI OSCO Vdd Vdd IOB7 IOB6 IOB5 IOB4 TLC155 TLC157 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSTB OSCI OSCO IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOB7 IOB6 IOB5 SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TLC155 TLC157 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSTB OSCI OSCO IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOB7 IOB6 IOB5 Vss T0CKI Vdd Vdd IOA0 IOA1 IOA2 IOA3 IOB0/INT IOB1 IOB2 IOB3 IOB4 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN DESCRIPTIONS Name IOA0 ~ IOA3 IOB0/INT IOB1 ~ IOB7 IOC0 ~ IOC7 I/O I/O I/O I/O I/O Description IOA0 ~ IOA3 as bi-direction I/O port Bi-direction I/O pin with system wake-up function / External interrupt input Bi-direction I/O port with system wake-up function Bi-direction I/O port Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current T0CKI I consumption RSTB I System clear (RESET) input. This pin is an active low RESET to the device. X’tal type: Oscillator crystal input OSCI I RC type: Clock input of RC oscillator X’tal type: Oscillator crystal output. OSCO O RC mode: Outputs with the instruction cycle rate Vdd Positive supply Vss Ground Legend: I=input, O=output, I/O=input/output Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 1.0 MEMORY ORGANIZATION TLC156 memory is organized into program memory and data memory. 1.1 Program Memory Organization The TLC154/155 have a 9-bit Program Counter (PC) capable of addressing a 512×13 program memory space. The TLC156 have a 10-bit Program Counter capable of addressing a 1K×13 program memory space. The TLC157 have an 11-bit Program Counter capable of addressing a 2K×13 program memory space. The RESET vector for the TLC154/155 is at 1FFh. The RESET vector for the TLC156 is at 3FFh. The RESET vector for the TLC157 is at 7FFh. The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h. TLC157 has program memory size greater than 1K words, but the CALL and GOTO instructions only have a 10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow CALL and GOTO instructions to address the entire 2K program memory address range for TLC157, there is another one bit to specify the program memory page. This paging bit comes from the PCHBUF<2> bit. When doing a CALL or GOTO instruction, the user must ensure that page bit PCHBUF<2> are programmed so that the desired program memory page is addressed. When one of the return instructions is executed, the entire 11-bit PC is POPed from the stack. Therefore, manipulation of the PCHBUF <2> is not required for the return instructions. FIGURE 1.1: Program Memory Map and STACK PC<10:0> Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 PC<9:0> Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 PC<8:0> Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 1FFh Reset Vector 3FFh 7FFh Reset Vector Reset Vector : : : : : : 008h H/W Interrupt Vector 008h H/W Interrupt Vector 008h H/W Interrupt Vector 002h S/W Interrupt Vector 002h S/W Interrupt Vector 002h S/W Interrupt Vector 000h 000h 000h TLC154/155 TLC156 TLC157 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 1.2 Data Memory Organization Data memory is composed of Special Function Registers and General Purpose Registers. The General Purpose Registers are accessed either directly or indirectly through the FSR register. The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device. In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1 and RP0 bits in the FSR register to be configured for the desired bank. TABLE 1.1: Operational Registers Map Address Name B7 B6 B5 B4 B3 B2 B1 B0 N/A (w) OPTION INTEDG T0CS T0SE PSA PS2 PS1 PS0 N/A (w) IOSTA Port A I/O Control Register N/A (w) IOSTB Port B I/O Control Register N/A (w) IOSTC Port C I/O Control Register 00h (r/w) INDF Uses contents of FSR to address data memory (not a physical register) 01h (r/w) TMR0 8-bit real-time clock/counter 02h (r/w) PCL Low order 8 bits of PC 03h (r/w) STATUS GP2 GP1 GP0 TO PD Z DC C (3) (3) 04h (r/w) FSR RP1 RP0 Indirect data memory address pointer 05h (r/w) PORTA IOA3 IOA2 IOA1 IOA0 06h (r/w) PORTB IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 (1) 07h (r/w) PORTC IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 08h (r/w) PCON WDTE EIS LVDTE ROC 09h (r/w) WUCON WUB7 WUB6 WUB5 WUB4 WUB3 WUB2 WUB1 WUB0 (2) 0Ah (r/w) PCHBUF Upper 3 bits Buffer of PC 0Bh (r/w) PDCON /PDB3 /PDB2 /PDB1 /PDB0 /PDA3 /PDA2 /PDA1 /PDA0 0Ch (r/w) ODCON ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0Dh (r/w) PHCON /PHB7 /PHB6 /PHB5 /PHB4 /PHB3 /PHB2 /PHB1 /PHB0 0Eh (r/w) INTEN GIE INTIE PBIE T0IE 0Fh (r/w) INTFLAG INTIF PBIF T0IF Legend: - = unimplemented, read as ‘0’, Note 1 : PORTC is an 8-bit I/O Register for TLC155/157. PORTC is a General Purpose Register for TLC154/156. 2 : There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in TLC157. 3 : For TLC154/155/156, these bits are not used, read as ‘1’ Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 TABLE 1.2: Registers File Map for TLC154/155/156 Address Description 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h | 3Fh INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PCON WUCON PCHBUF PDCON ODCON PHCON INTEN INTFLAG General Purpose Registers TABLE 1.3: Registers File Map for TLC157 Description FSR<7:6> Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h | 2Fh 30h | 3Fh 00 Bank 0 INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PCON WUCON PCHBUF PDCON ODCON PHCON INTEN INTFLAG General Purpose Registers General Purpose Registers 01 Bank 1 10 Bank 2 11 Bank 3 Memory back to address in Bank 0 General Purpose Registers General Purpose Registers General Purpose Registers Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.0 FUNCTIONAL DESCRIPTIONS 2.1 Operational Registers 2.1.1 INDF (Indirect Addressing Register) Address 00h (r/w) Name INDF B7 B6 B5 B4 B3 B2 B1 B0 Uses contents of FSR to address data memory (not a physical register) The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh). In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1 and RP0 bits in the FSR register to be configured for the desired bank. The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers. All Special Function Registers and some of General Purpose Registers from bank 0 are mirrored in other banks for code reduction and quicker access. Accessed Bank 0 1 2 3 RP1:RP0 0 0 1 1 0 1 0 1 EXAMPLE 2.1: INDIRECT ADDRESSING • Register file 38 contains the value 10h • Register file 39 contains the value 0Ah • Load the value 38 into the FSR Register • A read of the INDF Register will return the value of 10h • Increment the value of the FSR Register by one (@FSR=39h) • A read of the INDR register now will return the value of 0Ah. FIGURE 2.1: Direct/Indirect Addressing for TLC154/155/156 Direct Addressing 5 from opcode location select Indirect Addressing 0 5 from FSR register 0 00h location select addressing INDF register 3Fh Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 FIGURE 2.2: Direct/Indirect Addressing for TLC157 Direct Addressing RP1:RP0 5 from opcode bank select Indirect Addressing 0 5 from FSR register 0 00 location select 01 10 11 00h location select addressing INDF register 3Fh 2.1.2 TMR0 (Time Clock/Counter register) Address 01h (r/w) Name TMR0 B7 B6 B5 B4 B3 B2 8-bit real-time clock/counter B1 B0 The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)). The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared when TMR0 register is written with a value. 2.1.3 PCL (Low Bytes of Program Counter) & Stack Address 02h (r/w) Name PCL B7 B6 B5 B4 B3 Low order 8 bits of PC B2 B1 B0 TLC156 devices have a 9-bit (for TLC154/155) or 10-bit (for TLC156) or 11-bit (for TLC157) wide Program Counter (PC) and five-level deep 9-bit (10-bit, or 11-bit) hardware push/pop stack. The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called the PCH register. This register contains the PC<10:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<10> is updated from the PCHBUF<2>. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated. For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<10> is updated from the PCHBUF<2>. The next PC will be loaded (PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated. For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated. For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word. However, the PC<10:8> will come from the PCHBUF<2:0> register (PCHBUF à PCH). PCHBUF register is never updated with the contents of PCH. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 FIGURE 2.2: Loading of PC in Different Situations Situation 1: GOTO Instruction PCH 10 9 8 PCL 7 0 PC PCHBUF<2> - - - - Opcode<9:0> PCHBUF Situation 2: CALL Instruction STACK<10:0> PCH 10 9 8 PCL 7 0 PC PCHBUF<2> - - - - Opcode<9:0> PCHBUF Situation 3: RETIA, RETFIE, or RETURN Instruction STACK<10:0> PCH 10 9 8 PCL 7 0 PC - - - - PCHBUF Situation 4: Instruction with PCL as destination PCH 10 9 8 PCL 7 0 PC PCHBUF<2:0> - - - - ALU result<7:0> or Opcode<7:0> PCHBUF Note: 1. Bits PC<10:9> and PCHBUF<2:1> are unimplemented for TLC154/155. Bits PC<10> and PCHBUF<2> are unimplemented for TLC156. 2. PCHBUF is used only for instruction with PCL as destination for TLC154/155/156. PCHBUF is used for instruction with PCL as destination, GOTO and CALL instructions for TLC157. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.1.4 STATUS (Status Register) Address 03h (r/w) Name STATUS B7 GP2 B6 GP1 B5 GP0 B4 TO B3 PD B2 Z B1 DC B0 C This register contains the arithmetic status of the ALU, the RESET status. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS Register as 000u u1uu (where u = unchanged). C : Carry/borrow bit. ADDAR, ADDIA = 1, a carry occurred. = 0, a carry did not occur. SUBAR, SUBIA = 1, a borrow did not occur. = 0, a borrow occurred. Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR) instructions, this bit is loaded with either the high or low order bit of the source register. DC : Half carry/half borrow bit. ADDAR, ADDIA = 1, a carry from the 4th low order bit of the result occurred. = 0, a carry from the 4th low order bit of the result did not occur. SUBAR, SUBIA = 1, a borrow from the 4th low order bit of the result did not occur. = 0, a borrow from the 4th low order bit of the result occurred. Z : Zero bit. = 1, the result of a logic operation is zero. = 0, the result of a logic operation is not zero. PD : Power down flag bit. = 1, after power-up or by the CLRWDT instruction. = 0, by the SLEEP instruction. TO : Time overflow flag bit. = 1, after power-up or by the CLRWDT or SLEEP instruction. = 0, a watch-dog time overflow occurred. GP2:GP0 : General purpose read/write bits. 2.1.5 FSR (Indirect Data Memory Address Pointer) Address 04h (r/w) Name FSR B7 RP1 B6 RP0 B5 B4 B3 B2 B1 Indirect data memory address pointer B0 Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description. RP1:RP0 : For TLC154/155/156, these bits are not used. Read as “1”s. For TLC157, these bits are used to switching the bank of four data memory banks. See 2.1.1 for detail description. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.1.6 PORTA, PORTB & PORTC (Port Data Registers) Address 05h (r/w) 06h (r/w) 07h (r/w) Name PORTA PORTB PORTC B7 IOB7 IOC7 B6 IOB6 IOC6 B5 IOB5 IOC5 B4 IOB4 IOC4 B3 IOA3 IOB3 IOC3 B2 IOA2 IOB2 IOC2 B1 IOA1 IOB1 IOC1 B0 IOA0 IOB0 IOC0 Reading the port (PORTA, PORTB, PORTC register) reads the status of the pins independent of the pin’s input/output modes. Writing to these ports will write to the port data latch. PORTA is a 4-bit port data Register. Only the low order 4 bits are used (PORTA<3:0>). Bits 7-4 are unimplemented and read as ‘0’s. PORTB is a 8-bit port data register. PORTC is a 8-bit port data register for TLC155/157, or a General Purpose Register for TLC154/156. 2.1.7 PCON (Power Control Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 08h (r/w) PCON WDTE EIS LVDTE ROC - - - - Bit3:Bit0 : Not used. Read as “0”s. ROC : R-option function of IOA0 and IOA1 pins enable bit. = 0, Disable the R-option function. = 1, Enable the R-option function. In this case, if a 430KΩ external resister is connected/disconnected to Vss, the status of IOA0 (IOA1) is read as “0”/”1”. LVDTE : LVDT (low voltage detector) enable bit. = 0, Disable LVDT. = 1, Enable LVDT. EIS : Define the function of IOB0/INT pin. = 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked. = 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way of reading PORTB. WDTE : WDT (watch-dog timer) enable bit. = 0, Disable WDT. = 1, Enable WDT. 2.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register) Address 09h (r/w) Name WUCON B7 WUB7 B6 WUB6 B5 WUB5 B4 WUB4 B3 WUB3 B2 WUB2 B1 WUB1 B0 WUB0 WUB0 : = 0, Disable the input change interrupt/wake-up function of IOB0 pin. = 1, Enable the input change interrupt/wake-up function of IOB0 pin. WUB1 : = 0, Disable the input change interrupt/wake-up function of IOB1 pin. = 1, Enable the input change interrupt/wake-up function of IOB1 pin. WUB2 : = 0, Disable the input change interrupt/wake-up function of IOB2 pin. = 1, Enable the input change interrupt/wake-up function of IOB2 pin. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 WUB3 : = 0, Disable the input change interrupt/wake-up function of IOB3 pin. = 1, Enable the input change interrupt/wake-up function of IOB3 pin. WUB4 : = 0, Disable the input change interrupt/wake-up function of IOB4 pin. = 1, Enable the input change interrupt/wake-up function of IOB4 pin. WUB5 : = 0, Disable the input change interrupt/wake-up function of IOB5 pin. = 1, Enable the input change interrupt/wake-up function of IOB5 pin. WUB6 : = 0, Disable the input change interrupt/wake-up function of IOB6 pin. = 1, Enable the input change interrupt/wake-up function of IOB6 pin. WUB7 : = 0, Disable Enable the input change interrupt/wake-up function of IOB7 pin. = 1, Enable the input change interrupt/wake-up function of IOB7 pin. 2.1.9 PCHBUF (High Byte Buffer of Program Counter) Address 0Ah (r/w) Name PCHBUF B7 - B6 - B5 - B4 - B3 - B2 B1 B0 Upper 3 bits Buffer of PC There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in TLC157. See 2.1.3 for detail description. 2.1.10 PDCON (Pull-down Control Register) Address 0Bh (r/w) Name PDCON B7 /PDB3 B6 /PDB2 B5 /PDB1 B4 /PDB0 B3 /PDA3 B2 /PDA2 B1 /PDA1 B0 /PDA0 /PDA0 : = 0, Enable the internal pull-down of IOA0 pin. = 1, Disable the internal pull-down of IOA0 pin. /PDA1 : = 0, Enable the internal pull-down of IOA1 pin. = 1, Disable the internal pull-down of IOA1 pin. /PDA2 : = 0, Enable the internal pull-down of IOA2 pin. = 1, Disable the internal pull-down of IOA2 pin. /PDA3 : = 0, Enable the internal pull-down of IOA3 pin. = 1, Disable the internal pull-down of IOA3 pin. /PDB0 : = 0, Enable the internal pull-down of IOB0 pin. = 1, Disable the internal pull-down of IOB0 pin. /PDB1 : = 0, Enable the internal pull-down of IOB1 pin. = 1, Disable the internal pull-down of IOB1 pin. /PDB2 : = 0, Enable the internal pull-down of IOB2 pin. = 1, Disable the internal pull-down of IOB2 pin. /PDB3 : = 0, Enable the internal pull-down of IOB3 pin. = 1, Disable the internal pull-down of IOB3 pin. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.1.11 ODCON (Open-drain Control Register) Address 0Ch (r/w) Name ODCON B7 ODB7 B6 ODB6 B5 ODB5 B4 ODB4 B3 ODB3 B2 ODB2 B1 ODB1 B0 ODB0 B4 /PHB4 B3 /PHB3 B2 /PHB2 B1 /PHB1 B0 /PHB0 ODB0 : = 0, Disable the internal open-drain of IOB0 pin. = 1, Enable the internal open-drain of IOB0 pin. ODB1 : = 0, Disable the internal open-drain of IOB1 pin. = 1, Enable the internal open-drain of IOB1 pin. ODB2 : = 0, Disable the internal open-drain of IOB2 pin. = 1, Enable the internal open-drain of IOB2 pin. ODB3 : = 0, Disable the internal open-drain of IOB3 pin. = 1, Enable the internal open-drain of IOB3 pin. ODB4 : = 0, Disable the internal open-drain of IOB4 pin. = 1, Enable the internal open-drain of IOB4 pin. ODB5 : = 0, Disable the internal open-drain of IOB5 pin. = 1, Enable the internal open-drain of IOB5 pin. ODB6 : = 0, Disable the internal open-drain of IOB6 pin. = 1, Enable the internal open-drain of IOB6 pin. ODB7 : = 0, Disable the internal open-drain of IOB7 pin. = 1, Enable the internal open-drain of IOB7 pin. 2.1.12 PHCON (Pull-high Control Register) Address 0Dh (r/w) Name PHCON B7 /PHB7 B6 /PHB6 B5 /PHB5 /PHB0 : = 0, Enable the internal pull-high of IOB0 pin. = 1, Disable the internal pull-high of IOB0 pin. /PHB1 : = 0, Enable the internal pull-high of IOB1 pin. = 1, Disable the internal pull-high of IOB1 pin. /PHB2 : = 0, Enable the internal pull-high of IOB2 pin. = 1, Disable the internal pull-high of IOB2 pin. /PHB3 : = 0, Enable the internal pull-high of IOB3 pin. = 1, Disable the internal pull-high of IOB3 pin. /PHB4 : = 0, Enable the internal pull-high of IOB4 pin. = 1, Disable the internal pull-high of IOB4 pin. /PHB5 : = 0, Enable the internal pull-high of IOB5 pin. = 1, Disable the internal pull-high of IOB5 pin. /PHB6 : = 0, Enable the internal pull-high of IOB6 pin. = 1, Disable the internal pull-high of IOB6 pin. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 /PHB7 : = 0, Enable the internal pull-high of IOB7 pin. = 1, Disable the internal pull-high of IOB7 pin. 2.1.13 INTEN (Interrupt Mask Register) Address 0Eh (r/w) Name INTEN B7 GIE B6 - B5 - B4 - B3 - B2 INTIE B1 PBIE B0 T0IE T0IE : Timer0 overflow interrupt enable bit. = 0, Disable the Timer0 overflow interrupt. = 1, Enable the Timer0 overflow interrupt. PBIE : Port B input change interrupt enable bit. = 0, Disable the Port B input change interrupt. = 1, Enable the Port B input change interrupt . INTIE : External INT pin interrupt enable bit. = 0, Disable the External INT pin interrupt. = 1, Enable the External INT pin interrupt. Bit6:BIT3 : Not used. Read as “0”s. GIE : Global interrupt enable bit. = 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue execution at the instruction after the SLEEP instruction. = 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device will branch to the interrupt address (008h). Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the interrupt routine and set the GIE bit to re-enable interrupt. 2.1.14 INTFLAG (Interrupt Status Register) Address 0Fh (r/w) Name INTFLAG B7 - B6 - B5 - B4 - B3 - B2 INTIF B1 PBIF B0 T0IF T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software. PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software. INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin, reset by software. Bit7:BIT3 : Not used. Read as “0”s. 2.1.15 ACC (Accumulator) Address N/A (r/w) Name ACC B7 B6 B5 B4 B3 Accumulator B2 B1 B0 Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.1.16 OPTION Register Address N/A (w) Name OPTION B7 - B6 INTEDG B5 T0CS B4 T0SE B3 PSA B2 PS2 B1 PS1 B0 PS0 By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register. The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler, Timer0, and the external INT interrupt. The OPTION Register are “write-only” and are set all “1”s except INTEDG bit. PS2:PS0 : Prescaler rate select bits. PS2:PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Timer0 Rate WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 0 1 0 1 0 1 0 1 PSA : Prescaler assign bit. = 1, WDT (watch-dog timer). = 0, TMR0 (Timer0). T0SE : TMR0 source edge select bit. = 1, Falling edge on T0CKI pin. = 0, Rising edge on T0CKI pin. T0CS : TMR0 clock source select bit. = 1, External T0CKI pin. = 0, internal instruction clock cycle. INTEDG : Interrupt edge select bit. = 1, interrupt on rising edge of INT pin. = 0, interrupt on falling edge of INT pin. Bit7 : Not used. 2.1.17 IOSTA, IOSTB & IOSTC (Port I/O Control Registers) Address Name N/A (w) N/A (w) N/A (w) IOSTA IOSTB IOSTC B7 B6 B5 B4 B3 B2 B1 B0 Port A I/O Control Register Port B I/O Control Register Port C I/O Control Register The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~07h) instruction. A ‘1’from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode). A ‘0’enables the output buffer and puts the contents of the output data latch on the selected pins (output mode). The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.2 I/O Ports Port A, port B and port C are bi-directional tri-state I/O ports. Port A is a 4-pin I/O port. Port B and port C are 8-pin I/O ports. All I/O pins (IOA<3:0>, IOB<7:0> and IOC<7:0>) have data direction control registers (IOSTA, IOSTB, IOSTC) which can configure these pins as output or input. IOB<7:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high. The weak pull-high is automatically turned off when the pin is configured as an output pin. IOA<3:0> and IOB<3:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin. IOB<7:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when these pins are configured to be an output pin. IOA0 and IOA1 are the R-option pins enabled by setting the ROC bit (PCON<4>). When the R-option function is used, it is recommended that IOA0 and IOA1 are used as output pins, and read the status of IOA0 and IOA1 before these pins are configured to be an output pin. IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source. The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input change interrupt/wake-up function will be disabled by hardware even if it is enabled by software. FIGURE 2.3: Block Diagram of I/O PINs IOA3 ~ IOA0, IOC7 ~ IOC0 : Data bus D Q IOST Latch IOST R > EN Q I/O PIN D Q DATA Latch WR PORT > EN Q RD PORT Pull-down is not shown in the figure Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 IOB0/INT : Data bus D Q IOST Latch > EN IOST R Q I/O PIN D Q DATA Latch > EN WR PORT Q RD PORT Q Set PBIF D Latch EN< Q WUBn EIS INTEDG INT EIS Pull-high/pull-down and open-drain are not shown in the figure IOB7 ~ IOB1 : Data bus D Q IOST Latch IOST R > EN Q I/O PIN D Q DATA Latch WR PORT > EN Q RD PORT Set PBIF WUBn Q D Latch Q EN< Pull-high/pull-down and open-drain are not shown in the figure Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.3 Timer0/WDT & Prescler 2.3.1 Timer0 The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external clock source (T0CKI pin). 2.3.1.1 Using Timer0 with an Internal Clock : Timer mode Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles. 2.3.1.2 Using Timer0 with an External Clock : Counter mode Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select the rising edge. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2 Tosc. When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc divided by the prescaler value. 2.3.2 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode. During normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS<4>) will be cleared. The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”. The WDT has a nominal time-out period of 18 ms (without prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register. Thus, the longest time-out period is approxmately 2.3 seconds. The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out and generating a device reset. The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT Wake-up Reset. 2.3.3 Prescaler An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog Timer (WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa. The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine prescaler ratio. When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s. To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the prescaler assignment from Timer0 to the WDT, and vice-versa. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler Instruction Cycle (Fosc/4 or Fosc/2 or Fosc/8) 0 T0CKI 1 1 MUX 0 T0SE MUX Sync 2 Cycles TMR0 Register 8 Data Bus Set T0IF flag on overflow T0CS PSA 0 Watchdog Timer 1 MUX 8-Bit Prescaler 1 0 PSA MUX WDT Time-out PS2:PS0 PSA 2.4 Interrupts The TLC156 series has up to three sources of interrupt: 1. External interrupt INT pin. 2. TMR0 overflow interrupt. 3. Port B input change interrupt (pins IOB7:IOB0). INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags. A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register regardless of the status of the GIE bit. When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts. The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt. The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit. Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN. When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h. 2.4.1 External INT Interrupt External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>). When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled by clearing INTIE bit (INTEN<2>). The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will execute next PC after wake-up. 2.4.2 Timer0 Interrupt An overflow (FFh à 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be disabled by clearing T0IE bit (INTEN<0>). Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.4.3 Port B Input Change Interrupt An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit (INTEN<1>). Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared to “0” or configured as output or IOB0 pin configured as INT pin will be excluded from this function. The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will execute next PC after wake-up. 2.5 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will be cleared and keeps running, and the oscillator driver is turned off. All I/O pins maintain the status they had before the SLEEP instruction was executed. 2.5.1 Wake-up from SLEEP Mode The device can wake-up from SLEEP mode through one of the following events: 1. RSTB reset. 2. WDT time-out reset (if enabled). 3. Interrupt from RB0/INT pin, or PORTB change interrupt. External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is executed. The TO bit is cleared if a WDT time-out occurred. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP instruction. If the GIE bit is set, the device will branch to the interrupt address (008h). The system wake-up delay time is 18ms plus 128 oscillator cycle time. 2.6 Reset TLC156 devices may be RESET in one of the following ways: 1. Power-on Reset (POR) 2. Brown-out Reset (BOR) 3. RSTB Pin Reset 4. WDT time-out Reset Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT Reset. A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely ties the RSTB pin to Vdd. On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is typically used in AC line or heavy loads switched applications. A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.6.1 Power-up Reset Timer(PWRT) The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active. The PWDT delay will vary from device to device due to Vdd, temperature, and process variation. 2.6.2 Oscillator Start-up Timer(OST) The OST timer provides a 128 oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as long as the OST is active. This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds. 2.6.3 Reset Sequence When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset sequence is as follows: 1. The reset latch is set and the PWRT & OST are cleared. 2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins counting. 3. After the PWRT time-out, the OST is activated. 4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal. The totally system reset delay time is 18ms plus 128 oscillator cycle time. FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit WDT Module WDT Time-out S RSTB Vdd Low Voltage BOR Detector (LVD) Power-on Reset (POR) R Q CHIP RESET POR On-Chip RC OSC OSCI Q Reset Latch RESET RESET Power-up Reset Timer (PWRT) Oscillator Start-up Timer (OST) Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 TABLE 2.1: Reset Conditions for All Registers Register Address Power-on Reset Brown-out Reset RSTB Reset WDT Reset ACC N/A xxxx xxxx uuuu uuuu OPTION N/A -011 1111 -011 1111 IOSTA N/A ---- 1111 ---- 1111 1111 1111 IOSTB N/A 1111 1111 IOSTC N/A 1111 1111 1111 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu FSR 04h xxxx xxxx uuuu uuuu PORTA 05h ---- xxxx ---- uuuu PORTB 06h xxxx xxxx uuuu uuuu PORTC 07h xxxx xxxx uuuu uuuu PCON 08h 1010 ---- 1010 ---- WUCON 09h 0000 0000 0000 0000 PCHBUF 0Ah ---- -000 ---- -000 PDCON 0Bh 1111 1111 1111 1111 ODCON 0Ch 0000 0000 0000 0000 PHCON 0Dh 1111 1111 1111 1111 INTEN 0Eh 0--- -000 0--- -000 INTFLAG 0Fh ---- -000 ---- -000 General Purpose Registers 10 ~ 3Fh xxxx xxxx uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented, # = refer to the following table for possible values. TABLE 2.2: TO / PD Status after Reset RESET was caused by TO PD 1 1 Power-on Reset 1 1 Brown-out reset u u RSTB Reset during normal operation 1 0 RSTB Reset during SLEEP 0 1 WDT Reset during normal operation 0 0 WDT Reset during SLEEP Legend: u = unchanged TABLE 2.3: Events Affecting TO / PD Status Bits TO PD Power-on 1 1 WDT Time-Out 0 u SLEEP instruction 1 0 CLRWDT instruction 1 1 Event Legend: u = unchanged Rev0.95 Nov 20, 2003 P.2/TLC156 P TLC TLC156 2.7 Hexadecimal Convert to Decimal (HCD) Decimal format is another number format for TLC156. When the content of the data memory has been assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions. When the decimal converting operation is processing, all of the operand data (including the contents of the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the results of conversion will be incorrect. Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and restored to ACC. The conversion operation is illustrated in example 2.2. EXAMPLE 2.2: DAA CONVERSION MOVIA 90h ;Set immediate data = decimal format number “90” (ACC ß 90h) MOVAR 30h ;Load immediate data “90” to data memory address 30H MOVIA 10h ;Set immediate data = decimal format number “10” (ACC ß 10h) ADDAR 30h, 0 ;Contents of the data memory address 30H and ACC are binary-added ;the result loads to the ACC (ACC ß A0h, C ß 0) DAA ;Convert the content of ACC to decimal format, and restored to ACC ;The result in the ACC is “00” and the carry bit C is “1”. This represents the ;decimal number “100” Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation and restored to ACC. The conversion operation is illustrated in example 2.3. EXAMPLE 2.3: DAS CONVERSION MOVIA 10h ;Set immediate data = decimal format number “10” (ACC ß 10h) MOVAR 30h ;Load immediate data “10” to data memory address 30H MOVIA 20h ;Set immediate data = decimal format number “20” (ACC ß 20h) SUBAR 30h, 0 ;Contents of the data memory address 30H and ACC are binary-subtracted ;the result loads to the ACC (ACC ß F0h, C ß 0) DAS ;Convert the content of ACC to decimal format, and restored to ACC ;The result in the ACC is “90” and the carry bit C is “0”. This represents the ;decimal number “ -10” 2.8 Oscillator Configurations TLC156 can be operated in four different oscillator modes. Users can program two configuration bits (Fosc<1:0>) to select the appropriate modes: • LF: Low Frequency Crystal Oscillator • XT: Crystal/Resonator Oscillator • HF: High Frequency Crystal/Resonator Oscillator • RC: Resistor/Capacitor Oscillator In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin. The RC device option offers additional cost savings for timing insensitive applications. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext), the operating temperature, and the process parameter. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 FIGURE 2.6: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator) TLC156 OSCI C1 X’TAL C2 SLEEP RF RS OSCO Internal Circuit FIGURE 2.7: HF, XT or LF Oscillator Modes (External Clock Input Operation) TLC156 OSCI Clock from External System OSCO Open FIGURE 2.8: RC Oscillator Mode Rext TLC156 OSCI Internal Circuit Cext OSCO /2, /4, /8 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 2.9 Configurations Word TABLE 2.4: Configurations Word bit Name Description Oscillator Selection Bits = 1, 1 à RC mode (default) 1, 0 Fosc<1:0> = 1, 0 à HF mode = 0, 1 à XT mode = 0, 0 à LF mode Watchdog Timer Enable Bit 2 WDTEN = 1, WDT enabled (default) = 0, WDT disabled Code Protection Bit 3 PROTECT = 1, EPROM code protection off (default) = 0, EPROM code protection on Low Voltage Detector Selection Bit = 1, 1 à disable (default) 5, 4 LVDT<1:0> = 0, 1 à enable, LVDT voltage = 2.0V = 0, 0 à enable, LVDT voltage = 3.6V Instruction Period Selection Bits = 1, 1 à four oscillator periods (default) 7, 6 OSCD<1:0> = 1, 0 à two oscillator periods = 0, 0 à eight oscillator periods Power Mode Selection Bits = 1, 1 à Power Mode 3, non-power saving (default) 9, 8 PMOD<1:0> = 1, 0 à Power Mode 2, power saving = 0, 1 à Power Mode 1, power saving = 0, 0 à Power Mode 0, power saving 12, 11, 10 Unused Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 3.0 INSTRUCTION SET Mnemonic, Operands Description Operation Cycles Status Affected - BCR R, bit Clear bit in R 0 à R<b> 1 BSR R, bit Set bit in R 1 à R<b> 1 - BTRSC R, bit Test bit in R, Skip if Clear Skip if R<b> = 0 1/2 (1) BTRSS R, bit Test bit in R, Skip if Set Skip if R<b> = 1 1/2 (1) NOP No Operation CLRWDT Clear Watchdog Timer OPTION Load OPTION register SLEEP Go into power-down mode INT S/W interrupt No operation 00h à WDT, 00h à WDT prescaler ACC à OPTION 00h à WDT, 00h à WDT prescaler PC + 1 à Top of Stack, 002h à PC Adjust ACC’s data format from HEX to DEC after any addition ACC(hex) à ACC(dec) operation Adjust ACC’s data format from HEX to DEC after any subtraction ACC(hex) à ACC(dec) operation DAA DAS RETURN Return from subroutine RETFIE Return from interrupt, set GIE bit CLRA Clear ACC Top of Stack à PC Top of Stack à PC, 1 à GIE 00h à ACC - 1 - 1 TO , PD 1 - 1 TO , PD 3/2 (2) - 1 C 1 - 2 - 2 - 1 Z IOST R Load IOST register ACC à IOST register 1 - CLRR R Clear R 00h à R 1 Z MOVAR R Move ACC to R ACC à R 1 - MOVR R, d Move R R à dest 1 Z DECR R, d Decrement R R - 1 à dest R - 1 à dest, Skip if result = 0 R + 1 à dest 1 Z DECRSZ R, d Decrement R, Skip if 0 INCR Increment R R, d 1/2 (1) 1 Z INCRSZ R, d Increment R, Skip if 0 R + 1 à dest, Skip if result = 0 ADDAR R, d Add ACC and R R + ACC à dest 1 C, DC, Z SUBAR R, d Subtract ACC from R R - ACC à dest 1 C, DC, Z ADCAR R, d Add ACC and R with Carry R + ACC + C à dest 1 C, DC, Z SBCAR R, d Subtract ACC from R with Carry R + ACC + C à dest 1 C, DC, Z ANDAR R, d AND ACC with R ACC and R à dest 1 Z IORAR R, d Inclusive OR ACC with R ACC or R à dest 1 Z XORAR R, d Exclusive OR ACC with R R xor ACC à dest 1 Z COMR R, d Complement R 1 Z RLR R, d Rotate left f through Carry R à dest R<7> à C, R<6:0> à dest<7:1>, C à dest<0> 1 C 1/2 (1) - Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 C à dest<7>, R<7:1> à dest<6:0>, R<0> à C R<3:0> à dest<7:4>, R<7:4> à dest<3:0> RRR R, d Rotate right f through Carry SWAPR R, d Swap R MOVIA I Move Immediate to ACC I à ACC 1 - ADDIA I Add ACC and Immediate I + ACC à ACC 1 C, DC, Z SUBIA I Subtract ACC from Immediate I - ACC à ACC 1 C, DC, Z ANDIA I AND Immediate with ACC ACC and I à ACC 1 Z IORIA I OR Immediate with ACC ACC or I à ACC 1 Z XORIA I Exclusive OR Immediate to ACC ACC xor I à ACC 1 Z RETIA I Return, place Immediate in ACC 2 - CALL I Call subroutine 2 - GOTO I Unconditional branch 2 - I à ACC, Top of Stack à PC PC + 1 à Top of Stack, I à PC<9:0> PCHBUF<2> à PC<10> I à PC<9:0> PCHBUF<2> à PC<10> 1 C 1 - Note: 1. 2 cycles for skip, else 1 cycle 2. 3 cycles for TLC154/156 2 cycles for TLC155/157 3. bit : Bit address within an 8-bit register R R : Register address (00h to 3Fh) I : Immediate data ACC : Accumulator d : Destination select; =0 (store result in ACC) =1 (store result in file register R) dest : Destination PC : Program Counter PCHBUF : High Byte Buffer of Program Counter WDT : Watchdog Timer Counter GIE : Global interrupt enable bit TO : Time-out bit PD : Power-down bit C : Carry bit DC : Digital carry bit Z : Zero bit Rev0.95 Nov 20, 2003 P.2/TLC156 TLC ADCAR Syntax: Operands: Operation: Status Affected: Description: Cycles: ADDAR Syntax: Operands: Operation: Status Affected: Description: Cycles: ADDIA Syntax: Operands: Operation: Status Affected: Description: Cycles: ANDAR Syntax: Operands: Operation: Status Affected: Description: Cycles: ANDIA Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Add ACC and R with Carry ADCAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + ACC + C à dest C, DC, Z Add the contents of the ACC register and register ‘R’with Carry. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is ‘1’the result is stored back in register ‘R’. 1 Add ACC and R ADDAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC + R à dest C, DC, Z Add the contents of the ACC register and register ‘R’. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is ‘1’the result is stored back in register ‘R’. 1 Add ACC and Immediate ADDIA I 0 ≤ I ≤ 255 ACC + I à ACC C, DC, Z Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 AND ACC and R ANDAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC and R à dest Z The contents of the ACC register are AND’ed with register ‘R’. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is ‘1’the result is stored back in register ‘R’. 1 AND Immediate with ACC ANDIA I 0 ≤ I ≤ 255 ACC AND I à ACC Z The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC BCR Syntax: Operands: Operation: Status Affected: Description: Cycles: BSR Syntax: Operands: Operation: Status Affected: Description: Cycles: BTRSC Syntax: Operands: Operation: Status Affected: Description: Cycles: BTRSS Syntax: Operands: Operation: Status Affected: Description: Cycles: CALL Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Clear Bit in R BCF R, b 0 ≤ R ≤ 63 0≤b≤7 0 à R<b> None Clear bit ‘b’in register ‘R’. 1 Set Bit in R BSR R, b 0 ≤ R ≤ 63 0≤b≤7 1 à R<b> None Set bit ‘b’in register ‘R’. 1 Test Bit in R, Skip if Clear BTRSC R, b 0 ≤ R ≤ 63 0≤b≤7 Skip if R<b> = 0 None If bit ‘b’in register ‘R’is 0 then the next instruction is skipped. If bit ‘b’is 0 then next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead making this a 2-cycle instruction.. 1(2) Test Bit in R, Skip if Set BTRSS R, b 0 ≤ R ≤ 63 0≤b≤7 Skip if R<b> = 1 None If bit ‘b’in register ‘R’is ‘1’then the next instruction is skipped. If bit ‘b’is ‘1’, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2-cycle instruction. 1(2) Subroutine Call CALL I 0 ≤ I ≤ 1023 PC +1 à Top of Stack; I à PC<9:0> PCHBUF<2> à PC<10> None Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate address is loaded into PC bits <10:0>. CALL is a two-cycle instruction. 2 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC CLRA Syntax: Operands: Operation: Status Affected: Description: Cycles: CLRR Syntax: Operands: Operation: Status Affected: Description: Cycles: CLRWDT Syntax: Operands: Operation: Status Affected: Description: Cycles: COMR Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Clear ACC CLRA None 00h à ACC; 1àZ Z The ACC register is cleared. Zero bit (Z) is set. 1 Clear R CLRR R 0 ≤ R ≤ 63 00h à R; 1àZ Z The contents of register ‘R’are cleared and the Z bit is set. 1 Clear Watchdog Timer CLRWDT None 00h à WDT; 00h à WDT prescaler (if assigned); 1 à TO ; 1 à PD TO , PD The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bitsTO and PD are set. 1 Complement R COMR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R à dest Z The contents of register ‘R’are complemented. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is 1 the result is stored back in register ‘R’. 1 Adjust ACC’s data format from HEX to DEC DAA Syntax: Operands: Operation: Status Affected: Description: DAA None ACC(hex) à ACC(dec) C Cycles: 1 Convert the ACC data from hexadecimal to decimal format after any addition operation and restored to ACC. Rev0.95 Nov 20, 2003 P.2/TLC156 TLC DAS Syntax: Operands: Operation: Status Affected: Description: Cycles: DECR Syntax: Operands: Operation: Status Affected: Description: Cycles: DECRSZ Syntax: Operands: Operation: Status Affected: Description: Cycles: GOTO Syntax: Operands: Operation: Status Affected: Description: Cycles: INCR Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Adjust ACC’s data format from HEX to DEC DAS None ACC(hex) à ACC(dec) None Convert the ACC data from hexadecimal to decimal format after any subtraction operation and restored to ACC. 1 Decrement R DECR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R - 1 à dest Z Decrement register ‘R’. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is 1 the result is stored back in register ‘R’. 1 Decrement R, Skip if 0 DECRSZ R, d 0 ≤ R ≤ 63 d ∈ [0,1] R - 1 à dest; skip if result =0 None The contents of register ‘R’are decremented. If ‘d’is 0 the result is placed in the ACC register. If ‘d’is 1 the result is placed back in register ’R’. If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 1(2) Unconditional Branch GOTO I 0 ≤ I ≤ 1023 I à PC<9:0> PCHBUF<2> à PC<10> None GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>. GOTO is a two-cycle instruction. 2 Increment R INCR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + 1 à dest Z The contents of register ‘R’are incremented. If ‘d’is 0 the result is placed in the ACC register. If ‘d’is 1 the result is placed back in register ‘R’. 1 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC INCRSZ Syntax: Operands: Operation: Status Affected: Description: Cycles: INT Syntax: Operands: Operation: Status Affected: Description: Cycles: IORAR Syntax: Operands: Operation: Status Affected: Description: Cycles: IORIA Syntax: Operands: Operation: Status Affected: Description: TLC156 Increment R, Skip if 0 INCRSZ R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + 1 à dest, skip if result = 0 None The contents of register ‘R’are incremented. If ‘d’is 0 the result is placed in the ACC register. If ‘d’is the result is placed back in register ‘R’. If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 1(2) S/W Interrupt INT None PC + 1 à Top of Stack, 002h à PC None Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address 002h is loaded into PC bits <10:0>. 2 for TLC155/157; 3 for TLC154/156 OR ACC with R IORAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC or R à dest Z Inclusive OR the ACC register with register ‘R’. If ‘d’is 0 the result is placed in the ACC register. If ‘d’is 1 the result is placed back in register ‘R’. 1 Cycles: OR Immediate with ACC IORIA I 0 ≤ I ≤ 255 ACC or I à ACC Z The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 IOST Syntax: Operands: Operation: Status Affected: Description: Cycles: Load IOST Register IOST R R = 5,6 or 7 ACC à IOST register R None IOST register ‘R’(R= 5,6 or7) is loaded with the contents of the ACC register. 1 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 MOVAR Syntax: Operands: Operation: Status Affected: Description: Cycles: Move ACC to R MOVAR R 0 ≤ R ≤ 63 ACC à R None Move data from the ACC register to register ‘R’. 1 MOVIA Syntax: Operands: Operation: Status Affected: Description: Cycles: Move Immediate to ACC MOVIA I 0 ≤ I ≤ 255 I à ACC None The 8-bit immediate ‘I’is loaded into the ACC register. The don’t cares will assemble as 0s. 1 MOVR Syntax: Operands: Cycles: Move R MOVR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R à dest Z The contents of register ‘R’is moved to destination ‘d’. If ‘d’is 0, destination is the ACC register. If ‘d’is 1, the destination is file register ‘R’. ‘d’is 1 is useful to test a file register since status flag Z is affected. 1 NOP Syntax: Operands: Operation: Status Affected: Description: Cycles: No Operation NOP None No operation None No operation. 1 OPTION Syntax: Operands: Operation: Status Affected: Description: Cycles: Load OPTION Register OPTION None ACC à OPTION None The content of the ACC register is loaded into the OPTION register. 1 RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt, Set ‘GIE’ Bit RETFIE None Top of Stack à PC None The program counter is loaded from the top of the stack (the return address). The ‘GIE’bit is set to 1. This is a two-cycle instruction. 2 Operation: Status Affected: Description: Cycles: Rev0.95 Nov 20, 2003 P.2/TLC156 TLC RETIA Syntax: Operands: Operation: Status Affected: Description: Cycles: RETURN Syntax: Operands: Operation: Status Affected: Description: Cycles: RLR Syntax: Operands: Operation: Status Affected: Description: Cycles: RRR Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Return with Immediate in ACC RETIA I 0 ≤ I ≤ 255 I à ACC; Top of Stack à PC None The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2 Return from Subroutine RETURN None Top of Stack à PC None The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2 Rotate Left f through Carry RLR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R<7> à C; R<6:0> à dest<7:1>; C à dest<0> C The contents of register ‘R’are rotated one bit to the left through the Carry Flag. If ‘d’is 0 the result is placed in the ACC register. If ‘d’is 1 the result is stored back in register ‘R’. 1 Rotate Right f through Carry RRR R, d 0 ≤ R ≤ 63 d ∈ [0,1] C à dest<7>; R<7:1> à dest<6:0>; R<0> à C C The contents of register ‘R’are rotated one bit to the right through the Carry Flag. If ‘d’is 0 the result is placed in the ACC register. If ‘d’is 1 the result is placed back in register ‘R’. 1 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC SLEEP Syntax: Operands: Operation: Status Affected: Description: Cycles: SBCAR Syntax: Operands: Operation: Status Affected: Description: Cycles: SUBAR Syntax: Operands: Operation: Status Affected: Description: Cycles: SUBIA Syntax: Operands: Operation: Status Affected: Description: Cycles: SWAPR Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Enter SLEEP Mode SLEEP None 00h à WDT; 00h à WDT prescaler; 1 à TO ; 0 à PD TO , PD Time-out status bit ( TO ) is set. The power-down status bit ( PD ) is cleared. The WDT and its prescaler are cleared. The processor is put into SLEEP mode. 1 Subtract ACC from R with Carry SBCAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + ACC + C à dest C, DC, Z Add the 2’s complement method of the ACC register from register ‘R’with Carry. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is 1 the result is stored back in register ‘R’. 1 Subtract ACC from R SUBAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R - ACC à dest C, DC, Z Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is 1 the result is stored back in register ‘R’. 1 Subtract ACC from Immediate SUBAR R, d 0 ≤ I ≤ 255 I - ACC à ACC C, DC, Z Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 Swap nibbles in R SWAPR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R<3:0> à dest<7:4>; R<7:4> à dest<3:0> None The upper and lower nibbles of register ‘R’are exchanged. If ‘d’is 0 the result is placed in ACC register. If ‘d’is 1 the result in placed in register ‘R’. 1 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC XORAR Syntax: Operands: Operation: Status Affected: Description: Cycles: XORIA Syntax: Operands: Operation: Status Affected: Description: Cycles: TLC156 Exclusive OR ACC with R XORAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC xor R à dest Z Exclusive OR the contents of the ACC register with register ’R’. If ‘d’is 0 the result is stored in the ACC register. If ‘d’is 1 the result is stored back in register ‘R’. 1 Exclusive OR Immediate with ACC XORIA I 0 ≤ I ≤ 255 ACC xor I à ACC Z The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 4.0 ABSOLUTE MAXIMUM RATINGS Ambient Operating Temperature Store Temperature DC Supply Voltage (Vdd) Input Voltage with respect to Ground (Vss) 0℃ to +70℃ -65℃ to +150℃ 0V to +6.0V -0.3V to (Vdd + 0.3)V 5.0 OPERATING CONDITIONS DC Supply Voltage Operating Temperature +2.3V to +5.5V 0℃ to +70℃ Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 6.0 ELECTRICAL CHARACTERISTICS 6.1 ELECTRICAL CHARACTERISTICS of TLC154/156 Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled Sym Description FHF X’tal oscillation range FXT X’tal oscillation range FLF X’tal oscillation range FRC RC oscillation range VIH VIL Input high voltage Input low voltage Conditions Min. Typ. Max. HF mode, Vdd=5V 1 20 HF mode, Vdd=3V 1 15 XT mode, Vdd=5V 0.5 10 XT mode, Vdd=3V 0.5 10 LF mode, Vdd=5V 32 4000 LF mode, Vdd=3V 32 1000 RC mode, Vdd=5V DC 15 RC mode, Vdd=3V DC 7 I/O ports, Vdd=5V 2.0 RSTB, T0CKI pins, Vdd=5V 4.0 I/O ports, Vdd=3V 1.5 RSTB, T0CKI pins, Vdd=3V 2.4 I/O ports, Vdd=5V 1.0 RSTB, T0CKI pins, Vdd=5V 1.0 I/O ports, Vdd=3V 0.6 RSTB, T0CKI pins, Vdd=3V 0.6 Output high voltage IOH=-5.4mA, Vdd=5V VOL Output low voltage IOL=8.7mA, Vdd=5V IPH Pull-high current Input pin at Vss, Vdd=5V -45 IPD Pull-down current Input pin at Vdd, Vdd=5V 35 Vdd=5V 9 12 2 20.4 17.9 16.2 30 23 6.8 4 WDT current TWDT WDT period ILVDT LVDT current Vdd=3V Vdd=3V Vdd=4V Vdd=5V Vdd=5V LVDT = 3.6V Vdd=5V LVDT = 2V Vdd=3V LVDT = 2V Sleep mode, Vdd=5V, WDT enable ISB Power down current MHz MHz KHZ MHz V VOH IWDT Unit 3.6 V V 0.6 V uA uA uA mS 40 30 8.0 uA 20 Sleep mode, Vdd=5V, WDT disable 3 Sleep mode, Vdd=3V, WDT enable 2.5 Sleep mode, Vdd=3V, WDT disable 1.1 uA HF mode, Vdd=5V, 4 clock instruction IDD Operating current 20MHz 2.04 15MHz 1.68 10MHz 1.28 4MHz 0.78 2MHz 0.62 mA Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 HF mode, Vdd=3V, 4 clock instruction IDD Operating current 20MHz 0.92 15MHz 0.72 10MHz 0.54 4MHz 0.30 2MHz 0.19 mA HF mode, Vdd=5V, 2 clock instruction IDD Operating current 20MHz 2.94 15MHz 2.34 10MHz 1.74 4MHz 0.96 2MHz 0.68 mA HF mode, Vdd=3V, 2 clock instruction IDD Operating current 20MHz 1.38 15MHz 1.07 10MHz 0.77 4MHz 0.38 2MHz 0.24 mA XT mode, Vdd=5V, 4 clock instruction IDD Operating current 20MHz 1.69 15MHz 1.36 10MHz 1.04 4MHz 0.64 2MHz 0.49 mA XT mode, Vdd=3V, 4 clock instruction IDD Operating current 20MHz 0.78 15MHz 0.60 10MHz 0.44 4MHz 0.24 2MHz 0.17 mA XT mode, Vdd=5V, 2 clock instruction IDD Operating current 20MHz 2.81 15MHz 2.20 10MHz 1.60 4MHz 0.87 2MHz 0.61 mA XT mode, Vdd=3V, 2 clock instruction IDD Operating current 20MHz 1.36 15MHz 1.05 10MHz 0.73 4MHz 0.36 2MHz 0.23 mA Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 LF mode, Vdd=5V, 4 clock instruction IDD Operating current 2MHz 290 1MHz 208 500KHz 167 100KHz 118 32KHz 101 uA LF mode, Vdd=3V, 4 clock instruction IDD Operating current 2MHz 105 1MHz 73 500KHz 54 100KHz 33 32KHz 26 uA LF mode, Vdd=5V, 2 clock instruction IDD Operating current 2MHz 371 1MHz 269 500KHz 194 100KHz 130 32KHz 108 uA LF mode, Vdd=3V, 2 clock instruction IDD IDD Operating current Operating current 2MHz 158 1MHz 100 500KHz 67 100KHz 38 32KHz 29 mA RC mode, Vdd=5V, 4 clock instruction R=1Kohm C=3P C=20P C=100P C=300P uA F=14.96MHz 4.572 R=3.3Kohm F=11.06MHz 1.845 R=10Kohm F=5.80MHz 0.761 R=100Kohm F=808KHz 0.170 R=300Kohm R=1Kohm F=276KHz F=11.7MHz 0.119 4.226 R=3.3Kohm F=6.35MHz 1.519 R=10Kohm F=2.73MHz 0.613 R=100Kohm F=320KHz 0.147 R=300Kohm R=1Kohm F=108KHz F=5.23MHz 0.109 3.429 R=3.3Kohm F=2.05MHz 1.163 R=10Kohm F=748KHz 0.454 R=100Kohm R=300Kohm F=80KHz F=26.4KHz 0.126 0.100 R=1Kohm F=2.5MHz 3.024 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 R=3.3Kohm F=900KHz 1.021 R=10Kohm F=316KHz 0.403 R=100Kohm F=32KHz R=300Kohm F=10.67KHz RC mode, Vdd=3V, 4 clock instruction C=3P C=20P IDD Operating current C=100P C=300P R=1Kohm F=8.29MHz 2.280 R=3.3Kohm F=7.2MHz 0.913 R=10Kohm F=4.58MHz 0.396 R=100Kohm R=300Kohm F=900KHz F=316KHz 0.071 0.040 R=1Kohm F=7MHz 2.214 R=3.3Kohm F=5.1MHz 0.837 R=10Kohm F=2.71MHz 0.327 R=100Kohm F=374KHz 0.058 R=300Kohm R=1Kohm F=128KHz F=4.14MHz 0.035 2.060 R=3.3Kohm F=2.11MHz 0.688 R=10Kohm F=848KHz 0.253 R=100Kohm F=96KHz 0.047 R=300Kohm F=32KHz 0.030 R=1Kohm F=2.36MHz 1.890 R=3.3Kohm F=972KHz 0.630 R=10Kohm F=360KHz 0.226 R=100Kohm F=38KHz 0.043 R=300Kohm F=12.71KHz RC mode, Vdd=5V, 2 clock instruction C=3P C=20P IDD Operating current C=100P C=300P 0.119 0.098 mA 0.028 R=1Kohm F=15.16MHz 5.435 R=3.3Kohm F=11.27MHz 2.358 R=10Kohm F=5.77MHz 986 R=100Kohm F=826KHz 0.183 R=300Kohm R=1Kohm F=274KHz F=11.56MHz 0.108 4.835 R=3.3Kohm F=6.12MHz 1.808 R=10Kohm F=2.72MHz 0.701 R=100Kohm F=308KHz 0.138 R=300Kohm R=1Kohm F=105KHz F=5.32MHz 0.092 3.680 R=3.3Kohm F=1.99MHz 1.234 R=10Kohm F=722KHz 0.479 R=100Kohm F=77KHz 0.110 R=300Kohm F=25.0KHz 0.081 R=1Kohm F=2.52MHz 3.107 R=3.3Kohm F=892KHz 1.057 R=10Kohm F=312KHz 0.398 R=100Kohm R=300Kohm F=32KHz F=11KHz 0.102 0.077 mA Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 RC mode, Vdd=3V, 2 clock instruction C=3P C=20P IDD Operating current C=100P C=300P R=1Kohm F=8.306MHz 2.552 R=3.3Kohm F=7.29MHz 1.130 R=10Kohm F=4.81MHz 0.518 R=100Kohm F=904KHz 0.084 R=300Kohm R=1Kohm F=338KHz F=7.08MHz 0.039 2.445 R=3.3Kohm F=5.07MHz 0.986 R=10Kohm F=2.68MHz 0.393 R=100Kohm F=362KHz 0.061 R=300Kohm F=123KHz 0.031 R=1Kohm F=4.11MHz 2.197 R=3.3Kohm F=2.03MHz 0.745 R=10Kohm F=810KHz 0.270 R=100Kohm F=91KHz 0.043 R=300Kohm R=1Kohm F=30KHz F=2.37MHz 0.025 1.953 R=3.3Kohm F=964KHz 0.648 R=10Kohm F=354KHz 0.231 R=100Kohm R=300Kohm F=38KHz F=13KHz 0.038 0.022 mA 6.2 ELECTRICAL CHARACTERISTICS of TLC155/157 To be defined 6.3 ELECTRICAL CHARACTERISTICS of TLC154/156 To be defined 6.4 ELECTRICAL CHARACTERISTICS of TLC155/157 To be defined Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7.0 PACKAGE DIMENSION 7.1 18-PIN PDIP 300mil E1 E eB 15o(4x) D TOP E-PIN INDENT £ 0.079 BOTTOM E-PIN INDENT £ 0.118 C L A1 A A2 0.727 e B B1 Symbols D1 Dimension In Millimeters Min Dimension In Inches Nom Max Min Nom Max A - - 4.57 - - 0.180 A1 0.13 - - 0.005 - - A2 - 3.30 3.56 - 0.130 0.140 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 1.27 1.52 1.78 0.050 0.060 0.070 C 0.20 0.25 0.33 0.008 0.010 0.013 D 22.71 22.96 23.11 0.894 0.904 0.910 D1 0.43 0.56 0.69 0.017 0.022 0.027 E 7.62 - 8.26 0.300 - 0.325 E1 6.40 6.50 6.65 0.252 0.256 0.262 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7o(4x) 7.2 18-PIN SOP 300mil C 0.020x45o E H View “ A D View “ A e B A1 A2 A 7o(4x) £ L Symbols Dimension In Millimeters Dimension In Inches Min Nom Max Min Nom Max A 2.36 2.49 2.64 0.093 0.098 0.104 A1 0.10 - 0.30 0.04 - 0.012 A2 - 2.31 - - 0.091 - B 0.33 0.41 0.51 0.013 0.016 0.020 C 0.18 0.23 0.28 0.007 0.009 0.011 D 11.35 - 11.76 0.447 - 0.463 E 7.39 7.49 7.59 0.291 0.295 0.299 e - 1.27 - - 0.050 - H 10.01 10.31 10.64 0.394 0.406 0.419 L 0.38 0.81 1.27 0.015 0.032 0.050 θ 0° - 8° 0° - 8° Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7.3 20-PIN SSOP 209mil D E E1 View “ A C b A2 -HA1 A e 0.004max. L View “ A Symbols £o GAUGE PLANE SEATING PLANE L1 Dimension In Millimeters Min Nom Max A - - 2.00 A1 0.05 - - A2 1.65 1.75 1.85 b 0.22 - 0.38 c 0.09 - 0.21 D 6.90 7.20 7.50 E 7.40 7.80 8.20 E1 5.00 5.30 5.60 e - 0.65 - L 0.55 0.75 0.95 L1 - 1.25 o 0 θ o 4 o o 8 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7.4 28-PIN PDIP 600mil eB L A1 A A2 E E1 15o(4x) D e B1 B Symbols Dimension In Millimeters Dimension In Inches Min Nom Max Min Nom Max A - - 5.59 - - 0.220 A1 0.38 - - 0.015 - - A2 3.81 3.94 4.06 0.150 0.155 0.160 B - 1.52 - - 0.06 - B1 - 0.46 - - 0.018 - D 36.96 37.08 37.34 1.455 1.460 1.470 E - 15.24 - - 0.600 - E1 13.72 13.84 13.97 0.540 0.545 0.550 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - eB 16.00 16.51 17.02 0.630 0.650 0.670 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7.5 28-PIN Skinny PDIP 300mil eB E E1 15o(4x) D C 1.000¡ L A1 A A2 PIN 1 INDENT e B B1 Symbols B2 Dimension In Millimeters Min Dimension In Inches Nom Max Min Nom Max A - - 4.57 - - 0.180 A1 0.38 - - 0.015 - - A2 - 3.30 3.56 - 0.130 0.140 B 1.02 - 1.65 0.0040 - 0.065 B1 0.41 - 0.58 0.016 - 0.023 B2 0.71 - 1.12 0.028 - 0.044 C 0.20 0.25 0.33 0.008 0.010 0.013 D 35.13 35.18 35.43 1.383 1.385 1.395 E 7.87 8.31 8.38 0.310 0.327 0.330 E1 7.26 7.32 7.52 0.284 0.288 0.296 e - 2.54 - - 0.100 - L 3.18 - - 0.125 - - eB 8.64 - 9.65 0.340 - 0.380 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7o(4x) 7.6 28-PIN SOP 300mil C 0.020x45o E eB View “ A D View “ A A2 A 7o(4x) e B A1 D1 £ L Symbols Dimension In Millimeters Dimension In Inches Min Nom Max Min Nom Max A - 2.488 A1 0.152 - 2.743 - 0.098 0.108 - 0.006 - - A2 2.21 B 0.305 2.336 2.464 0.087 0.091 0.097 0.406 0.508 0.012 0.016 0.020 C D 0.204 0.254 0.304 0.008 0.010 0.012 17.78 17.91 18.42 0.700 0.705 0.725 E 7.366 7.493 7.62 0.290 0.295 0.300 e 1.219 1.270 1.321 0.048 0.050 0.052 eB 10.26 10.42 10.57 0.404 0.410 0.416 L 0.635 - - 0.025 - - θ 0° 4° 8° 0° 4° 8° D1 0.356 0.508 - 0.014 0.020 - Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 7.7 28-PIN SSOP 209mil D E E1 View “ A C b e A2 -HA1 A R 0.10 L £o GAUGE PLANE SEATING PLANE View “ A Dimension In Millimeters Symbols Min Nom Max A - - 2.00 A1 0.05 - - A2 1.62 1.75 1.85 b 0.22 - 0.38 c 0.09 - 0.25 D 9.90 10.20 10.50 E 7.40 7.80 8.20 E1 5.00 5.30 5.60 e 0.65 BSC 10.42 10.57 L 0.55 0.75 0.95 R 0.09 o θ 0 o 4 o o 8 Rev0.95 Nov 20, 2003 P.2/TLC156 TLC TLC156 8.0 ORDERING INFORMATION OTP Type MCU Package Type Pin Count Package Size TLC154EP PDIP 18 300 mil TLC154ED SOP 18 300 mil TLC154ER SSOP 20 209 mil TLC155EP PDIP 28 600 mil TLC155EM Skinny PDIP 28 300 mil TLC155ED SOP 28 300 mil TLC155ER SSOP 28 209 mil TLC156EP PDIP 18 300 mil TLC156ED SOP 18 300 mil TLC156ER SSOP 20 209 mil TLC157EP PDIP 28 600 mil TLC157EM Skinny PDIP 28 300 mil TLC157ED SOP 28 300 mil TLC157ER SSOP 28 209 mil Mask Type MCU Package Type Pin Count Package Size TLC154P PDIP 18 300 mil TLC154D SOP 18 300 mil TLC154R SSOP 20 209 mil TLC155P PDIP 28 600 mil TLC155M Skinny PDIP 28 300 mil TLC155D SOP 28 300 mil TLC155R SSOP 28 209 mil TLC156P PDIP 18 300 mil TLC156D SOP 18 300 mil TLC156R SSOP 20 209 mil TLC157P PDIP 28 600 mil TLC157M Skinny PDIP 28 300 mil TLC157D SOP 28 300 mil TLC157R SSOP 28 209 mil Rev0.95 Nov 20, 2003 P.2/TLC156