PLL PLL602-03HOC-R

PLL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
FEATURES
•
•
•
•
•
Low phase noise XO output for the 48MHz to
100MHz range (-130 dBc at 10kHz offset).
12 to 25MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Low jitter (RMS): 3ps period jitter (1 sigma).
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
3.3V operation.
Available in 8-Pin TSSOP or SOIC.
DESCRIPTION
CLK
1
VDD
2
OE^
3
XIN
4
PLL602-03
•
•
PIN CONFIGURATION
8
GND
7
GND
6
N/C
5
XOUT
Note: ^ denotes internal pull up
OUTPUT RANGE
FREQUENCY
RANGE
48 - 100MHz
MULTIPLIER
X4
The PLL602-03 is a low cost, high performance and
low phase noise XO, providing less than -130dBc at
10kHz offset in the 48MHz to 100MHz operating
range. The very low jitter (3ps RMS period jitter)
makes this chip ideal for applications requiring clean
reference frequency sources. Input crystal can range
from 12 to 25MHz (fundamental resonant mode).
OUTPUT
BUFFER
CMOS
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
XIN
XOUT
XTAL
OSC
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
PLL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
PIN DESCRIPTIONS
Name
Number
Type
Description
CLK
1
O
Output clock.
VDD
2
P
power supply.
OE
3
I
Output enable input. Disables (tri-state) output when low. Internal pull-up
enables output by default if pin is not connected to low.
XIN
4
I
Crystal input. See Crystal Specification on page 3.
XOUT
5
I
Crystal output. See Crystal Specification on page 3.
N/C
6
-
Not connected.
GND
7, 8
P
Ground.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
V DD
VI
VO
TS
TA
TJ
-0.5
-0.5
-65
-40
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
MAX.
UNITS
4.6
V DD +0.5
V DD +0.5
150
85
125
260
2
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. DC Specifications
PARAMETERS
Supply Current, Dynamic, with
Loaded Outputs
Operating Voltage
SYMBOL
I DD
CONDITIONS
MIN.
F XIN = 12 - 25MHz
Output load of 10pF
V DD
TYP.
MAX.
UNITS
16
20
mA
3.63
V
2.97
Output drive current
(High Drive)
I OH
V OH = V DD -0.4V, V DD =3.3V
30
mA
I OL
V OL = 0.4V, V DD = 3.3V
30
mA
Output drive current
(Standard Drive)
I OH
V OH = V DD -0.4V, V DD =3.3V
10
mA
I OL
V OL = 0.4V, V DD = 3.3V
10
mA
Short Circuit Current
±50
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2
PLL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
3. AC Specifications
PARAMETERS
SYMBOL
CONDITIONS
Input Crystal Frequency
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
Output Clock Duty Cycle
MIN.
TYP.
12
0.3V ~ 3.0V with 15 pF load
2.4
0.3V ~ 3.0V with 15 pF load
1.2
Measured @ 50% V DD
45
MAX.
UNITS
25
MHz
ns
50
55
%
4. Jitter and Phase Noise Specification
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
at 80MHz, with capacitive decoupling
between VDD and GND.
80MHz @100Hz offset
3.5
ps
-103
dBc/Hz
Phase Noise relative to carrier
80MHz @1kHz offset
-122
dBc/Hz
Phase Noise relative to carrier
80MHz @10kHz offset
-130
dBc/Hz
Phase Noise relative to carrier
80MHz @100kHz offset
-125
dBc/Hz
5. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance Rating
Driving power
ESR
SYMBOL
MIN.
F XIN
C L (xtal)
12
TYP.
MAX.
UNITS
25
MHz
pF
mW
30
Ω
20
1
RS
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
TSSOP
Narrow SOIC
Symbol
Min.
Max.
Min.
Max.
A
1.47
1.73
-
1.20
A1
0.10
0.25
0.05
0.15
B
0.33
0.51
0.19
0.30
C
0.19
0.25
0.09
0.20
D
4.80
4.95
2.90
3.10
E
3.80
4.00
4.30
4.50
H
5.80
6.20
6.20
6.60
L
0.38
1.27
0.45
e
1.27 BSC
E
H
D
A
0.75
0.65 BSC
A1
C
L
e
B
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3
PLL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-03 (H) X C
PART NUMBER
Optional High Drive
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
Order Number
Marking
Package Option
PLL602-03OC-R
PLL602-03OC
PLL602-03HOC-R
PLL602-03HOC
PLL602-03OC
PLL602-03OC
PLL602-03HOC
PLL602-03HOC
TSSOP
TSSOP
TSSOP
TSSOP
PLL602-03SC-R
PLL602-03SC
PLL602-03HSC-R
PLL602-03HSC
PLL602-03SC
PLL602-03SC
PLL602-03HSC
PLL602-03HSC
SOIC
SOIC
SOIC
SOIC
- Tape and Reel
– Tube
- Tape and Reel
– Tube
- Tape and Reel
– Tube
- Tape and Reel
- Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/14/00 Page 4