NTLJS4114N Power MOSFET 30 V, 7.8 A, mCoolt Single N−Channel, 2x2 mm WDFN Package Features • WDFN Package Provides Exposed Drain Pad for Excellent Thermal • • • • • Conduction 2x2 mm Footprint Same as SC−88 Lowest RDS(on) in 2x2 mm Package 1.8 V RDS(on) Rating for Operation at Low Voltage Logic Level Gate Drive Low Profile (< 0.8 mm) for Easy Fit in Thin Environments This is a Pb−Free Device http://onsemi.com RDS(on) MAX V(BR)DSS ID MAX (Note 1) 35 mW @ 4.5 V 30 V 7.8 A 45 mW @ 2.5 V 55 mW @ 1.8 V S Applications • DC−DC Conversion • Boost Circuits for LED Backlights • Optimized for Battery and Load Management Applications in G Portable Equipment such as, Cell Phones, PDA’s, Media Players, etc. • Low Side Load Switch for Noisy Environment D N−CHANNEL MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Parameter Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±12 V ID 6.0 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C 4.4 t≤5s TA = 25°C 7.8 Steady State PD Power Dissipation (Note 2) Pulsed Drain Current ID TA = 85°C TA = 25°C tp = 10 ms WDFN6 CASE 506AP STYLE 1 1 2 3 6 JA M G 5 G 4 PIN CONNECTIONS A 3.6 2.6 PD 0.70 IDM 28 A −55 to 150 °C Source Current (Body Diode) (Note 2) IS 3.0 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. © Semiconductor Components Industries, LLC, 2006 D 1 D 2 G 3 6 D 5 D 4 S W TJ, TSTG Operating Junction and Storage Temperature November, 2006 − Rev. 1 MARKING DIAGRAM JA = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 3.3 TA = 25°C Steady State Pin 1 D TA = 25°C t≤5s Continuous Drain Current (Note 2) W 1.92 S 1 D S (Top View) ORDERING INFORMATION Device Package Shipping† NTLJS4114NT1G WDFN6 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTLJS4114N/D NTLJS4114N THERMAL RESISTANCE RATINGS Symbol Max Junction−to−Ambient – Steady State (Note 3) Parameter RqJA 65 Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA 38 Junction−to−Ambient – Steady State Min Pad (Note 4) RqJA 180 Unit °C/W 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min 30 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = 250 mA, Ref to 25°C Zero Gate Voltage Drain Current IDSS VDS = 24 V, VGS = 0 V mV/°C TJ = 25°C 1.0 TJ = 85°C 10 IGSS VDS = 0 V, VGS = ±12 V VGS(TH) VGS = VDS, ID = 250 mA Gate−to−Source Leakage Current V 20 ±100 mA nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Gate Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(TH)/TJ 0.55 1.0 3.18 RDS(on) Forward Transconductance 0.4 gFS V mV/°C VGS = 4.5 V, ID = 2.0 A 20.3 35 VGS = 2.5 V, ID = 2.0 A 25.8 45 VGS = 1.8 V, ID = 1.8 A 35.2 55 VDS = 16 V, ID = 2.0 A 8 S 650 pF mW CHARGES, CAPACITANCES AND GATE RESISTANCE CISS Input Capacitance VGS = 0 V, f = 1.0 MHz, VDS = 15 V Output Capacitance COSS Reverse Transfer Capacitance CRSS 70 Total Gate Charge QG(TOT) 8.5 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 2.1 RG 3.0 W td(ON) 5 ns tr 9 Gate Resistance VGS = 4.5 V, VDS = 15 V, ID = 2.0 A 115.5 13 nC 0.6 0.9 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(OFF) VGS = 4.5 V, VDD = 15 V, ID = 2.0 A, RG = 3.0 W tf 20 4 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time VSD VGS = 0 V, IS = 2.0 A TJ = 25°C 0.71 TJ = 85°C 0.58 tRR 14 ta 8.0 tb VGS = 0 V, dISD/dt = 100 A/ms, IS = 1.0 A QRR http://onsemi.com 2 V 35 ns 6.0 5.0 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. 1.2 nC NTLJS4114N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 7 8 VGS = 1.6 V to 8 V VDS ≥ 10 V TJ = 25°C 1.5 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 6 5 1.4 V 4 3 1.3 V 2 1.2 V 1 4 TJ = 25°C 2 TJ = 100°C 1 1.5 2 2.5 3 4 3.5 4.5 5 5.5 0 6 1.5 1 0.5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.03 VGS = 4.5 V TJ = 100°C 0.025 TJ = 25°C 0.02 TJ = −55°C 0.015 0.01 0.005 1.0 1.5 3.0 2.5 2.0 3 2.5 2 VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 0.5 0.05 TJ = 25°C 0.04 VGS = 1.8 V 0.03 VGS = 2.5 V 0.02 VGS = 4.5 V 0.01 0 1 2 3 ID, DRAIN CURRENT (A) 4 5 6 ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Gate Voltage 100000 1.6 ID = 2 A VGS = 4.5 V TJ = 150°C 1.4 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 6 1.2 1.0 VGS = 0 V 10000 TJ = 100°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 1000 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 NTLJS4114N C, CAPACITANCE (pF) VDS = 0 V VGS = 0 V TJ = 25°C Ciss 1000 400 Coss Crss −200 5 5 0 VGS 15 10 20 25 QT 4 VDS 3 VGS QGS 8 4 1 ID = 2 A TJ = 25°C 0 30 16 12 QGD 2 0 8 4 QG, TOTAL GATE CHARGE (nC) 0 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 IS, SOURCE CURRENT (AMPS) 4 VDD = 15 V ID = 3.0 A VGS = 4.5 V td(off) 100 tf tr td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V TJ = 25°C 3 2 1 0 0.3 1 100 0.4 0.5 See Note 2 on Page 1 10 ms 10 100 ms 1 ms 1 0.01 10 ms SINGLE PULSE TC = 25°C TJ = 150°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.7 0.8 Figure 10. Diode Forward Voltage versus Current 100 0.1 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance I D, DRAIN CURRENT (AMPS) t, TIME (ns) 20 5 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1600 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTLJS4114N EFFECTIVE TRANSIENT THERMAL RESISTANCE TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 1000 100 D = 0.5 0.2 0.1 10 0.05 P(pk) 0.02 0.01 1 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.1 0.000001 See Note 2 on Page 1 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 Figure 12. Thermal Response http://onsemi.com 5 1 10 100 1000 NTLJS4114N PACKAGE DIMENSIONS WDFN6 2x2 CASE 506AP−01 ISSUE B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL LEAD IS CONNECTED TO TERMINAL LEAD # 4. 6. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG. A B ÍÍÍ ÍÍÍ ÍÍÍ E PIN ONE REFERENCE STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN 0.10 C 2X 0.10 C 2X DIM A A1 A3 b b1 D D2 E E2 e K L L2 J J1 A3 0.10 C A 0.08 C 7X A1 C D2 6X SEATING PLANE 4X SOLDERING FOOTPRINT* e L2 L 1 2.30 3 b1 0.10 C A B 1 b 0.60 1.25 NOTE 5 4 6X 0.35 0.43 0.05 C 6 1.10 6X 6X E2 K MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 0.51 0.61 2.00 BSC 1.00 1.20 2.00 BSC 1.10 1.30 0.65 BSC 0.15 REF 0.20 0.30 0.20 0.30 0.27 REF 0.65 REF 6X J J1 0.10 C A 0.05 C 0.35 B NOTE 3 0.34 BOTTOM VIEW 0.65 PITCH 0.66 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTLJS4114N/D