SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 FEATURES • • • • • Member of Texas Instruments Widebus+™ Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Supports Mixed-Mode Signal Operation (5-V • • • Input and Output Voltages With 3.3-V VCC) Supports Unregulated Battery Operation Down to 2.7 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) GKE OR ZKE PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS 1 2 3 4 5 6 A 1Y2 1Y1 1OE 2OE 1A1 1A2 B 1Y4 1Y3 GND GND 1A3 1A4 C 2Y2 2Y1 1VCC 1VCC 2A1 2A2 D 2Y4 2Y3 GND GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 F 3Y4 3Y3 1VCC 1VCC 3A3 3A4 E G 4Y2 4Y1 GND GND 4A1 4A2 F H 4Y3 4Y4 4OE 3OE 4A4 4A3 G J 5Y2 5Y1 5OE 6OE 5A1 5A2 H K 5Y4 5Y3 GND GND 5A3 5A4 J L 6Y2 6Y1 2VCC 2VCC 6A1 6A2 K M 6Y4 6Y3 GND GND 6A3 6A4 L N 7Y2 7Y1 GND GND 7A1 7A2 P 7Y4 7Y3 2VCC 2VCC 7A3 7A4 R 8Y2 8Y1 GND GND 8A1 8A2 T 8Y3 8Y4 8OE 7OE 8A4 8A3 1 2 3 4 5 6 A B C D M N P R T DESCRIPTION/ORDERING INFORMATION The SN74LVT32244 is a 32-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) BGA – GKE BGA – ZKE (Pb-free) ORDERABLE PART NUMBER Reel of 1000 SN74LVT32244GKER SN74LVT32244ZKER TOP-SIDE MARKING VJ244 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2006, Texas Instruments Incorporated SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. The device provides true outputs and has symmetrical active-output-enable (OE) inputs. It is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE (each 4-bit buffer/driver) INPUTS 2 OE A OUTPUT Y L H H L L L H X Z Submit Documentation Feedback SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 5OE 5A1 5A2 5A3 5A4 6OE 6A1 6A2 6A3 6A4 A3 3OE A5 A2 A6 A1 B5 B2 B6 B1 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 A4 4OE C5 C2 C6 C1 D5 D2 D6 D1 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 J3 7OE J5 J2 J6 J1 K5 K2 K6 K1 5Y1 7A1 5Y2 7A2 5Y3 7A3 5Y4 7A4 J4 8OE L5 L2 L6 L1 M5 M2 M6 M1 6Y1 8A1 6Y2 8A2 6Y3 8A3 6Y4 8A4 H4 E5 E2 E6 E1 F5 F2 F6 F1 3Y1 3Y2 3Y3 3Y4 H3 G5 G2 G6 G1 H6 H1 H5 H2 4Y1 4Y2 4Y3 4Y4 T4 N5 N2 N6 N1 P5 P2 P6 P1 7Y1 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 T5 T2 Submit Documentation Feedback 8Y1 8Y2 8Y3 8Y4 3 SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high state (2) IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 –50 mA 40 °C/W 150 °C θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) GKE/ZKE package –65 V 128 mA 64 mA –50 mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MAX 2.7 3.6 UNIT Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 VI Input voltage 5.5 V IOH High-level output current –32 mA IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate 200 TA Operating free-air temperature –40 (1) 4 MIN VCC V 2 Outputs enabled V V 64 mA 10 ns/V µs/V 85 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback °C SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 2.7 V, II = –18 mA VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC = 2.7 V, IOH = –8 mA VCC = 3 V, IOH = –32 mA VCC = 2.7 V VOL VCC = 3 V Control inputs II Data inputs MIN TYP (1) MAX UNIT –1.2 V VCC – 0.2 2.4 V 2 IOL = 100 µA 0.2 IOL = 24 mA 0.5 IOL = 16 mA 0.4 IOL = 32 mA 0.5 IOL = 64 mA 0.55 VCC = 0 or 3.6 V, VI = 5.5 V 10 VCC = 3.6 V, VI = VCC or GND ±1 VCC = 3.6 V VI = VCC 1 VI = 0 V µA –5 ±100 µA 5 µA –5 µA ±100 µA Ioff VCC = 0, VI or VO = 0 to 4.5 V IOZH VCC = 3.6 V, VO = 3 V IOZL VCC = 3.6 V, VO = 0.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care ±100 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.38 Outputs low 10 Outputs disabled mA 0.38 ∆ICC (2) VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 4 pF Co VO = 3 V or 0 9 pF (1) (2) 0.2 mA All typical values are at VCC = 3.3 V, TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Submit Documentation Feedback 5 SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ (1) 6 FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN TYP (1) MAX 1.2 2.3 3.2 3.7 1.2 2 3.2 3.7 1.2 2.6 4 5 1.2 2.7 4 5 2.2 3.3 4.5 5 2 3.1 4.2 4.4 tsk(LH) 0.5 tsk(HL) 0.5 All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback MIN MAX ns ns ns ns SN74LVT32244 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCBS748C – OCTOBER 2000 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 2.7 V Input 1.5 V 1.5 V 0V tPHL tPLH VOH Output 1.5 V 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH tPLH VOH Output 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2007 PACKAGING INFORMATION Status (1) Package Type Package Drawing SN74LVT32244GKER NRND LFBGA GKE 96 1000 SN74LVT32244ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) Orderable Device Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish MSL Peak Temp (3) SNPB Level-3-220C-168 HR SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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