19-3720; Rev 0; 11/06 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs The MAX1391/MAX1394 micropower, serial-output, 8-bit, analog-to-digital converters (ADCs) operate with a single power supply from +1.5V to +3.6V. These ADCs feature automatic shutdown, fast wake-up, and a highspeed 3-wire interface. Power consumption is only 0.743mW (VDD = +1.5V) at the maximum conversion rate of 416ksps. AutoShutdown™ between conversions reduces power consumption at slower throughput rates. The MAX1391/MAX1394 require an external reference V REF that has a wide range from 0.6V to V DD . The MAX1391 provides one true-differential analog input that accepts signals ranging from 0 to VREF (unipolar mode) or ±VREF/2 (bipolar mode). The MAX1394 provides two single-ended inputs that accept signals ranging from 0 to V REF . Analog conversion results are available through a 5MHz 3-wire SPI™-/QSPI™-/ MICROWIRE™-/digital signal processor (DSP)-compatible serial interface. Excellent dynamic performance, low voltage, low power, ease of use, and small package sizes make these converters ideal for portable battery-powered data-acquisition applications, as well as other applications that demand low-power consumption and minimal space. The MAX1391/MAX1394 are available in a space-saving (3mm x 3mm), 10-pin TDFN package. The parts operate over the extended (-40°C to +85°C) and military (-55°C to +125°C) temperature ranges. Features ♦ 416ksps, 8-Bit Successive-Approximation Register (SAR) ADCs ♦ Single True-Differential Analog Input Channel with Unipolar-/Bipolar-Selected Input (MAX1391) ♦ Dual Single-Ended Input Channel with ChannelSelected Input (MAX1394) ♦ ±0.2 LSB INL, ±0.2 LSB DNL, No Missing Codes ♦ ±0.25 LSB Total Unadjusted Error (TUE) ♦ 49dB SINAD at 100kHz Input Frequency ♦ Single-Supply Voltage (+1.5V to +3.6V) ♦ 0.97mW at 416ksps, 1.8V ♦ 0.230mW at 100ksps, 1.8V ♦ 3.1µW at 1ksps, 1.8V ♦ < 1µA Shutdown Current ♦ External Reference (0.6V to VDD) ♦ AutoShutdown Between Conversions ♦ SPI-/QSPI-/MICROWIRE-/DSP-Compatible, 3- or 4-Wire Serial Interface ♦ Small (3mm x 3mm), 10-Pin TDFN Applications Portable Datalogging Typical Operating Circuit and Pin Configurations appear at end of data sheet. Data Acquisition Medical Instruments AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Battery-Powered Instruments Process Control Ordering Information ANALOG INPUTS TOP MARK PKG CODE MAX1391ETB PART -40°C to +85°C TEMP RANGE 10 TDFN-EP* PIN-PACKAGE 1-CH DIFF AOX T1033-1 MAX1391MTB** -55°C to +125°C 10 TDFN-EP* 1-CH DIFF — T1033-1 MAX1394ETB -40°C to +85°C 10 TDFN-EP* 2-CH S/E APA T1033-1 MAX1394MTB** -55°C to +125°C 10 TDFN-EP* 2-CH S/E — T1033-1 *EP = Exposed pad. **Future product—contact factory for availability. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1391/MAX1394 General Description MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +4V SCLK, CS, OE, CH1/CH2, UNI/BIP, DOUT to GND.........................................-0.3V to (VDD + 0.3V) AIN+, AIN-, AIN1, AIN2, REF to GND ........-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 10-Pin TDFN (derate 18.5mW/°C above +70°C) ....1481.5mW Operating Temperature Ranges MAX139_E_ _...................................................-40°C to +85°C MAX139_M_ _ ................................................-55°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.2 LSB ±0.2 LSB ±0.15 LSB ±0.15 LSB ±0.25 LSB DC ACCURACY (Note 2) Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Bits No missing code overtemperature Offset Error Gain Error Offset nulled Total Unadjusted Error TUE Offset-Error Temperature Coefficient ±25 mLSB/°C Gain-Error Temperature Coefficient ±0.06 mLSB/°C Channel-to-Channel Offset Matching MAX1394 only ±0.05 LSB Channel-to-Channel Gain Matching MAX1394 only ±0.05 LSB VCM = 0 to VDD, MAX1391 only ±0.1 mV/V Input Common-Mode Rejection CMR DYNAMIC SPECIFICATIONS (Note 3) Signal-to-Noise Plus Distortion SINAD 49 dB Signal-to-Noise Ratio SNR 49 Total Harmonic Distortion THD -65 dBc Spurious-Free Dynamic Range SFDR -66 dBc dB fIN1 = 98kHz at -6.5dBFS, fIN2 = 102kHz at -6.5dBFS -73 dB Channel-to-Channel Crosstalk MAX1394 only -70 dB Full-Power Bandwidth -3dB point 4 MHz Intermodulation Distortion IMD Full-Linear Bandwidth SINAD > 48dB MAX1391 200 MAX1394 150 kHz CONVERSION RATE Conversion Time 2 tCONV 9 clock cycles per conversion 1.8 _______________________________________________________________________________________ µs 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP 12 clocks per conversion, includes powerup acquisiton and conversion time Throughput Rate Power-Up and Acquisition Time tACQ Three SCLK cycles MAX UNITS 416 ksps 600 ns Aperture Delay tAD 8 ns Aperture Jitter tAJ 30 ps Serial-Clock Frequency fCLK 0.1 5.0 MHz ANALOG INPUTS (AIN+, AIN-, AIN1, AIN2) Input Voltage Range VIN Common-Mode Input Voltage Range VCM Unipolar Bipolar, MAX1391 only, (AIN+ - AIN-) Bipolar, MAX1391 only, [(AIN+) + (AIN-)] / 2 0 VREF -VREF/2 +VREF/2 0 VDD V ±1.5 µA Channel not selected, or conversion stopped, or in shutdown mode Input Leakage Current Input Capacitance 16 V pF REFERENCE INPUT (REF) REF Input Voltage Range VREF VDD + 0.05 V 0.025 ±2.5 µA 20 60 µA 0.3 x VDD V 0.6 REF Input Capacitance 24 REF DC Leakage Current REF Input Dynamic Current 416ksps pF DIGITAL INPUTS (SCLK, CS, OE, CH1/CH2, UNI/BIP) Input-Voltage Low VIL Input-Voltage High VIH 0.7 x VDD V 0.06 x VDD Input Hysteresis Input Leakage Current Input Capacitance IIL CIN Inputs at GND or VDD V ±1 CS, OE 1 CH1/CH2, UNI/BIP µA pF 12.5 DIGITAL OUTPUT (DOUT) Output-Voltage Low VOL ISINK = 2mA Output-Voltage High VOH ISOURCE = 2mA Tri-State Leakage Current Tri-State Output Capacitance ILT OE = VDD COUT OE = VDD 0.1 x VDD 0.9 x VDD V V ±1 10 µA pF POWER SUPPLY Positive Supply Voltage VDD 1.5 3.6 V _______________________________________________________________________________________ 3 MAX1391/MAX1394 ELECTRICAL CHARACTERISTICS (continued) MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fSAMPLE = 100ksps Positive Supply Current (Note 4) Power-Supply Rejection IDD PSR fSAMPLE = 416ksps TYP MAX VDD = 1.6V MIN 125 150 VDD = 3V 150 200 VDD = 1.6V 520 600 VDD = 3V 710 800 Power-down mode (Note 5) 5 10 Power-down mode (Note 6) 0.2 ±2.5 ±150 ±1000 VDD = 1.6V to 3.6V, full-scale input (Note 7) UNITS µA µV/V TIMING CHARACTERISTICS (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10,000 ns SCLK Clock Period tCP 200 SCLK Pulse-Width High tCH 90 ns SCLK Pulse-Width Low tCL 90 ns CS Fall to SCLK Rise Setup tCSS 80 ns SCLK Rise to CS Fall Ignore tCSO SCLK Fall to DOUT Valid tDOV OE Rise to DOUT Disable tDOD 0 CLOAD = 0 to 30pF ns 10 80 ns 6 20 ns 9 20 ns OE Fall to DOUT Enable tDOE CS Pulse-Width High and Low tCSW 80 ns OE Pulse-Width High and Low tOEW 80 ns CH1/CH2 Setup Time (to the First SCLK) tCHS MAX1394 only 10 ns CH1/CH2 Hold Time (to the First SCLK) tCHH MAX1394 only 0 ns UNI/BIP Setup Time (to the First SCLK) tUBS MAX1391 only 10 ns UNI/BIP Hold Time (to the First SCLK) tUBH MAX1391 only 0 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 4 Devices are production tested at room and +85°C. Specification to -40°C are guaranteed by design. VDD = 1.6V, VREF = 1.6V, and VAIN = 1.6V. VDD = 1.6V, VREF = 1.6V, VAIN = 1.6VP-P, fSCLK = 5MHz, fSAMPLE = 416ksps, and fIN (sine wave) = 100kHz. All digital inputs swing between VDD and GND. VREF = VDD, fIN = 100kHz sine wave, VAIN = VREFP-P, CLOAD = 30pF on DOUT. CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is active. CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is inactive. Change in VAIN at code boundary 254.5. _______________________________________________________________________________________ 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs MAX1391/MAX1394 UNI/BIP OR CH1/CH2 tCHS tUBS OE tCHH tUBH tOEW CS tCSO tCH tCL tCSS tCSW SCLK tCP tDOE tDOV DOUT tDOD HIGH-Z HIGH-Z Figure 1. Detailed Serial-Interface Timing Diagram VDD 6kΩ DOUT 6kΩ DOUT 50pF 50pF GND GND a) HIGH IMPEDANCE TO VOH, VOL TO VOH, AND VOH TO HIGH IMPEDANCE b) HIGH IMPEDANCE TO VOL, VOH TO VOL, AND VOL TO HIGH IMPEDANCE Figure 2. Load Circuits for Enable/Disable Times _______________________________________________________________________________________ 5 Typical Operating Characteristics (VDD = +1.6V, VREF = +1.6V, CREF = 0.1µF, CL = 30pF, fSCLK = 5MHz. TA = +25°C, unless otherwise noted.) INL ERROR vs. REFERENCE VOLTAGE 0.02 0 -0.02 0.04 0.02 0.02 0 -0.02 -0.04 -0.06 -0.06 -0.08 -0.08 -0.10 -0.10 128 160 192 224 256 -0.08 -0.10 0.6 1.1 CODE DNL ERROR vs. REFERENCE VOLTAGE 0 -0.02 -0.04 -0.06 MIN DNL 64 96 128 160 192 224 256 AIN2 200 OFFSET ERROR vs. TEMPERATURE 400 300 100 0 -100 AIN1 AIN2 200 100 0 -100 -200 -200 -300 -300 -400 -400 AIN1 VDD = 3.6V 2.6 3.1 3.6 1.5 1.8 REFERENCE VOLTAGE (V) 2.1 2.4 2.7 3.0 3.3 3.6 -55 -25 SUPPLY VOLTAGE (V) GAIN ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. REFERENCE VOLTAGE 400 MAX1391/94 toc07 400 300 200 GAIN ERROR (µV) 200 100 0 -100 VREF = 1.5V TEMPERATURE = +25°C 300 AIN2 0 -100 AIN1 65 95 125 400 VDD = 2.6V 300 AIN2 200 100 0 -100 AIN1 -200 -300 -300 35 GAIN ERROR vs. TEMPERATURE 100 -200 -200 5 TEMPERATURE (°C) MAX1391/94 toc09 -0.10 2.1 32 CODE VREF = 1.5V TEMPERATURE = +25°C 300 OFFSET ERROR (µV) DNL ERROR (LSB) 0.02 1.6 0 3.6 OFFSET ERROR vs. SUPPLY VOLTAGE 0.04 1.1 3.1 OFFSET ERROR (µV) MAX DNL 0.6 2.6 400 MAX1391/94 toc04 VDD = 3.6V 0.08 -0.08 2.1 REFERENCE VOLTAGE (V) 0.10 0.06 1.6 GAIN ERROR (µV) 96 -0.06 MAX1391/94 toc05 64 0 -0.02 -0.04 MIN INL MAX1391/94 toc08 32 0.06 0.04 -0.04 0 MAX INL MAX1391/94 toc06 INL ERROR (LSB) INL (LSB) 0.04 0.06 VDD = 1.5V VREF = 1.5V 0.08 DNL (LSB) 0.06 VDD = 3.6V 0.08 0.10 MAX1391/94 toc02 MAX1391/94 toc01 0.08 DNL vs. CODE 0.10 MAX1391/94 toc03 INL vs. CODE 0.10 OFFSET ERROR (µV) MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs -300 VDD = 3.6V -400 -400 0.6 1.1 1.6 2.1 2.6 REFERENCE VOLTAGE (V) 6 3.1 3.6 -400 1.5 1.8 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 -55 -25 5 35 65 TEMPERATURE (°C) _______________________________________________________________________________________ 95 125 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs SUPPLY CURRENT vs. SUPPLY VOLTAGE -100 600 500 -200 400 REFERENCE VOLTAGE (V) SUPPLY CURRENT vs. CONVERSION RATE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 2.5 3.0 800 600 VDD = VREF = 3.0V 400 200 VDD = VREF = 1.6V 3.3 3.6 -55 0.4 0.3 0.2 0.1 1.6 1.2 VDD = 3.6V 0.8 VDD = 1.8V 0.4 1.8 2.1 2.4 2.7 3.0 3.3 3.6 -55 -25 5 35 65 95 TEMPERATURE (°C) SCLK-TO-DOUT TIMING FFT SAMPLING ERROR vs. SOURCE IMPEDANCE 0 MAX1391/94 toc16 VDD = 1.5V 60 50 40 30 VDD = 1.6V VREF = 1.6V fS = 417ksps fIN = 100.4kHz THD = -79.9dB SINAD = 49.0dB SFDR = -71.1dB -20 MAGNITUDE (dB) 70 -40 -60 VDD = 3.6V -80 20 125 2.0 VOLTAGE (V) 90 MAX1391/94 toc12 95 fSAMPLE (ksps) 100 80 65 0 1.5 100 150 200 250 300 350 400 35 125 0.3 MAX1391/94 toc18 50 5 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 0 0 -25 TEMPERATURE (°C) 0.5 0 DOUT DELAY (ns) 1.8 AIN HIGH-TO-LOW FS TRANSITION 0.2 SAMPLING ERROR (LSB) SUPPLY CURRENT (µA) fSCLK = 5MHz, fSAMPLE = 417ksps AIN = FULL SCALE, 100kHz SINE WAVE CL = 30pF 1.5 3.5 MAX1391/94 toc14 2.1 SHUTDOWN CURRENT (µA) 1.6 500 400 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 1.1 MAX1391/94 toc13 0.6 SHUTDOWN SUPPLY CURRENT (µA) -400 550 450 VREF = 1.5V, CL = 33pF fSCLK = 5MHz, fSAMPLE = 416ksps AIN = FULL SCALE, 10kHz SINE WAVE -300 VREF = 1.5V, CL = 33pF fSCLK = 5MHz, fSAMPLE = 416ksps AIN = FULL SCALE, 10kHz SINE WAVE MAX1391/94 toc15 0 SUPPLY CURRENT (µA) 100 700 MAX1391/94 toc17 GAIN ERROR (µV) 200 600 MAX1391/94 toc11 VDD = 3.6V 300 SUPPLY CURRENT vs. TEMPERATURE 800 SUPPLY CURRENT (µA) 400 MAX1391/94 toc10 GAIN ERROR vs. REFERENCE VOLTAGE 0.1 0 -0.1 AIN HIGH-TO-LOW FS TRANSITION -0.2 10 0 -0.3 -100 0 100 200 300 CLOAD (pF) 400 500 600 0 20 40 60 80 100 FREQUENCY (kHz) 120 140 0 500 1000 1500 2000 2500 SOURCE IMPEDANCE (Ω) _______________________________________________________________________________________ 7 MAX1391/MAX1394 Typical Operating Characteristics (continued) (VDD = +1.6V, VREF = +1.6V, CREF = 0.1µF, CL = 30pF, fSCLK = 5MHz. TA = +25°C, unless otherwise noted.) MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs Pin Description PIN MAX1391 MAX1394 1 1 NAME FUNCTION VDD Positive Supply Voltage. Connect VDD to a 1.6V to 3.6V power supply. Bypass VDD to GND with a 0.1µF capacitor as close as possible to the device. 2 — AIN- Negative Analog Input — 2 AIN2 Analog Input Channel 2 3 — AIN+ Positive Analog Input — 3 AIN1 Analog Input Channel 1 4 4 GND Ground 5 5 REF External Reference Voltage Input. VREF = 0.6V to (VDD + 0.05V). Bypass REF to GND with a 0.1µF capacitor as close as possible to the device. 6 — UNI/BIP Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to select bipolar input mode. In unipolar mode, the output data is in straight binary format. In bipolar mode, the output data is in two’s complement format. — 6 CH1/CH2 Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select channel 2. 7 7 OE Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT. Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface with DSP devices. 8 8 CS Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition. 9 9 DOUT Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high impedance when OE is high. 10 10 SCLK Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 11th falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10). — — EP Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave floating. VDD Detailed Description The MAX1391/MAX1394 use an input track and hold (T/H) circuit along with a SAR to convert an analog input signal to a serial 8-bit digital output data stream. The serial interface provides easy interfacing to microprocessors and DSPs. Figure 3 shows the simplified functional diagram for the MAX1391 (1 channel, true differential) and the MAX1394 (2 channels, single ended). True-Differential Analog Input T/H The equivalent input circuit of Figure 4 shows the MAX1391/MAX1394 input architecture that is composed of a T/H, a comparator, and a switched-capacitor DAC. The T/H enters its tracking mode on the falling edge of CS (while OE is held low). The positive input capacitor is connected to AIN+ (MAX1391), or to AIN1 or AIN2 (MAX1394). The negative input capacitor is connected to AIN- (MAX1391) or GND (MAX1394). The T/H enters its hold mode on the 3rd falling edge of SCLK and the dif8 CONTROL LOGIC AND TIMING AIN+ (AIN1)* AIN- (AIN2)* INPUT MUX AND T/H OUTPUT SHIFT REGISTER 8-BIT SAR ADC REF CS SCLK OE DOUT UNI/BIP (CH1/CH2)* MAX1391 MAX1394 GND *INDICATES THE MAX1394 Figure 3. Simplified Functional Diagram _______________________________________________________________________________________ 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs REF GND RSOURCE DAC AIN2 AIN1 (AIN+)* ANALOG SIGNAL SOURCE CIN+ MAX1391 MAX1394 COMPARATOR + HOLD GND (AIN-)* CINRIN- RIN+ HOLD VDD/2 (*INDICATES THE MAX1391) Figure 4. Equivalent Input Circuit HOLD Analog Input Bandwidth The ADC’s input-tracking circuitry has a 4MHz fullpower bandwidth, making it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Analog Input Range and Protection The MAX1391/MAX1394 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within their specified range. When operating the MAX1391 in unipolar mode (UNI/BIP = 1), the specified differential analog input range is from 0 to VREF. When operating in bipolar mode (UNI/BIP = 0), the differential analog input range is from -VREF/2 to +VREF/2 with a common-mode range of 0 to VDD. The MAX1394 has an input range from 0 to VREF. Internal protection diodes confine the analog input voltage within the region of the analog power input rails (VDD, GND) and allow the analog input voltage to swing from GND - 0.3V to VDD + 0.3V without damage. Input voltages beyond GND - 0.3V and VDD + 0.3V forward bias the internal protection diodes. In this situation, limit the forward diode current to less than 50mA to avoid damage to the MAX1391/MAX1394. Output Data Format Figures 8, 9, and 10 illustrate the conversion timing for the MAX1391/MAX1394. Twelve SCLK cycles are required to read the conversion result and data on DOUT transitions on the falling edge of SCLK. The conversion result contains 4 zeros, followed by 8 data bits with the data in MSB-first format. For the MAX1391, data is straight binary for unipolar mode and two’s complement for bipolar mode. For the MAX1394, data is always straight binary. TRACK Transfer Function Figure 5 shows the unipolar transfer function for the MAX1391/MAX1394. Figure 6 shows the bipolar transfer function for the MAX1391. Code transitions occur halfway between successive-integer LSB values. _______________________________________________________________________________________ 9 MAX1391/MAX1394 ference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. The required acquisition time lengthens as the input signal’s source impedance increases. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ ≥ 5.6 x (RSOURCE + RIN) x CIN + tPU where RSOURCE is the source impedance of the input signal. RIN = 500Ω, which is the equivalent differential analog input resistance. CIN = 16pF, which is the equivalent differential analog input capacitance. tPU = 400ns. Note: tACQ is never less than 600ns and any source impedance below 400Ω does not significantly affect the ADC’s AC performance. MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs 7F ZS = 0 FE 1 LSB = 7E VREF 256 +FS = VREF 2 ZS = 0 FULL-SCALE TRANSITION -VREF 2 V 1 LSB = REF 256 -FS = OUTPUT CODE (hex) FD OUTPUT CODE (hex) FULL-SCALE TRANSITION FS = VREF FF FC FB 04 01 00 FF FE 03 02 81 01 80 00 0 1 2 3 4 FS - 1.5 LSB INPUT VOLTAGE (LSB) FS Figure 5. Unipolar Transfer Function Applications Information Starting a Conversion A falling edge on CS initiates the power-up sequence and begins acquiring the analog input as long as OE is also asserted low. On the 3rd SCLK falling edge, the analog input is held for conversion. The most significant bit (MSB) decision is made and clocked onto DOUT on the 4th SCLK falling edge. Valid DOUT data is available to be clocked into the master (microcontroller (µC)) on the following SCLK rising edge. The rest of the bits are decided and clocked out to DOUT on each successive SCLK falling edge. See Figures 8 and 9 for conversion timing diagrams. Once a conversion has been initiated, CS can go high at any time. Further falling edges of CS do not reinitiate an acquisition cycle until the current conversion completes. Once a conversion completes, the first falling edge of CS begins another acquisition/conversion cycle. 10 -FS 0 -FS + 0.5 LSB +FS - 1.5 LSB INPUT VOLTAGE (LSB) +FS Figure 6. Bipolar Transfer Function Selecting Unipolar or Bipolar Mode (MAX1391 Only) Drive UNI/BIP high to select unipolar mode or pull UNI/BIP low to select bipolar mode. UNI/BIP can be connected to VDD for logic-high, to GND for logic-low, or actively driven. UNI/BIP needs to be stable for tUBS prior to the first rising edge of SCLK after the CS falling edge (see Figure 1) for a valid conversion result when being actively driven. Selecting Analog Input AIN1 or AIN2 (MAX1394 Only) Pull CH1/CH2 low to select AIN1 or drive CH1/CH2 high to select AIN2 for conversion. CH1/CH2 can be connected to VDD for logic-high, to GND for logic-low, or actively driven. CH1/CH2 needs to be stable for tCHS prior to the first rising edge of SCLK after the CS falling edge (see Figure 1) for a valid conversion result when being actively driven. ______________________________________________________________________________________ 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs External Reference The MAX1391/MAX1394 use an external reference between 0.6V and (VDD + 50mV). Bypass REF with a I/O OE CS SCK SCLK MAX1391 MAX1394 MISO DOUT I/O UNI/BIP (CH1/CH2)* CS OE a) SPI CS SCK SCLK MAX1391 MAX1394 MISO DOUT I/O UNI/BIP (CH1/CH2)* I/O OE b) QSPI CS SK SCLK MAX1391 MAX1394 SI I/O DOUT UNI/BIP (CH1/CH2)* 0.1µF capacitor to GND for best performance (see the Typical Operating Circuit). Serial Interface The MAX1391/MAX1394 serial interface is fully compatible with SPI, QSPI, and MICROWIRE (see Figure 7). If a serial interface is available, set the µC’s serial interface in master mode so the µC generates the serial clock. Choose a clock frequency between 100kHz and 5MHz. CS and OE can be connected together and driven simultaneously. OE can also be connected to GND if the DOUT bus is not shared and driven independently. SPI and MICROWIRE When using SPI or MICROWIRE, make the µC the bus master and set CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1. (These are the bits in the SPI or MICROWIRE control register.) Two consecutive 1-byte reads are required to get the entire 8-bit result from the ADC. The MAX1391/MAX1394 shut down after clocking out the LSB. DOUT then becomes high impedance. DOUT transitions on SCLK’s falling edge and is clocked into the µC on the SCLK’s rising edge. See Figure 7 for connections and Figures 8 and 9 for timing diagrams. The conversion result contains 4 zeros, followed by the 8 data bits with the data in MSB-first format. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the MSB of the data is clocked into the µC on the SCLK’s fifth rising edge. To be compatible with SPI and MICROWIRE, connect CS and OE together and drive simultaneously. QSPI Unlike SPI, which requires two 1-byte reads to acquire the 8 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1391/MAX1394 require a minimum of 12 clock cycles from the µC to clock out the 8 bits of data. See Figure 7 for connections and Figures 8 and 9 for timing diagrams. The conversion result contains 4 zeros, followed by the 8 data bits with the data in MSBfirst format. The MAX1391/MAX1394 shut down after clocking out the LSB. DOUT then becomes high impedance. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the MSB of the data is clocked into the µC on the SCLK’s fifth rising edge. To be compatible with QSPI, connect CS and OE together and drive simultaneously. DSP Interface c) MICROWIRE *INDICATES THE MAX1394 Figure 10 shows the timing for DSP operation. Figure 11 shows the connections between the MAX1391/ MAX1394 and several common DSPs. Figure 7. Common Serial-Interface Connections to the MAX1391/MAX1394 ______________________________________________________________________________________ 11 MAX1391/MAX1394 AutoShutdown Mode The ADC automatically powers down on the SCLK falling edge that clocks out the LSB. This is the falling edge after the 11th SCLK. DOUT goes low when the LSB has been clocked into the master (µC) on the 16th rising SCLK edge. Alternatively, drive OE high to force the MAX1391/ MAX1394 into power-down. Whenever OE goes high, the ADC powers down and disables DOUT regardless of CS, SCLK, or the state of the ADC. DOUT enters a high-impedance state after tDOD. MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs SAMPLING INSTANT ADC STATE POWER-UP AND ACQUIRE (tACQ) POWERDOWN UNI/BIP (CH1/CH2)* HOLD AND CONVERT (tCONV) POWER-DOWN UNI (AIN2)* BIPOLAR (AIN1)* CS = OE 1 2 3 4 5 6 7 8 9 10 11 12 D7 D6 D5 D4 D3 D2 D1 D0 13 14 15 16 1 SCLK DOUT HIGH-Z HIGH-Z *INDICATES THE MAX1394 Figure 8. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 1) and MICROWIRE (G6 = 0, G5 = 1) SAMPLING INSTANT ADC STATE POWER-UP AND ACQUIRE (tACQ) POWERDOWN UNI/BIP (CH1/CH2)* HOLD AND CONVERT (tCONV) POWER-DOWN UNI (AIN2)* BIPOLAR (AIN1)* CS = OE 1 2 3 4 5 6 7 8 9 10 11 12 D7 D6 D5 D4 D3 D2 D1 D0 13 14 15 16 SCLK DOUT HIGH-Z HIGH-Z *INDICATES THE MAX1394 Figure 9. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 0) and MICROWIRE (G6 = 0, G5 = 0) 12 ______________________________________________________________________________________ 1 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs MAX1391/MAX1394 SAMPLING INSTANT ADC STATE OE POWER-UP AND ACQUIRE (tACQ) POWERDOWN UNI/BIP (CH1/CH2)* HOLD AND CONVERT (tCONV) POWERDOWN UNI (AIN2)* BIPOLAR (AIN1)* FS CS 16 1 2 3 4 5 6 7 8 9 10 11 12 D7 D6 D5 D4 D3 D2 D1 D0 13 14 15 16 1 2 SCLK DOUT *INDICATES THE MAX1394 Figure 10. DSP Serial-Timing Diagram As shown in Figure 11, drive the MAX1391/MAX1394 chip-select input (CS) with the DSP’s frame-sync signal. OE may be connected to GND or driven independently. For continuous conversion operation, keep OE low and make the CS falling edge coincident with the 16th falling edge of the SCLK. Unregulated Two-Cell or Single Lithium LiMnO2 Cell Operation Low operating voltage (1.5V to 3.6V) and ultra-low-power consumption make the MAX1391/MAX1394 ideal for low cost, unregulated, battery-powered applications without the need for a DC-DC converter. Power the MAX1391/ MAX1394 directly from two alkaline/NiMH/NiCd cells in series or a single lithium coin cell as shown in the Typical Operating Circuit. Fresh alkaline cells have a voltage of approximately 1.5V per cell (3V with 2 cells in series) and approach end of life at 0.8V (1.6V with 2 cells in series). A typical 2 x AA alkaline discharge curve is shown in Figure 12a. A typical CR2032 lithium (LiMnO2) coin cell discharge curve is shown in Figure 12b. Layout, Grounding, and Bypassing For best performance, use PCBs. Board layout must ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 13 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at the MAX1391/MAX1394s’ GND pin or use the ground plane. High-frequency noise in the power supply (V DD ) degrades the ADC’s performance. Bypass VDD to GND with a 0.1µF capacitor as close to the device as possible. Minimize capacitor lead lengths for best supply noise rejection. To reduce the effects of supply noise, a 10Ω resistor can be connected as a lowpass filter to attenuate supply noise. Exposed Pad The MAX1391/MAX1394 TDFN package has an exposed pad on the bottom of the package. This pad is not internally connected. Connect the exposed pad to the GND pin on the MAX1391/MAX1394 or leave floating for proper electrical performance. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For the MAX1391/ MAX1394, this straight line is between the end points of the transfer function once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics section. ______________________________________________________________________________________ 13 I/O OE FSX CS FSR 3.0 2.8 MAX1391 SCLK MAX1394 CLKX CLKR DR DOUT I/O UNI/BIP (CH1/CH2)* 2.6 VOLTAGE (V) MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs 2.4 2.2 2.0 a) TMS320C541 CONNECTION DIAGRAM 1.8 I/O OE TFS CS RFS SCLK SCLK TA = +25°C 1.6 0 100 200 300 400 500 600 700 DAYS MAX1391 MAX1394 Figure 12a. Typical 2 x AA Discharge Curve at 100ksps DR DOUT I/O UNI/BIP (CH1/CH2)* 3.0 b) ADSP218x CONNECTION DIAGRAM 2.8 OE SC2 CS SLK SCLK SDR DOUT 2.6 MAX1391 MAX1394 VOLTAGE (V) I/O 2.4 2.2 2.0 I/O UNI/BIP (CH1/CH2)* 1.8 TA = +25°C 1.6 c) DSP563xx CONNECTION DIAGRAM *INDICATES THE MAX1394 ONLY Figure 11. Common DSP Connections to the MAX1391/MAX1394 0 10 20 30 40 50 DAYS Figure 12b. Typical CR2032 Discharge Curve at 100ksps Differential Nonlinearity (DNL) Signal-to-Noise Plus Distortion (SINAD) DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification less than ±1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1391/ MAX1394, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics section. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics (HD2–HD6), and the DC offset. RMS distortion includes the first five harmonics (HD2–HD6). 14 SIGNALRMS SINAD = 20 × log 2 2 NOISERMS + DISTORTIONRMS ______________________________________________________________________________________ 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs POWER SUPPLY VDD VDD 10Ω (OPTIONAL) Spurious-Free Dynamic Range (SFDR) GND SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). STAR GROUND POINT Intermodulation Distortion (IMD) VDD GND DVDD MAX1391/MAX1394 DATA IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: DGND DIGITAL CIRCUITRY VIM12 + VIM22 + ..... + VIM32 + VIMN2 IMD = 20 × log V12 + V22 Figure 13. Power-Supply Grounding Connections Signal-to-Noise Ratio (SNR) SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Total Harmonic Distortion (THD) THD is a dynamic figure of merit that indicates how much harmonic distortion the converter adds to the signal. THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself. This is expressed as: 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 THD = 20 × log V1 The fundamental input tone amplitudes (V1 and V2) are at -6.5dBFS. 14 intermodulation products (V IM_) are used in the MAX1391/MAX1394 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where f IN1 and fIN2 are the fundamental input tone frequencies: • 2nd-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 • 3rd-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 • 4th-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 • 5th-order intermodulation products: 3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1 Channel-to-Channel Crosstalk Channel-to-channel crosstalk indicates how well each analog input is isolated from the others. The channel-tochannel crosstalk for the MAX1394 is measured by applying DC to channel 2 while a sine wave is applied to channel 1. An FFT is taken for channels 1 and 2, and the difference (in dB) is reported as the channel-tochannel crosstalk. Aperture Delay The MAX1391/MAX1394 sample data on the falling edge of its third SCLK cycle (Figure 14). In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (tAD) is the time defined between the ______________________________________________________________________________________ 15 MAX1391/MAX1394 where V1 is the fundamental amplitude, and V2 through V6 are the amplitudes of the 2nd- through 6th-order harmonics. MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs falling edge of the sampling clock and the instant when an actual sample is taken. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay (Figure 14). THIRD FALLING EDGE SCLK DC Power-Supply Rejection Ratio (PSRR) DC PSRR is defined as the change in the positive fullscale transfer function point caused by a full range variation in the analog power-supply voltage (VDD). Chip Information TRANSISTOR COUNT: 9106 PROCESS: BiCMOS tAD ANALOG INPUT tAJ SAMPLED DATA T/H (INTERNAL SIGNAL) TRACK HOLD Figure 14. T/H Aperture Timing Typical Operating Circuit 2 x AA CELLS REF INPUT VOLTAGE INPUT VOLTAGE 0.1µF VDD REF 0.1µF OE MAX1391 MAX1394 + AIN+ (AIN1)* - AIN- (AIN2)* GND CS SCLK SCL DOUT MISO UNI/BIP (CH1/CH2)* *INDICATES THE MAX1394 16 CPU SS ______________________________________________________________________________________ 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs 6 CH1/CH2 UNI/BIP 7 OE OE 8 CS CS 9 DOUT DOUT 10 TOP VIEW SCLK SCLK TOP VIEW 10 9 8 7 6 MAX1394 AIN- AIN+ GND REF 3mm x 3mm TDFN 1 2 3 4 5 REF 5 GND 4 AIN1 3 AIN2 2 VDD 1 VDD MAX1391 3mm x 3mm TDFN ______________________________________________________________________________________ 17 MAX1391/MAX1394 Pin Configurations Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS MAX1391/MAX1394 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm 21-0137 COMMON DIMENSIONS 1 2 PACKAGE VARIATIONS MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e A 0.70 0.80 T633-1 6 1.50–0.10 2.30–0.10 0.95 BSC MO229 / WEEA 0.40–0.05 1.90 REF D 2.90 3.10 T633-2 6 1.50–0.10 2.30–0.10 0.95 BSC MO229 / WEEA 0.40–0.05 1.90 REF E 2.90 3.10 T833-1 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF A1 0.00 0.05 T833-2 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF L 0.20 0.40 T833-3 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF SYMBOL H k 0.25 MIN. T1033-1 10 1.50–0.10 2.30–0.10 0.50 BSC MO229 / WEED-3 0.25–0.05 2.00 REF A2 0.20 REF. T1033-2 10 1.50–0.10 2.30–0.10 0.50 BSC MO229 / WEED-3 0.25–0.05 2.00 REF T1433-1 14 1.70–0.10 2.30–0.10 0.40 BSC ---- 0.20–0.05 2.40 REF T1433-2 14 1.70–0.10 2.30–0.10 0.40 BSC ---- 0.20–0.05 2.40 REF PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 H 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.