19-3709; Rev 0; 5/05 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs The MAX1392/MAX1395 micropower, serial-output, 10-bit, analog-to-digital converters (ADCs) operate with a single power supply from +1.5V to +3.6V. These ADCs feature automatic shutdown, fast wake-up, and a high-speed 3-wire interface. Power consumption is only 0.740mW (VDD = +1.5V) at the maximum conversion rate of 357ksps. AutoShutdown™ between conversions reduces power consumption at slower throughput rates. The MAX1392/MAX1395 require an external reference V REF that has a wide range from 0.6V to V DD . The MAX1392 provides one true-differential analog input that accepts signals ranging from 0 to VREF (unipolar mode) or ±VREF/2 (bipolar mode). The MAX1395 provides two single-ended inputs that accept signals ranging from 0 to V REF . Analog conversion results are available through a 5MHz, 3-wire SPI™-/QSPI™/MICROWIRE™-/digital signal processor (DSP)-compatible serial interface. Excellent dynamic performance, low voltage, low power, ease of use, and small package sizes make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low power consumption and minimal space. The MAX1392/MAX1395 are available in a space-saving (3mm x 3mm) 10-pin TDFN package or 10-pin µMAX® package. The parts operate over the extended (-40°C to +85°C) and military (-55°C to +125°C) temperature ranges. Applications Portable Datalogging Data Acquisition Features ♦ 357ksps 10-Bit Successive-Approximation Register (SAR) ADCs ♦ Single True-Differential Analog Input Channel with Unipolar-/Bipolar-Selected Input (MAX1392) ♦ Dual Single-Ended Input Channel with ChannelSelected Input (MAX1395) ♦ ±0.5 LSB INL, ±0.5 LSB DNL, No Missing Codes ♦ ±1 LSB Total Unadjusted Error ♦ 61dB SINAD at 85kHz Input Frequency ♦ Single Supply Voltage (+1.5V to +3.6V) ♦ 0.945mW at 350ksps, 1.8V ♦ 0.27mW at 100ksps, 1.8V ♦ 3.1µW at 1ksps, 1.8V ♦ <1µA Shutdown Current ♦ External Reference (0.6V to VDD) ♦ AutoShutdown Between Conversions ♦ SPI-/QSPI-/MICROWIRE-/DSP-Compatible, 3- or 4-Wire Serial Interface ♦ Small (3mm x 3mm), 10-Pin TDFN or µMAX (3mm x 5mm) Package Typical Operating Circuit and Pin Configurations appear at end of data sheet. AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. µMAX is a registered trademark of Maxim Integrated Products, Inc. Medical Instruments Battery-Powered Instruments Process Control Ordering Information PART TEMP RANGE PIN-PACKAGE ANALOG INPUTS TOP MARK 1-CH DIFF AOY MAX1392ETB** -40°C to +85°C 10 TDFN-EP* MAX1392EUB** -40°C to +85°C 10 µMAX 1-CH DIFF — MAX1392MTB** -55°C to +125°C 10 TDFN-EP* 1-CH DIFF — MAX1392MUB** -55°C to +125°C 10 µMAX 1-CH DIFF — APB MAX1395ETB -40°C to +85°C 10 TDFN-EP* 2-CH S/E MAX1395EUB** -40°C to +85°C 10 µMAX 2-CH S/E — MAX1395MTB** -55°C to +125°C 10 TDFN-EP* 2-CH S/E — MAX1395MUB** -55°C to +125°C 10 µMAX 2-CH S/E — *EP = Exposed pad. **Future product—contact factory for availability. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1392/MAX1395 General Description MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +4V SCLK, CS, OE, CH1/CH2, UNI/BIP, DOUT to GND.........................................-0.3V to (VDD + 0.3V) AIN+, AIN-, AIN1, AIN2, REF to GND ........-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 10-Pin TDFN (derate 18.5mW/°C above +70°C) ....1481.5mW 10-Pin µMAX (derate 5.6mW/°C above +70°C) ........444.4mW Operating Temperature Ranges MAX139_E_ _...................................................-40°C to +85°C MAX139_M_ _ ................................................-55°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.5 LSB ±0.5 LSB 0.25 ±0.5 LSB 0.25 ±0.5 LSB ±1 LSB DC ACCURACY (Note 1) Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL No missing code overtemperature Offset Error Gain Error Offset nulled Total Unadjusted Error Bits TUE Offset-Error Temperature Coefficient ±0.001 LSB/°C Gain-Error Temperature Coefficient ±0.00025 LSB/°C Channel-to-Channel Offset Matching MAX1395 only ±0.1 LSB Channel-to-Channel Gain Matching MAX1395 only ±0.1 LSB VCM = 0 to VDD, MAX1392 only ±0.1 mV/V Input Common-Mode Rejection CMR DYNAMIC SPECIFICATIONS (Note 2) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio SINAD VREF = VDD = 1.6 to 3.6V 61 dB SNR VREF = VDD = 1.6 to 3.6V 61 dB Total Harmonic Distortion THD -83 -73 dBc Spurious-Free Dynamic Range SFDR -84 -74 dBc fIN1 = 83kHz at -6.5dBFS, fIN2 = 87kHz at -6.5dBFS -75 Channel-to-Channel Crosstalk MAX1395 only -70 dB Full-Power Bandwidth -3dB point 4 MHz Full-Linear Bandwidth SINAD > 59dB Intermodulation Distortion 2 IMD MAX1392 200 MAX1395 150 _______________________________________________________________________________________ dB kHz 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Conversion Time tCONV 11 clock cycles 2.2 µs 14 clocks per conversion; includes powerup, acquisition, and conversion time Throughput Rate Power-Up and Acquisition Time tACQ Three SCLK cycles 357 600 ksps ns Aperture Delay tAD 8 ns Aperture Jitter tAJ 30 ps Serial Clock Frequency fCLK 0.1 5.0 MHz ANALOG INPUTS (AIN+, AIN-, AIN1, AIN2) Input Voltage Range VIN Common-Mode Input Voltage Range VCM Unipolar Bipolar, MAX1392 only (AIN+ - AIN-) Bipolar, MAX1392 only [(AIN+) + (AIN-)] / 2 0 VREF -VREF/2 +VREF/2 0 VDD V ±1 µA Channel not selected, or conversion stopped, or in shutdown mode Input Leakage Current Input Capacitance 16 V pF REFERENCE INPUT (REF) REF Input Voltage Range VREF VDD + 0.05 V 0.025 ±2.5 µA 20 60 µA 0.3 x VDD V 0.6 REF Input Capacitance 24 REF DC Leakage Current REF Input Dynamic Current 357ksps pF DIGITAL INPUTS (SCLK, CS, OE, CH1/CH2, UNI/BIP) Input-Voltage Low VIL Input-Voltage High VIH 0.7 x VDD V 0.06 x VDD Input Hysteresis Input Leakage Current Input Capacitance IIL CIN Inputs at GND or VDD V ±1 CS, OE 1 CH1/CH2, UNI/BIP µA pF 12.5 DIGITAL OUTPUT (DOUT) Output-Voltage Low VOL ISINK = 2mA Output-Voltage High VOH ISOURCE = 2mA 0.1 x VDD 0.9 x VDD V V _______________________________________________________________________________________ 3 MAX1392/MAX1395 ELECTRICAL CHARACTERISTICS (continued) MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Tri-State Output Capacitance CONDITIONS ILT OE = VDD COUT OE = VDD Tri-State Leakage Current MIN TYP MAX UNITS ±1 µA 10 pF POWER SUPPLY Positive Supply Voltage VDD 1.5 fSAMPLE = 100ksps Positive Supply Current (Note 3) Power-Supply Rejection (Note 6) IDD PSR fSAMPLE = 357ksps 3.6 VDD = 1.6V 150 140 VDD = 3V 200 225 VDD = 1.6V 520 600 VDD = 3V 710 800 Power-down mode (Note 4) 5 10 Power-down mode (Note 5) 0.2 ±2.5 ±150 ±1000 VDD = 1.5V to 3.6V, full-scale input V µA µV/V TIMING CHARACTERISTICS (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX tCP 200 SCLK Pulse-Width High tCH 90 ns SCLK Pulse-Width Low tCL 90 ns CS Fall to SCLK Rise Setup tCSS 80 ns SCLK Rise to CS Fall Ignore tCSO 0 ns tDOV 80 ns OE Rise to DOUT Disable tDOD 6 20 ns OE Fall to DOUT Enable tDOE 9 20 ns CS Pulse-Width High or Low tCSW 80 ns OE Pulse-Width High or Low tOEW 80 ns CH1/CH2 Setup Time (to the First SCLK) tCHS MAX1395 only 10 ns CH1/CH2 Hold Time (to the First SCLK) tCHH MAX1395 only 0 ns UNI/BIP Setup Time (to the First SCLK) tUBS MAX1392 only 10 ns UNI/BIP Hold Time (to the First SCLK) tUBH MAX1392 only 0 ns 4 10 ns SCLK Fall to DOUT Valid Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: CLOAD = 0 to 30pF 10000 UNITS SCLK Clock Period VDD = 1.5V, VREF = 1.5V, and VAIN = 1.5V. VDD = 1.5V, VREF = 1.5V, VAIN = 1.5VP-P, fSCLK = 5MHz, fSAMPLE = 357ksps, and fIN (sine-wave) = 85kHz. All digital inputs swing between VDD and GND. VREF = VDD, fIN = 85kHz sine-wave, VAIN = VREFP-P, CLOAD = 30pF on DOUT. CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is active. CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is inactive. Change in VAIN at code boundary 1022.5. _______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 UNI/BIP OR CH1/CH2 tCHS tUBS OE tCHH tUBH tOEW CS tCSO tCH tCL tCSS tCSW SCLK tCP tDOE tDOV DOUT tDOD HIGH-Z HIGH-Z Figure 1. Detailed Serial-Interface Timing Diagram VDD 10mA DOUT 10mA DOUT 50pF 50pF GND GND a) HIGH IMPEDANCE TO VOH, VOL TO VOH, AND VOH TO HIGH IMPEDANCE b) HIGH IMPEDANCE TO VOL, VOH TO VOL, AND VOL TO HIGH IMPEDANCE Figure 2. Load Circuits for Enable/Disable Times _______________________________________________________________________________________ 5 Typical Operating Characteristics (VDD = +1.5V, VREF = +1.5V, CREF = 0.1µF, CL = 30pF, fSCLK = 5MHz. TA = +25°C, unless otherwise noted.) INL ERROR vs. REFERENCE VOLTAGE 0.2 0 -0.2 0.4 0 -0.2 MIN INL 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 -1.0 128 256 384 512 640 768 896 1024 -0.6 0.6 DNL ERROR vs. REFERENCE VOLTAGE 1.1 2.1 2.6 3.1 3.6 0 0.2 0 -0.2 MIN DNL -0.6 -0.8 -1.0 MAX1392/95 toc05 VREF = 1.5V TEMPERATURE = +25°C 300 AIN2 200 OFFSET ERROR vs. TEMPERATURE 100 0 -100 400 VDD = 3.6V 300 OFFSET ERROR (µV) MAX DNL AIN1 2.1 2.6 3.1 -300 3.6 OFFSET ERROR vs. REFERENCE VOLTAGE 1.8 3.3 -55 3.6 100 0 -100 VREF = 1.5V TEMPERATURE = +25°C 300 AIN2 200 0 AIN1 0 -300 -400 2.6 REFERENCE VOLTAGE (V) 3.1 3.6 AIN2 -100 -300 2.1 125 100 -300 1.6 95 200 -200 1.1 65 VDD = 3.6V 300 -200 0.6 35 400 -200 -400 5 GAIN ERROR vs. TEMPERATURE 100 -100 -25 TEMPERATURE (°C) GAIN ERROR vs. SUPPLY VOLTAGE GAIN ERROR (µV) 200 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 400 MAX1392/95 toc07 VDD = 3.6V 300 AIN1 -400 1.5 REFERENCE VOLTAGE (V) 400 0 -100 -300 GAIN ERROR (µV) 1.6 100 -200 MAX1392/95 toc08 1.1 AIN2 200 -200 -400 0.6 128 256 384 512 640 768 896 1024 CODE OFFSET ERROR vs. SUPPLY VOLTAGE OFFSET ERROR (µV) 0.6 -0.4 1.6 400 MAX1392/95 toc04 VDD = 3.6V 0.4 -0.4 REFERENCE VOLTAGE (V) 1.0 0.8 MAX1392/95 toc03 0.4 MAX INL 0.2 CODE DNL ERROR (LSB) 0.6 -0.4 0 6 0.8 MAX1392/95 toc06 INL ERROR (LSB) 0.4 0.6 DNL (LSB) 0.6 VDD = 3.6V 0.8 DNL vs. CODE 1.0 MAX1392/95 toc02 MAX1392/95 toc01 0.8 INL (LSB) 1.0 MAX1392/95 toc09 INL vs. CODE 1.0 OFFSET ERROR (µV) MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs AIN1 -400 1.5 1.8 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 -55 -25 5 35 65 TEMPERATURE (°C) _______________________________________________________________________________________ 95 125 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs 100 0 -100 -200 700 600 1.6 2.1 2.6 3.1 3.6 1.5 1.8 2.1 2.4 2.7 3.0 3.3 -55 3.6 65 95 SUPPLY CURRENT vs. CONVERSION RATE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 200 VDD = VREF = 1.6V 0.3 0.2 0.1 0 150 200 250 300 350 1.6 1.2 0.8 VDD = 1.8V VDD = 3.6V 0.4 0 0 100 MAX1392/95 toc15 MAX1392/95 toc14 0.4 1.5 1.8 2.1 2.4 2.7 3.0 3.3 -55 3.6 -25 5 35 65 95 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SCLK-TO-DOUT TIMING FFT SAMPLING ERROR vs. SOURCE IMPEDANCE 60 MAGNITUDE (dB) 70 VDD = 3.6V 50 -20 40 30 20 -40 -60 -80 1.0 0.8 0.4 0.2 0 -0.2 -0.4 -100 -0.6 -120 -1.0 10 AIN HIGH-TO-LOW FS TRANSITION 0.6 125 MAX1392/95 toc18 VDD = 1.5V VDD = 1.6V VREF = 1.6V fS = 357ksps fIN = 85kHz THD = -82.7dB SINAD = 61.3dB SFDR = -83.8dB SAMPLING ERROR (LSB) 0 MAX1392/95 toc16 90 MAX1392/95 toc17 fSAMPLE (ksps) 100 125 2.0 SHUTDOWN SUPPLY CURRENT (µA) 400 0.5 SHUTDOWN CURRENT (µA) VDD = VREF = 3.0V 80 35 TEMPERATURE (°C) 600 50 5 SUPPLY VOLTAGE (V) fSCLK = 5MHz, fSAMPLE = 357ksps AIN = FULL SCALE, 85kHz SINE WAVE CL = 30pF 0 -25 REFERENCE VOLTAGE (V) MAX1392/95 toc13 SUPPLY CURRENT (µA) 800 1.1 500 400 400 0.6 550 VREF = 1.5V, CL = 33pF fSCLK = 5MHz, fSAMPLE = 357ksps AIN = FULL SCALE, 10kHz SINE WAVE -300 DOUT DELAY (ns) VREF = 1.5V, CL = 33pF fSCLK = 5MHz, fSAMPLE = 357ksps AIN = FULL SCALE, 10kHz SINE WAVE 450 500 -400 600 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) GAIN ERROR (µV) 200 MAX1392/95 toc11 VDD = 3.6V 300 SUPPLY CURRENT vs. TEMPERATURE 800 MAX1392/95 toc10 400 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1392/95 toc12 GAIN ERROR vs. REFERENCE VOLTAGE AIN LOW-TO-HIGH FS TRANSITION -0.8 0 0 100 200 300 CLOAD (pF) 400 500 600 0 20 40 60 80 100 120 140 160 180 FREQUENCY (kHz) 0 500 1000 1500 2000 2500 SOURCE IMPEDENCE (Ω) _______________________________________________________________________________________ 7 MAX1392/MAX1395 Typical Operating Characteristics (continued) (VDD = +1.5V, VREF = +1.5V, CREF = 0.1µF, CL = 30pF, fSCLK = 5MHz. TA = +25°C, unless otherwise noted.) MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs Pin Description PIN MAX1392 MAX1395 1 1 NAME FUNCTION VDD Positive Supply Voltage. Connect VDD to a 1.5V to 3.6V power supply. Bypass VDD to GND with a 0.1µF capacitor as close to the device as possible. 2 — AIN- Negative Analog Input — 2 AIN2 Analog Input Channel 2 3 — AIN+ Positive Analog Input — 3 AIN1 Analog Input Channel 1 4 4 GND Ground 5 5 REF External Reference Voltage Input. VREF = 0.6V to (VDD + 0.05V). Bypass REF to GND with a 0.1µF capacitor as close to the device as possible. 6 — UNI/BIP Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to select bipolar input mode. In unipolar mode, the output data is in straight binary format. In bipolar mode, the output data is in two’s-complement format. — 6 CH1/CH2 Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select channel 2. 7 7 OE Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT. Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface with DSP devices. 8 8 CS Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition. 9 9 DOUT Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high impedance when OE is high. 10 10 SCLK Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 13th falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10). — — EP Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave floating. VDD Detailed Description The MAX1392/MAX1395 use an input track and hold (T/H) circuit along with a SAR to convert an analog input signal to a serial 10-bit digital output data stream. The serial interface provides easy interfacing to microprocessors and DSPs. Figure 3 shows the simplified functional diagram for the MAX1392 (1 channel, true differential) and the MAX1395 (2 channels, single ended). True-Differential Analog Input T/H The equivalent input circuit of Figure 4 shows the MAX1392/MAX1395 input architecture, which is composed of a T/H, a comparator, and a switched-capacitor DAC. The T/H enters its tracking mode on the falling edge of CS (while OE is held low). The positive input capacitor is connected to AIN+ (MAX1392), or to AIN1 or AIN2 (MAX1395). The negative input capacitor is connected to AIN- (MAX1392) or GND (MAX1395). The T/H enters its hold mode on the 3rd falling edge of SCLK 8 CONTROL LOGIC AND TIMING AIN+ (AIN1)* AIN- (AIN2)* INPUT MUX AND T/H OUTPUT SHIFT REGISTER 10-BIT SAR ADC REF SCLK OE DOUT UNI/BIP (CH1/CH2)* MAX1392 MAX1395 *INDICATES THE MAX1395 CS GND Figure 3. Simplified Functional Diagram _______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs Note: tACQ is never less than 600ns and any source impedance below 400Ω does not significantly affect the ADC’s AC performance. REF GND RSOURCE DAC AIN2 AIN1 (AIN+)* ANALOG SIGNAL SOURCE CIN+ MAX1392 MAX1395 COMPARATOR + HOLD CIN- GND- (AIN-)* RIN- RIN+ HOLD VDD/2 *INDICATES THE MAX1392 Figure 4. Equivalent Input Circuit HOLD Analog Input Bandwidth The ADC’s input-tracking circuitry has a 4MHz fullpower bandwidth, making it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Analog Input Range and Protection The MAX1392/MAX1395 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within their specified range. When operating the MAX1392 in unipolar mode (UNI/BIP = 1), the specified differential analog input range is from 0 to VREF. When operating in bipolar mode (UNI/BIP = 0), the differential analog input range is from -VREF/2 to +VREF/2 with a common mode range of 0 to VDD. The MAX1395 has an input range from 0 to VREF. Internal protection diodes confine the analog input voltage within the region of the analog power input rails (VDD, GND) and allow the analog input voltage to swing from GND - 0.3V to VDD + 0.3V without damage. Input voltages beyond GND - 0.3V and VDD + 0.3V forward bias the internal protection diodes. In this situation, limit the forward diode current to less than 50mA to avoid damage to the MAX1392/MAX1395. Output Data Format Figures 8, 9, and 10 illustrate the conversion timing for the MAX1392/MAX1395. Fourteen SCLK cycles are required to read the conversion result and data on DOUT transitions on the falling edge of SCLK. The conversion result contains 4 zeros, followed by 10 data bits with the data in MSB-first format. For the MAX1392, data is straight binary for unipolar mode and two’s complement for bipolar mode. For the MAX1395, data is always straight binary. TRACK Transfer Function Figure 5 shows the unipolar transfer function for the MAX1392/MAX1395. Figure 6 shows the bipolar transfer function for the MAX1392. Code transitions occur halfway between successive-integer LSB values. _______________________________________________________________________________________ 9 MAX1392/MAX1395 and the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. The required acquisition time lengthens as the input signal’s source impedance increases. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ ≥ 7.4 x (RSOURCE + RIN) x CIN + tPU where: RSOURCE is the source impedance of the input signal. RIN = 500Ω, which is the equivalent differential analog input resistance. CIN = 16pF, which is the equivalent differential analog input capacitance. tPU = 400ns. FULL-SCALE TRANSITION FS = VREF 3FF 1FF ZS = 0 3FE 1 LSB = VREF 1024 1FE +FS = VREF 2 ZS = 0 FULL-SCALE TRANSITION -VREF 2 V 1 LSB = REF 1024 -FS = OUTPUT CODE (hex) 3FD OUTPUT CODE (hex) MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs 3FC 3FB 004 001 000 3FF 3FE 003 002 201 001 200 000 0 1 2 3 4 FS - 1.5 LSB INPUT VOLTAGE (LSB) FS Figure 5. Unipolar Transfer Function Applications Information Starting a Conversion A falling edge on CS initiates the power-up sequence and begins acquiring the analog input as long as OE is also asserted low. On the 3rd SCLK falling edge, the analog input is held for conversion. The most significant bit (MSB) decision is made and clocked onto DOUT on the 4th SCLK falling edge. Valid DOUT data is available to be clocked into the master (microcontroller (µC)) on the following SCLK rising edge. The rest of the bits are decided and clocked out to DOUT on each successive SCLK falling edge. See Figures 8 and 9 for conversion timing diagrams. Once a conversion has been initiated, CS can go high at any time. Further falling edges of CS do not reinitiate an acquisition cycle until the current conversion completes. Once a conversion completes, the first falling edge of CS begins another acquisition/conversion cycle. 10 -FS 0 -FS + 0.5 LSB +FS - 1.5 LSB INPUT VOLTAGE (LSB) +FS Figure 6. Bipolar Transfer Function Selecting Unipolar or Bipolar Mode (MAX1392 Only) Drive UNI/BIP high to select unipolar mode or pull UNI/BIP low to select bipolar mode. UNI/BIP can be connected to VDD for logic high, to GND for logic low, or actively driven. UNI/BIP needs to be stable for tUBS prior to the first rising edge of SCLK after the CS falling edge (see Figure 1) for a valid conversion result when being actively driven. Selecting Analog Input AIN1 or AIN2 (MAX1395 Only) Pull CH1/CH2 low to select AIN1 or drive CH1/CH2 high to select AIN2 for conversion. CH1/CH2 can be connected to VDD for logic high, to GND for logic low, or actively driven. CH1/CH2 needs to be stable for tCHS prior to the first rising edge of SCLK after the CS falling edge (see Figure 1) for a valid conversion result when being actively driven. ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs External Reference The MAX1392/MAX1395 use an external reference between 0.6V and (VDD + 50mV). Bypass REF with a I/O OE CS SCK SCLK MAX1392 MAX1395 MISO DOUT I/O UNI/BIP (CH1/CH2)* CS OE a) SPI CS SCK SCLK MAX1392 MAX1395 MISO DOUT I/O UNI/BIP (CH1/CH2)* I/O OE b) QSPI CS SK SCLK MAX1392 MAX1395 SI I/O DOUT UNI/BIP (CH1/CH2)* 0.1µF capacitor to GND for best performance (see the Typical Operating Circuit). Serial Interface The MAX1392/MAX1395 serial interface is fully compatible with SPI, QSPI, and MICROWIRE (see Figure 7). If a serial interface is available, set the µC’s serial interface in master mode so the µC generates the serial clock. Choose a clock frequency between 100kHz and 5MHz. CS and OE can be connected together and driven simultaneously. OE can also be connected to GND if the DOUT bus is not shared and driven independently. SPI and MICROWIRE When using SPI or MICROWIRE, make the µC the bus master and set CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1. (These are the bits in the SPI or MICROWIRE control register.) Two consecutive 1-byte reads are required to get the entire 10-bit result from the ADC. The MAX1392/MAX1395 shut down after clocking the LSB and DOUT becomes high impedance. DOUT transitions on SCLK’s falling edge and is clocked into the µC on the SCLK’s rising edge. See Figure 7 for connections and Figures 8 and 9 for timing diagrams. The conversion result contains 4 zeros, followed by the 10 data bits with the data in MSB-first format. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the MSB of the data is clocked into the µC on the SCLK’s fifth rising edge. To be compatible with SPI and MICROWIRE, connect CS and OE together and drive simultaneously. QSPI Unlike SPI, which requires two 1-byte reads to acquire the 10 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1392/MAX1395 require a minimum of 14 clock cycles from the µC to clock out the 10 bits of data. See Figure 7 for connections and Figures 8 and 9 for timing diagrams. The conversion result contains 4 zeros, followed by the 10 data bits with the data in MSB-first format. The MAX1392/MAX1395 shut down after clocking out the LSB. DOUT then becomes high impedance. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the MSB of the data is clocked into the µC on the SCLK’s fifth rising edge. To be compatible with QSPI, connect CS and OE together and drive simultaneously. DSP Interface c) MICROWIRE *INDICATES THE MAX1395 Figure 10 shows the timing for DSP operation. Figure 11 shows the connections between the MAX1392/ MAX1395 and several common DSPs. Figure 7. Common Serial-Interface Connections to the MAX1392/MAX1395 ______________________________________________________________________________________ 11 MAX1392/MAX1395 AutoShutdown Mode The ADC automatically powers down on the SCLK falling edge that clocks out the LSB. This is the falling edge after the 13th SCLK. DOUT goes low when the LSB has been clocked into the master (µC) on the 16th rising SCLK edge. Alternatively, drive OE high to force the MAX1392/ MAX1395 into power-down. Whenever OE goes high, the ADC powers down and disables DOUT regardless of CS, SCLK, or the state of the ADC. DOUT enters a high-impedance state after tDOD. MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs SAMPLING INSTANT ADC STATE HOLD AND CONVERT (tCONV) POWER-UP AND ACQUIRE (tACQ) POWERDOWN UNI/BIP (CH1/CH2)* POWER-DOWN UNI (AIN2)* BIPOLAR (AIN1)* CS = OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 15 16 1 SCLK DOUT HIGH-Z HIGH-Z *INDICATES THE MAX1395 Figure 8. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 1) and MICROWIRE (G6 = 0, G5 = 1) SAMPLING INSTANT ADC STATE HOLD AND CONVERT (tCONV) POWER-UP AND ACQUIRE (tACQ) POWERDOWN UNI/BIP (CH1/CH2)* POWER-DOWN UNI (AIN2)* BIPOLAR (AIN1)* CS = OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 15 16 SCLK DOUT HIGH-Z HIGH-Z *INDICATES THE MAX1395 Figure 9. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 0) and MICROWIRE (G6 = 0, G5 = 0) 12 ______________________________________________________________________________________ 1 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 SAMPLING INSTANT ADC STATE OE HOLD AND CONVERT (tCONV) POWER-UP AND ACQUIRE (tACQ) POWERDOWN UNI/BIP (CH1/CH2)* POWERDOWN UNI (AIN2)* BIPOLAR (AIN1)* FS CS 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 15 16 1 2 SCLK DOUT *INDICATES THE MAX1395 Figure 10. DSP Serial-Timing Diagram As shown in Figure 11, drive the MAX1392/MAX1395 chip-select input (CS) with the DSP’s frame-sync signal. OE may be connected to GND or driven independently. For continuous conversion operation, keep OE low and make the CS falling edge coincident with the 14th falling edge of the SCLK. Fourteen-bit data transfers can also be performed with compatible DSPs. Unregulated Two-Cell or Single Lithium LiMnO2 Cell Operation Low operating voltage (1.5V to 3.6V) and ultra-low-power consumption make the MAX1392/MAX1395 ideal for low cost, unregulated, battery-powered applications without the need for a DC-DC converter. Power the MAX1392/ MAX1395 directly from two alkaline/NiMH/NiCd cells in series or a single lithium coin cell as shown in the Typical Operating Circuit. Fresh alkaline cells have a voltage of approximately 1.5V per cell (3V with 2 cells in series) and approach end of life at 0.8V (1.6V with 2 cells in series). A typical 2xAA alkaline discharge curve is shown in Figure 12a. A typical CR2032 lithium (LiMnO2) coin cell discharge curve is shown in Figure 12b. Layout, Grounding, and Bypassing For best performance, use PC boards. Board layout must ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 13 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at the MAX1392/MAX1395s’ GND pin or use the ground plane. High-frequency noise in the power supply (V DD ) degrades the ADC’s performance. Bypass VDD to GND with a 0.1µF capacitor as close to the device as possible. Minimize capacitor lead lengths for best supply noise rejection. To reduce the effects of supply noise, a 10Ω resistor can be connected as a lowpass filter to attenuate supply noise. Exposed Pad The MAX1392/MAX1395 TDFN package has an exposed pad on the bottom of the package. This pad is not internally connected. Connect the exposed pad to the GND pin on the MAX1392/MAX1395 or leave floating for proper electrical performance. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For the MAX1392/ MAX1395, this straight line is between the end points of the transfer function once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics section. ______________________________________________________________________________________ 13 I/O OE FSX CS 2.8 FSR CLKX 3.0 SCLK MAX1392 MAX1395 CLKR DR DOUT I/O UNI/BIP (CH1/CH2)* 2.6 VOLTAGE (V) MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs 2.4 2.2 2.0 a) TMS320C541 CONNECTION DIAGRAM 1.8 I/O OE TFS CS RFS SCLK TA = +25°C 1.6 0 100 200 300 400 500 600 700 DAYS MAX1392 SCLK MAX1395 Figure 12a. Typical 2xAA Discharge Curve at 100ksps DR DOUT I/O UNI/BIP (CH1/CH2)* 3.0 b) ADSP218x CONNECTION DIAGRAM 2.8 OE SC2 CS SLK SCLK SDR DOUT 2.6 MAX1392 MAX1395 VOLTAGE (V) I/O 2.4 2.2 2.0 I/O UNI/BIP (CH1/CH2)* 1.8 TA = +25°C 1.6 c) DSP563xx CONNECTION DIAGRAM *INDICATES THE MAX1395 Figure 11. Common DSP Connections to the MAX1392/MAX1395 0 10 20 30 40 50 DAYS Figure 12b. Typical CR2032 Discharge Curve at 100ksps Differential Nonlinearity (DNL) Signal-to-Noise Plus Distortion (SINAD) DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1392/ MAX1395, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics section. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics (HD2–HD5), and the DC offset. RMS distortion includes the first five harmonics (HD2–HD5). 14 SIGNALRMS SINAD = 20 × log 2 2 NOISERMS + DISTORTIONRMS ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs POWER SUPPLY Spurious-Free Dynamic Range (SFDR) VDD VDD 10Ω (OPTIONAL) GND SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). STAR GROUND POINT Intermodulation Distortion (IMD) VDD GND DVDD MAX1392/MAX1395 DATA IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: DGND DIGITAL CIRCUITRY VIM12 + VIM22 + ..... + VIM32 + VIMN2 IMD = 20 × log V12 + V22 Figure 13. Power-Supply Grounding Connections Signal-to-Noise Ratio (SNR) SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Total Harmonic Distortion (THD) THD is a dynamic figure of merit that indicates how much harmonic distortion the converter adds to the signal. THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself. This is expressed as: 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 THD = 20 × log V1 The fundamental input tone amplitudes (V1 and V2) are at -6.5dBFS. Fourteen intermodulation products (VIM_) are used in the MAX1392/MAX1395 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where fIN1 and fIN2 are the fundamental input tone frequencies: • 2nd-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 • 3rd-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 • 4th-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 • 5th-order intermodulation products: 3 x f IN1 - 2 x f IN2 , 3 x f IN2 - 2 x f IN1 , 3 x f IN1 + 2 x f IN2 , 3 x f IN2 + 2 x fIN1 Channel-to-Channel Crosstalk Channel-to-channel crosstalk indicates how well each analog input is isolated from the others. The channel-tochannel crosstalk for the MAX1395 is measured by applying DC to channel 2 while an AC sine wave is applied to channel 1. An FFT is taken for channel 1 and channel 2 and the difference (in dB) is reported as the channel-to-channel crosstalk. ______________________________________________________________________________________ 15 MAX1392/MAX1395 where V1 is the fundamental amplitude, and V2 through V6 are the amplitudes of the 2nd- through 6th-order harmonics. MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs Aperture Delay The MAX1392/MAX1395 sample data on the falling edge of its third SCLK cycle (Figure 14). In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay (Figure 14). DC Power-Supply Rejection Ratio (PSRR) DC PSRR is defined as the change in the positive fullscale transfer function point caused by a full range variation in the analog power-supply voltage (VDD). THIRD FALLING EDGE SCLK tAD ANALOG INPUT tAJ SAMPLED DATA T/H (INTERNAL SIGNAL) TRACK HOLD Figure 14. T/H Aperture Timing Chip Information Typical Operating Circuit TRANSISTOR COUNT: 9106 PROCESS: BiCMOS 2 x AA CELLS REF INPUT VOLTAGE INPUT VOLTAGE 0.1µF VDD REF OE CS + MAX1392 MAX1395 AIN+ (AIN1)* SCLK SCL - AIN- (AIN2)* DOUT MISO 0.1µF GND UNI/BIP (CH1/CH2)* *INDICATES THE MAX1395 ONLY 16 ______________________________________________________________________________________ CPU SS 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs SCLK DOUT CS OE UNI/BIP TOP VIEW 10 9 8 7 6 TOP VIEW VDD 1 10 SCLK AIN- 2 AIN+ 3 1 2 3 4 5 VDD AIN- AIN+ GND REF MAX1392 9 DOUT MAX1392 8 CS GND 4 7 OE REF 5 6 UNI/BIP µMAX DOUT CS OE CH1/CH2 TOP VIEW SCLK 3mm x 3mm TDFN 10 9 8 7 6 TOP VIEW VDD 1 10 SCLK AIN2 2 AIN1 3 1 2 3 4 5 VDD AIN2 AIN1 GND REF MAX1395 9 DOUT MAX1395 8 CS GND 4 7 OE REF 5 6 CH1/CH2 µMAX 3mm x 3mm TDFN ______________________________________________________________________________________ 17 MAX1392/MAX1395 Pin Configurations Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS MAX1392/MAX1395 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs D2 D A2 PIN 1 ID N 0.35x0.35 b PIN 1 INDEX AREA E [(N/2)-1] x e REF. E2 DETAIL A e k A1 CL CL A L L e e PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 G 1 2 COMMON DIMENSIONS MIN. MAX. D 0.70 2.90 0.80 3.10 E A1 2.90 0.00 3.10 0.05 L k 0.20 0.40 0.25 MIN. A2 0.20 REF. SYMBOL A PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e DOWNBONDS ALLOWED T633-1 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF NO T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF NO T833-1 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF NO T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF NO T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF YES T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF NO T1433-1 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF YES T1433-2 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF NO PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 18 21-0137 G 2 2 ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs 10LUMAX.EPS e 4X S 10 10 INCHES H Ø0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0° 6° MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0° 6° E2 GAGE PLANE A2 c A b A1 α E1 L D1 L1 FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 REV. I 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX1392/MAX1395 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)