TOSHIBA T6B70BFG

T6B70BFG
TOSHIBA CMOS Digital Integrated
Circuit
Silicon Monolithic
T6B70BFG
Interface IC for Hot Water Dispensers
The T6B70BFG is designed to be used mainly as an interface IC
for communication between hot water dispensers and the
corresponding controller unit, and comes equipped with a two
channel 4-bit D/A converter, pseudo sine wave generator and an
external analog signal detection circuit.
Features
•
Built-in two channel 4-bit D/A converter (opposite polarities)
•
Built-in pseudo sine wave generator
(external clock 1/16 frequency divider)
•
Built-in external analog signal detection/non-detection circuit
•
Built-in two channel analog switch
Weight: 0.16 g (typ.)
Block Diagram
OSCIN 1
OSCOUT 2
16
frequency
divider unit
0°C
Pseudo
sine wave
180°C
generator
Waveform
initialization block
4-bit D/A
converter
13 SOUT+
4-bit D/A
converter
12 SOUT−
FOUT 3
/SCTL 4
16 VDD
Modulation
control
circuit
Zero crossing
waveform
shaping circuit
SW1IN 14
Amp input
circuit
7 AMPIN
SW1OUT 15
6 AMPOUT
Cycle measurement
counter
SW2IN 11
Detection/non-detection
judgment circuit
SW2OUT 10
/RESET 5
Reset
circuit
Output buffer
8 VSS
9 /DOUT
Pin Assignment Diagram
16 ■ VDD
OSCIN ■ 1
OSCOUT ■ 2
15 ■ SW1OUT
FOUT ■ 3
/SCTL ■ 4
14 ■ SW1IN
T6B70BFG
13 ■ SOUT+
/RESET ■ 5
12 ■ SOUT−
AMPOUT ■ 6
11 ■ SW2IN
AMPIN ■ 7
10 ■ SW2OUT
VSS ■ 8
9 ■ /DOUT
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Pin Functions
Pin No.
Symbol
Input/Output
Function
1
OSCIN
Input
Pins connected to oscillation
2
OSCOUT
Output
Pins connected to oscillation
3
FOUT
Output
Output pin for oscillation waveform shaping circuit
4
/SCTL
Input
Modulation control signal input pin
5
/RESET
Input
Reset signal input pin
6
AMPOUT
Output
7
AMPIN
Input
Amplifier signal input pin
8
VSS
⎯
Device ground pin (0 V)
9
/DOUT
Output
Output pin for amplifier input signal detector
10
SW2OUT
Output
Output pin on analog SW2 side
11
SW2IN
Input
12
SOUT−
Output
Pseudo sine wave (opposite polarity of SOUT + output) output pin
13
SOUT+
Output
Pseudo sine wave output pin
14
SW1IN
Input
Input pin on analog SW1 side
15
SW1OUT
Output
Output pin on analog SW1 side
16
VDD
⎯
Device power supply pin (+5 V)
Amplifier signal output pin
Input pin on analog SW2 side
The equivalent circuit diagrams provided in the above table are given to facilitate understanding in designing the
external circuitry but are not intended to accurately represent the internal circuitry.
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Functions
1. Pseudo sine wave generator and 4-bit D/A converters (transmission block)
The pseudo sine wave signal with Fosc/16 frequency is output from the pseudo sine wave output pins
(SOUT+ and SOUT−).
The output polarity of SOUT+ and SOUT− are the opposite.
The transmission block (pseudo sine wave generator and 4-bit D/A converter are as shown below (SOUT+
pin side):
SOUT+ pin
R
R
R
R
R
R
R
R
R
SOUT+
LSB
R
R
FOSC
SOUT−
2R
Pseudo sine wave generator
MSB
VSS
RST
The data of the pseudo sine wave generator is output in the following sequence:
0 → 1 → 3 → 6 → 9 → C → E → F → F → E → C → 9 → 6 → 3 → 1 → 0 (hexadecimal)
F
F
E
E
C
C
9
9
6
6
3
0
1
3
FSIN
1
0
250 kHz
@FOSC = 4 MHz
Therefore, when there is no load, the pseudo sine waveform of the positive and negative output is like a
staircase (as illustrated above).
An analog switch is built-in so that the driver output buffer connects to the transmission line only during
transmission.
However, an emitter follower circuit is externally connected to the driver output buffer.
The phase difference between the positive and negative output is within 180° ± 5° (to account for fluctuation
in the pseudo sine wave output phase).
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2. Amplifier input circuit and signal detection/non-detection circuit (reception block)
The modulation signal input block is equipped with high and a low comparator to detect only when the
external sine wave signal’s amplitude is above the defined threshold. In this way, signals with amplitudes
lower than the specified threshold (e.g., noise signals) are prevented from being mistakenly detected as sine
waves.
The detection frequency range (frequency window) is determined by the divider ratio 1/17 to 1/15 of Fosc.
Detection/non-detection confirmation conditions are such that when the signals within the specified
frequency range are detected (or not detected) in succession, the signals are controlled. It takes about 9 to 15
waves (based on Fosc 1/16 frequency) to make detection/non-detection confirmation in this manner.
VDD
VDD
APU
R1
Reference
voltage
High comparator
VA
+
VH
R2
−
7
VBIAS
Low comparator
VB
+
S
−
RESET
Q
R4
APU
R3
AMPIN pin
Reference
voltage
VL
Q
R
Detection
/non-detection
9
judgment
/DOUT pin
circuit
Cycle
measurement
counter
6
AMPOUT pin
VSS
VSS
AMP IN input sine waveform
VH
Input
sensitivity
VL V
PP
Reception detected
Reception non-detected
Reception non-detected
Reception non-detected
AMPOUT output timing (/RESET = L)
AMPOUT Truth Table
VH
VL
AMPOUT
VA
VB
AMPOUT
VBIAS > VH
L
H
L
VH > VBIAS > VL
H
H
Hold
VBIAS < VL
H
L
H
VBIAS
Held at high
Held at low
VBIAS < VL
VBIAS > VH
VH > VBIAS > VL VH > VBIAS > VL
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3. Transmission block function and timing
When the modulation control input (/SCTL) is in High-level, the pseudo sine wave output is held at 0° phase
of the pseudo sine wave. When the modulation control input changes from High-level to Low-level, the
pseudo sine wave output (SOUT+) initially outputs from -90° (SOUT− outputs from +90°).
The time required to turn ON in this case is as follows:
td (ON) < 500 ns
When modulation control input changes from Low-level to High-level, the phase is forcibly held at 0° (the
pseudo sine wave output is stopped), regardless of the phase of the pseudo sine wave output. The time
required to turn OFF in this case is as follows:
td (OFF) < 1 μs
～
～
/SCTL
td (OFF)
td (ON)
～
～
SOUT+ pseudo sine wave output
(SOUT− is the opposite polarity)
4. Reception block function and timing
Once it is okay to receive the amplifier input signal, the time it takes for the /DOUT pin to changes from
High to Low (T (DET)) is about 9 to 15 waves (based on Fosc 1/16 frequency). This condition is only valid
when the cyclic input signal within the range specified by the frequency window is detected (or not detected)
in continuation.
～
～
～
～
Amplifier input
T (DET)
T (DET)
/DOUT
～
～
Note 1: You are free to use any kind of communication protocol you wish, however be sure to configure a time of
carrier wave × 15 waves or more for both when there are and aren’t signals.
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Timing Chart (SOUT+ = SW1IN, SW1OUT, SOUT− = SW2IN, SW2OUT)
VDD
/RESET
OSCIN
(4 MHz)
FOUT
VPP
AMPIN
(250 kHz)
AMPOUT
X
Transmitting
/SCTL
td (ON)
FSIN
td (OFF)
SOUT+
VOPP
SOUT−
Receiving
/DOUT
TDET
TDET
SW1IN
SW1OUT
X
X
SW2IN
SW2OUT
X
X
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Absolute Maximum Ratings (Ta = 25 ± 1.5°C)
Characteristics
Symbol
Rating
Unit
VDD
−0.3 to 6.0
V
Input voltage
VI
−0.3 to
VDD + 0.3
V
Input peak current
IIK
−20 to 20
mA
Operating temperature
Topr
−20 to 80
°C
Storage temperature
Tstg
−55 to 125
°C
0.54
W
Power supply voltage
Power dissipation
PD (Note 1)
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
Note 1: Power dissipation decreases approximately 4.35 mW per degree (Centigrade).
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Electrical Characteristics
(unless otherwise specified, VDD = 5.0 V, VSS = 0 V, FOSC = 4 MHz and Ta = −20 to 80°C)
Symbol
Test
Circuit
Operating voltage
VDD
⎯
Current consumption
IDD
1
Characteristics
Test Condition
Min
Typ.
Max
Unit
4.5
5.0
5.5
V
⎯
⎯
10
mA
MHz
VDD pin (pin 16)
When there is no load;
FOSC = 4 MHz
OSCIN pin (pin 1) and OSCOUT pin (pin 2)
Oscillation frequency
FOSC
2
1
4
10
High level
VIHOSC
3
0.7
VDD
⎯
VDD
Low level
VILOSC
3
VSS
⎯
0.3
VDD
High level
IIHROSC
4
VIN = 5 V, Ta = 25°C
3.2
6.58
13.2
Low level
IILROSC
4
VIN = 0 V, Ta = 25°C
−3.2
−6.58
−13.2
High level
VOHOSC
3
IOH = −0.1 mA
VDD − 1
⎯
VDD
Low level
VOLOSC
4
IOL = +0.1 mA
VSS
⎯
VSS
+ 0.6
V
Low to High input switching level
VIHRST
5
0.65
VDD
⎯
VDD
V
High to Low input switching level
VILRST
5
VSS
⎯
0.35
VDD
V
High-level input current
IIHRST
6
VIN = VDD
−10
⎯
10
μA
Pull-up resistance 1
IILRRST1
7
VIN = VSS, Ta = 25°C
9
15
21
kΩ
Pull-up resistance 2
IILRRST2
7
VIN = VSS, Ta = −20 to 80°C
6.3
⎯
27.3
kΩ
Low to High input switching level
VIHSCTL
8
0.65
VDD
⎯
VDD
V
High to Low input switching level
VILSCTL
8
VSS
⎯
0.35
VDD
V
High level
IIHSCTL
9
VIN = VDD
−1
⎯
1
Low level
IILSCTL
9
VIN = VDD
−1
⎯
1
High level
VOHFOUT
10
IOH = −1.0 mA
VDD − 1
⎯
VDD
Low level
VOLFOUT
11
IOL = +1.0 mA
VSS
⎯
VSS
+ 0.6
VOHDOUT
12
IOH = −1.0 mA
VDD
− 1.0
⎯
VDD
VSS
⎯
VSS
+ 0.6
Input voltage
Input current
Output
voltage
V
μA
/RESET pin (5 pin)
/SCTL pin (pin 4)
Input current
μA
FOUT pin (pin 3)
Output
voltage
V
/DOUT pin (pin 9)
Output
voltage
High level
Low level
Non-reception to reception
detection time
Reception to non-reception
detection time
V
VOLDOUT
13
IOL = +1.0 mA
TDET1
19
FOSC = 4 MHz,
AMPIN = 250 kHz
Time it takes for /DOUT to
change from High to Low
40
⎯
60
μs
19
FOSC = 4 MHz,
AMPIN = 250 kHz
Time it takes for /DOUT to
change from Low to High
36
⎯
56
μs
TDET2
Note: The direction of current flow should be + (sink) when flowing into the IC and − (drain) when flowing out of the IC.
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T6B70BFG
Symbol
Test
Circuit
Input dynamic range
VAMPIN
14
Pull-up resistance 1
IILRAPU1
15
VIN = VSS, Ta = 25°C
Pull-up resistance 2
IILRAPU2
15
VIN = VSS, Ta = −20 to 80°C
Pull-down resistance 1
IIHRAPD1
16
VIN = VDD, Ta = 25°C
Pull-down resistance 2
IIHRAPD2
16
VIN = VDD, Ta = −20 to 80°C
VBIAS
17
VPP
Min
Typ.
Max
Unit
VSS
⎯
VDD
V
11.6
19.4
27.2
kΩ
7
⎯
38
kΩ
5.9
9.8
13.7
kΩ
3
⎯
19.2
kΩ
No load (design target)
1.54
1.63
1.71
V
18
No load, receivable amplitude
range is 250 kHz, when sine
wave signal is applied.
(design target)
0.3
⎯
0.45
V
DETON
19
FOSC = 4 MHz
236
⎯
266
kHz
Non-detection frequency
(low frequency)
DETOFF1
19
FOSC = 4 MHz
⎯
⎯
236
kHz
Non-detection frequency
(high frequency)
DETOFF2
19
FOSC = 4 MHz
266
⎯
⎯
kHz
Characteristics
Test Condition
AMPIN pin (pin 7)
Amplifier input bias voltage
Amplifier input sensitivity
Detection frequency range
SW1IN pin (pin 14) and SW1OUT pin (pin 15)
VINASW1
⎯
VSS
⎯
VDD
V
Analog switch output voltage
VOUTASW1
⎯
VSS
⎯
VDD
V
OFF-leak current of analog
switch 1
IOFFASW1
20
/SCTL = H, SW1IN = VDD,
SW1OUT = VSS
−1
⎯
1
μA
ON-resistance of analog switch 1
RONASW1
21
/SCTL = L, SW1IN = 5 V,
SW1OUT = 0 V
Current measure
35
⎯
105
Ω
Analog switch input voltage
SW2IN pin (pin 11) and SW2OUT pin (pin 10)
VINASW2
⎯
VSS
⎯
VDD
V
Analog switch output voltage
VOUTASW2
⎯
VSS
⎯
VDD
V
OFF-leak current of analog
switch 2
IOFFASW2
20
/SCTL = H, SW2IN = VDD,
SW2OUT = VSS
−1
⎯
1
μA
ON-resistance of analog switch 2
RONASW2
21
/SCTL = L, SW2IN = 5 V,
SW2OUT = 0 V
Current measure
35
⎯
105
Ω
0.85
VDD
⎯
VDD
V
Analog switch input voltage
SOUT+ pin (13 pin), SOUT− pin (12 pin)
Output voltage
VOPP
22
Maximum voltage value when
there is no load
Pseudo sine wave output
frequency
FSIN
23
FOSC = 4 MHz
⎯
250
⎯
kHz
Pseudo sine wave output start
time
tdON
23
/SCTL = H → L
⎯
⎯
500
ns
Pseudo sine wave output stop
time
tdOFF
23
/SCTL = L → H
⎯
⎯
1
μs
Equivalent output impedance
ROUTSIN
24
No load
2.8
4
5.2
kΩ
Note: The direction of current flow should be + (sink) when flowing into the IC and − (drain) when flowing out of the IC.
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Test Circuit
(1) Current consumption
(2) Oscillation frequency
5V
5V
A
1 OSCIN
2 OSCOUT
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
FOSC
Monitor
V
2 OSCOUT
VDD 16
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
8 VSS
A
SW1OUT 15
3 FOUT
7 AMPIN
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
SW2OUT 10
/DOUT 9
IIHROSC
IILROSC
VIN
+0.1 mA
IOH
−0.1 mA
↓
VOHOSC
4 /SCTL
(4) High-level input current
Low-level input current
Low-level output voltage
5V
VIHOSC
VILOSC
SW1IN 14
8 VSS
/DOUT 9
(3) High-level input voltage
Low-level input voltage
High-level output voltage
1 OSCIN
VDD 16
SW1OUT 15
3 FOUT
7 AMPIN
SW2OUT 10
8 VSS
1 OSCIN
2 OSCOUT
SW1OUT 15
3 FOUT
7 AMPIN
ICC
VDD 16
↓
IOL
4 MHz
PG
1 to 10 MHz
PG
VOLOUT V
SW2OUT 10
5V
1 OSCIN
2 OSCOUT
SW1OUT 15
3 FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
7 AMPIN
/DOUT 9
VDD 16
SW2OUT 10
8 VSS
(5) Low to High input switching level
High to Low input switching level
/DOUT
(6) High-level input current
5V
4 MHz
PG
VIHRST
VILRST
1
OSCIN
2
OSCOUT
3
FOUT
SW1IN 14
4
/SCTL
SOUT+ 13
Monitor
5
/RESET
SOUT− 12
Monitor
6
AMPOUT
SW2IN 11
7
AMPIN
8
VSS
9
5V
VDD 16
1 OSCIN
SW1OUT 15
2 OSCOUT
IIHRST
A
VIN
SW2OUT 10
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
8 VSS
10
SW1OUT 15
3 FOUT
7 AMPIN
/DOUT 9
VDD 16
SW2OUT 10
/DOUT 9
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T6B70BFG
(7) Pull-up resistance 1
Pull-up resistance 2
(8) Low to High input switching level
High to Low input switching level
5V
1 OSCIN
1
OSCIN
SW1OUT 15
2
OSCOUT
3 FOUT
SW1IN 14
3
FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
4
/SCTL
SOUT+ 13
Monitor
5 /RESET
SOUT− 12
5
/RESET
SOUT− 12
Monitor
6 AMPOUT
SW2IN 11
6
AMPOUT
SW2IN 11
SW2OUT 10
7
AMPIN
/DOUT 9
8
VSS
2 OSCOUT
IILRRST1
IILRRST2
A
5V
4 MHz
PG
7 AMPIN
8 VSS
VDD 16
VIHSCTL
VILSCTL
(9) High-level input current
Low-level input current
VDD 16
SW1OUT 15
SW2OUT 10
/DOUT 9
(10) High-level output voltage
5V
SW1OUT 15
FOUT
SW1IN 14
4
/SCTL
SOUT+ 13
5
/RESET
SOUT− 12
6
AMPOUT
SW2IN 11
7
AMPIN
8
VSS
2 OSCOUT
↓
VOHFOUT V
SW2OUT 10
SW1OUT 15
3 FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
7 AMPIN
/DOUT 9
VDD 16
SW2OUT 10
8 VSS
(11) Low-level output voltage
/DOUT 9
(12) High-level output voltage
5V
↓
IOL
+1.0 mA
5V
VOLFOUT V
4 MHz
PG
VDD 16
1 OSCIN
VDD 16
1
OSCIN
2
OSCOUT
3
FOUT
SW1IN 14
3 FOUT
SW1IN 14
4
/SCTL
SOUT+ 13
4 /SCTL
SOUT+ 13
SOUT− 12
SW2IN 11
2 OSCOUT
SW1OUT 15
5
/RESET
SOUT− 12
5 /RESET
6
AMPOUT
SW2IN 11
6 AMPOUT
7
AMPIN
8
VSS
7 AMPIN
SW2OUT 10
8 VSS
/DOUT 9
SW1OUT 15
SW2OUT 10
/DOUT 9
VOHDOUT V
11
↓
IOH
VIN
1 OSCIN
−1.0 mA
A
OSCOUT
VDD 16
IOH
IIHSCTL 2
IILSCTL
3
OSCIN
−0.1 mA
1
5V
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(13) Low-level output voltage
(14) Input dynamic range
5V
1 OSCIN
2 OSCOUT
5V
4 MHz
PG
VDD 16
1 OSCIN
VDD 16
2 OSCOUT
SW1OUT 15
SW1OUT 15
3 FOUT
SW1IN 14
3 FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
6 AMPOUT
SW2IN 11
SW2OUT 10
8 VSS
Monitor
↓
IOL
7 AMPIN
+1.0mA
4 MHz
PG
7 AMPIN
VAMPIN
SW2OUT 10
8 VSS
/DOUT 9
V
/DOUT 9
VOLDOUT
(15) Pull-up resistance 1
Pull-up resistance 2
(16) Pull-down resistance 1
Pull-down resistance 2
5V
1 OSCIN
2 OSCOUT
IILRAPU1
IILRAPU2
A
5V
VDD 16
1 OSCIN
SW1OUT 15
2 OSCOUT
VDD 16
SW1OUT 15
3 FOUT
SW1IN 14
3 FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
6 AMPOUT
SW2IN 11
7 AMPIN
8 VSS
IIHRAPD1
IIHRAPD2
A
SW2OUT 10
VIN
/DOUT 9
(17) Amplifier input bias voltage
7 AMPIN
SW2OUT 10
8 VSS
/DOUT 9
(18) Amplifier input sensitivity
5V
1 OSCIN
2 OSCOUT
4 MHz
PG
VDD 16
SW1OUT 15
1 OSCIN
2 OSCOUT
VDD 16
SW1OUT 15
3 FOUT
SW1IN 14
3 FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
6 AMPOUT
SW2IN 11
7 AMPIN
VBIAS V
5V
8 VSS
Monitor
250 kHz Vp-p
SIN wave
SW2OUT 10
/DOUT 9
7 AMPIN
8 VSS
12
SW2OUT 10
/DOUT 9
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(19) Detection frequency range
Non-detection frequency (low frequency)
Non-detection frequency (high frequency)
Non-reception to reception detection time
Reception to non-reception detection time
(20) OFF-leak current of analog switch 1
OFF-leak current of analog switch 2
5V
DETON
DETOFF1
DETOFF2
200 to
300 kHz PG
SW1OUT 15
2 OSCOUT
VDD 16
SW1OUT 15
3 FOUT
SW1IN 14
3 FOUT
SW1IN 14
4 /SCTL
SOUT+ 13
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
6 AMPOUT
SW2IN 11
7 AMPIN
SW2OUT 10
8 VSS
/DOUT 9
7 AMPIN
Monitor TDET1
TDET2
(21) ON-resistance of analog switch 1
ON-resistance of analog switch 2
8 VSS
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
7 AMPIN
8 VSS
A
5V
SW1IN 14
RONASW2
A
SW2OUT 10
1 OSCIN
2 OSCOUT
RONASW1
5V
3 FOUT
/DOUT 9
SW1OUT 15
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
8 VSS
/DOUT 9
VDD 16
3 FOUT
7 AMPIN
(23) Pseudo sine wave output frequency
Pseudo sine wave output start time
Pseudo sine wave output stop time
1 OSCIN
2 OSCOUT
SW1IN 14
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
7 AMPIN
8 VSS
VOPP
/DOUT 9
5V
4 MHz
PG
SW1OUT 15
4 /SCTL
V
(24) Equivalent output impedance
VDD 16
3 FOUT
V VOPP
SW2OUT 10
5V
4 MHz
PG
A
5V
4 MHz
PG
SW1OUT 15
IOFFASW2
(22) Output voltage
VDD 16
2 OSCOUT
A
SW2OUT 10
5V
1 OSCIN
IOFFASW1
5V
2 OSCOUT
1 OSCIN
5V
VDD 16
1 OSCIN
2 OSCOUT
Monitor FSIN
DEGSOUT
tdON
Monitor tdOFF
SW2OUT 10
SW1IN 14
4 /SCTL
SOUT+ 13
5 /RESET
SOUT− 12
6 AMPOUT
SW2IN 11
8 VSS
13
SW1OUT 15
3 FOUT
7 AMPIN
/DOUT 9
VDD 16
SW2OUT 10
ROUTSIN
A
A
ROUTSIN
5V
1 OSCIN
5V
5V
4 MHz
PG
/DOUT 9
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T6B70BFG
IC Marking Specification
Lot Code
T6B70BFG
Trace Code
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Toshiba CMOS SOP Embossed Taping - Common Specifications
1. Applicable Scope
This specification defines the embossed taping package specifications and related items for Toshiba flat
package CMOS ICs. As a rule, these taping specifications comply with JEITA (RC-1009B) and EIA (EIA481).
2. Specifications
2.1
Tape Form and Dimensions
Package
JEITA Tape Standard
300 mm 14, 16 pin (JEITA Type II)
TE1612
300 mm 20 pin (JEITA Type II)
TE2412
P1
φD0
P2 P0
t
E
Y
W
B
F
φD1
X
X
Y
T1
Section view Y-Y
Direction of feed
Section view X-X
A
Unit: mm
A
B
W
F
E
P1
P2
P0
φD0
t
T1
φD1
14, 16
pin type
8.5
± 0.2
10.8
± 0.2
16.0
± 0.3
7.5
± 0.1
1.75
± 0.1
12.0
± 0.1
2.0
± 0.1
4.0
± 0.1
1.5
+ 0.1
−0
0.3
± 0.1
2.1
± 0.2
1.65
± 0.1
20
pin type
8.3
± 0.2
13.2
± 0.2
24.0
± 0.3
11.5
± 0.1
1.75
± 0.1
12.0
± 0.1
2.0
± 0.1
4.0
± 0.1
1.5
+ 0.1
−0
0.3
± 0.1
2.2
± 0.2
2.0
± 0.2
Note 1: The tape surface resistance shall be 106 Ω/cm or less.
Note 2: The accumulated error tolerance for the feed hole pitch (P0) shall be ≤ ± 0.2 mm per 10 pitches.
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T6B70BFG
2.2
Seal Tape Dimensions
Unit: mm
2.3
Tape Width
Tape Thickness
14,16 pin type
13.5
0.06
20 pin type
21.5
0.06
Reel Form and Dimensions
(Unit: mm)
2.5
φ330 ± 2
R1.0
φ80 ± 2
φ13 ± 0.5
2 ± 0.5
φ21 ± 0.8
W
(a)
T
t = 3.0 max
Unit: mm
14,16 pin
+ 2.0
16.4 − 0
20 pin
+ 2.0
24.4 − 0
W dimension
(a)
2.4
Bar code label (See page 18)
Insertion Direction
Pin 1
Type L (EL)
2.5
Direction
of feed
Tape Minimum Bending Radius
The strength of the seal tape shall not change even when an IC is inserted into the tape and the tape
is bent 40 mm. In addition, the tape and inserted IC shall not change under the corresponding
conditions.
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2.6
Seal Tape Peeling Strength
165 to 180°
300 mm/minut
The seal tape shall maintain a peeling strength of 0.1 N (10 gf) when tape bonding surface is at 165 to
180° and being pulled at a speed of 300 mm per minute. However, the seal tape shall not fracture or
break when it is being peeled.
2.7
Leader and Trailer Sections of the Tape
Empty cavities shall be created in leader and trailer sections of the tape in which ICs shall not be
inserted as specified below:
Seal Tape
Carrier Tape
Leader section
Minimum of 500 mm
Minimum of 400 mm
Trailer section
Minimum of 400 mm
Minimum of 400 mm
Carrier tape
Seal tape
Start end
Hub end
Trailer section
Empty cavities in which
ICs shall not be inserted
Empty cavities
in which ICs shall
not be inserted
Leader section
2.8
IC Insertion Failure Ratio
Item
Tolerated Ratio
Consecutive insertion failure
Non-consecutive insertion failure
None
0.1 % or less (per reel)
17
Comments
Does not apply to the empty
cavities in the leading and
trailing sections of the tape.
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T6B70BFG
3. Standard Packaging Unit
The standard packaging unit for one reel of tape shall be 2000 units.
4. Labeling
The reel shall be labeled with the following:
1) Product Name
2) Quantity
3) Lot No.
5. Boxing
Each completed reel of tape shall be boxed in a cardboard box (one per box). The box shall also be labeled
with the same labeling information as the reel (see above).
Dimensions
Unit: mm
A
B
C
14, 16 pin type
340
25
27
20 pin type
340
33
35
Bar code label
C
(inner dimension)
A
30
A
B
(inner dimension)
(inner dimension)
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6. Issuing Purchase Orders
When issuing IC purchase orders using the taping packaging information, be sure to include the product
name, taping type, insertion direction and quantity as follows:
Example:
TC74HC00F
(EL)
10000
• Quantity
• Insertion
• Taping type
• IC part number
7. Delivery and Storage Precautions
Tape reels should be delivered with enough care so as to prevent extreme vibration from impacting the
product. Tape reels should be kept out of direct sunlight and be kept below 45°C during delivery and storage
so as to prevent wearing down the peeling strength of seal tape and/or causing other deformities to the tape.
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T6B70BFG
Package Dimensions
Weight: 0.16 g (typ.)
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About solderability, following conditions were confirmed
● Solderability
(1) Use of Sn-37Pb solder Bath
･ solder bath temperature = 230℃
･ dipping time = 5 seconds
･ the number of times = once
･ use of R-type flux
(2) Use of Sn-3.0Ag-0.5Cu solder Bath
･ solder bath temperature = 245℃
･ dipping time = 5 seconds
･ the number of times = once
･ use of R-type flux
RESTRICTIONS ON PRODUCT USE
070711EBA
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety
in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are designed and manufactured for usage in hot water dispensers.
Do not use any of these products for any purposes other than hot water dispensers, unless otherwise agreed in
writing by TOSHIBA.
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from
its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third
parties.
• Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of
controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance
with applicable laws and regulations.
• The products described in this document are subject to foreign exchange and foreign trade control laws.
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