WEDC WEDPY256K72V

White Electronic Designs
WEDPY256K72V-XBX
256Kx72 Synchronous Pipeline SRAM
DESCRIPTION
FEATURES
Fast clock speed: 100, 133, 150, 166
and 200** MHz
Fast access time: 5.0, 4.0, 3.8, 3.5, 3.1ns
+3.3V power supply (VCC)
+2.5V output buffer supply (VCCQ)
Single-cycle deselect
Common data inputs and data outputs
Clock-controlled and registered addresses, data
I/Os and control signals
SNOOZE MODE for reduced-power standby
Individual BYTE WRITE control and GLOBAL
WRITE
The WEDPY256K72V-XBX employs high-speed, lowpower CMOS designs that are fabricated using an
advanced CMOS process. The 16Mb Synchronous
SRAMs integrate two 256K x 36 SRAMs into a single
PBGA package to provide 256K x 72 configuration. All
synchronous inputs are controlled by a positive-edgetriggered single-clock input (CLK). The synchronous inputs
include all addresses, all data inputs, and active LOW chip
selects (CS#). Asynchronous inputs include the output
enable (OE1#/OE2#), clock (CLK).
* This product is subject to change without notice.
FIGURE 1 – BLOCK DIAGRAM
Six chip enables for simple depth expansion and
address pipeline
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Packaging:
159-bump PBGA package, 14mm x 22mm
Commercial, industrial, and military temperature
ranges
User configurable as 512K x 36, or 1M x 18
256Kx36
A0-17 SSRAM
ADSC#
ADSP#
ADV#
BWa#
BWb#
BWc#
BWd#
WE#
DQ0-35
CS1#
CS2#
CS2
CLK
GW#
MODE
OE#
ZZ
SA0-17
ADSC#
ADSP#
ADV#
BWa#
BWb#
BWc#
BWd#
BWE#
CS11#
CS21#
CS21
CLK
GW#
MODE
OE1#
ZZ
**200 MHz for commercial and industrial temperature only.
IC1
BWe#
BWf#
BWg#
BWh#
CS11#
CS22#
CS22
OE2#
August 2004
Rev. 7
1
256Kx36
SSRAM
A0-17
ADSC#
ADSP#
ADV#
BWa#
BWb#
BWc#
BWd#
WE#
CS1#
CS2#
CS2
CLK
GW#
MODE
OE#
ZZ
DQ0-35
IC2
DQ36-71
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White Electronic Designs
WEDPY256K72V-XBX
PIN CONFIGURATION
(Top View)
1
2
3
4
5
6
7
8
9
10
A
—
DQ16
DQ14
DQ12
DQ10
ZZ
DQ6
DQ4
DQØ
DQ8
B
ADV#
DQ17
DQ15
DQ11
DQ9
DQ7
DQ5
DQ3
DQ1
SA13
C
OE1#
ADSP#
GW#
DQ13
DNU
GND
DQ29
DQ2
SA12
SA10
D
CS21#
CLK
BWa#
GND
GND
VCC
VCCQ
SA11
SA9
SA6
E
BWc#
BWb#
BWd#
GND
VCC
GND
GND
SA8
SA7
SAØ
F
CS21
DQ18
DQ22
VCC
VCCQ
GND
VCC
DQ30
DQ34
SA1
G
CS11#
DQ19
DQ23
GND
VCC
VCCQ
GND
DQ31
DQ33
SA5
H
DQ26
DQ20
DQ24
VCCQ
VCCQ
VCC
VCC
DQ28
DQ32
DQ35
J
SA17
DQ21
DQ25
VCC
VCC
VCCQ
VCCQ
DQ27
DQ39
DQ37
K
SA16
DQ52
DQ49
GND
VCCQ
VCC
GND
DQ40
DQ38
DQ36
L
SA14
DQ51
DQ50
VCC
GND
VCCQ
VCC
DQ42
DQ41
DQ44
M
SA15
DQ53
DQ48
GND
GND
VCC
GND
DQ43
SA3
DNU
N
OE2#
ADSC#
DQ47
VCCQ
VCC
GND
GND
MODE
SA2
SA4
P
BWE#
CS22#
DQ46
DQ45
GND
DNU
DQ59
DQ64
DQ66
DQ70
R
BWh#
BWg#
BWf#
BWe#
DQ56
DQ60
DQ61
DQ65
DQ69
DQ71
T
CS12#
CS22
DQ62
DQ54
DQ55
DQ57
DQ58
DQ63
DQ67
DQ68
DNU = DO NOT USE. RESERVED FOR FUTURE UPGRADES.
August 2004
Rev. 7
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WEDPY256K72V-XBX
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
First Address (External)
Second Address (Internal)
Third Address (Internal)
X...X00
X...X01
X...X10
Fourth Address (Internal)
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (X36)
Function
GW#
BWE#
BWa#
BWb#
BWc#
BWd#
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte "a"
H
L
L
H
H
H
WRITE All Bytes
H
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
NOTE:
1. Using BWE# and BWa# through BWd#, any one or more bytes may be written.
2. Insert BWe# through BWh# for DQ36-71 control.
August 2004
Rev. 7
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WEDPY256K72V-XBX
TRUTH TABLE
Operation
Address Used
CS1
CS2
CS2
ZZ
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselected Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
HIGH Z
Deselected Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
HIGH Z
Deselected Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
HIGH Z
Deselected Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
HIGH Z
Deselected Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
HIGH Z
SNOOZE MODE, Power-Down
None
X
X
X
H
X
X
X
X
X
X
HIGH Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
HIGH Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
HIGH Z
External
L
L
H
L
H
L
X
H
H
L-H
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
HIGH Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
HIGH Z
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
HIGH Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
HIGH Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE:
1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or WE#) are LOW or GW# is
LOW. WRITE# = H for all BWx#, BWE#, GW# High.
3. BWa enables WRITEs to DQ0-8. BWb# enables WRITEs to DQ9-17. BWc enables WRITEs to DQ18-26. BWd# enables
WRITE to DQ27-35.
4. All inputs excepts OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending bursts.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be held in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
August 2004
Rev. 7
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White Electronic Designs
WEDPY256K72V-XBX
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply relative to VSS
Voltage on VCCQ Supply relative to VSS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to +4.6V
-0.5V to VCCQ +0.5V
-0.5V to VCC +0.5V
-55°C to +150°C
100 mA
* Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
-55°C ≤ TA ≤ +125°C
Description
Input High (Logic 1)Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Ouptut Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Output Buffer Supply
Symbol
VIH
VIHQ
VIL
ILI
ILO
VOH
VOL
VCC
VCCQ
Conditions
Inputs
Data (DQ)
Min
1.7
1.7
-0.3
-2.0
-1.0
2.0
—
3.135
2.375
0V ≤ VIN ≤ VCC
Outputs disabled, 0V ≤ VIN ≤ VCCQ (DQX)
IOH = -1.0mA
IOL = 1.0mA
Max
VCC +0.3
VCCQ +0.3
0.7
2.0
1.0
—
0.4
3.6
2.9
Units
V
V
V
µA
µA
V
V
V
V
Notes
1
1
1
2
1
1
1
1
NOTES:
1. All voltages referenced to Vss (GND).
DC CHARACTERISTICS
-55°C ≤ TA ≤ +125°C
Units
Notes
Power Supply
Current: Operating
Description
IDD
Device selected; All inputs ≤ VIL or ≥ VIH; Cycle
time ≥ tKC MIN; VCC = MAX; Outputs open
Conditions
100 MHz 133 MHz 150 MHz 160 MHz 200 MHz
600
750
950
950
1050
mA
1.2
CMOS Standby
ISB2
Device deselected; VCC = MAX; All inputs ≤ Vss
+ 0.2
20
20
20
20
20
mA
2
Clock Running
ISB4
Device deselected; VCC = MAX; All inputs ≤ Vss +
0.2 or ≥ VCC -0.2; Cycle time ≥ tKC MIN; ADSC#,
ADSP#, GW#, BWx#, ADV#, ≥ VIH
170
180
220
220
240
mA
2
NOTES:
1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode).
BGA CAPACITANCE
TA = +25°C, F = 1MHz
Description
Control Input Capacitance
Common Control Input Capacitance (2)
Input/Output Capacitance (DQ)
Address Capacitance (SA)
Clock Capacitance (CLK)
BGA THERMAL RESISTANCE
Description
Junction to Ambient (No Airflow)
Junction to Ball
Junction to Case (Top)
Symbol Max Units Notes
CI
6
pF
1
CIC
15
pF
1
CO
10
pF
1
CsA
15
pF
1
CCK
12
pF
1
Symbol Max
Theta JA 30.5
Theta JB 17.3
Theta JC 9.8
Units Notes
0
C/W
1
0
C/W
1
0
C/W
1
NOTE 1: Refer to BGA Thermal Resistance Correlation application note at www.wedc.
com in the application notes section for modeling conditions.
NOTES:
1. This parameter is guaranteed by design but not tested.
2. Common Inputs = zz, ADV#, ADSP#, GW#, ADSC#, MODE#, BWE#.
August 2004
Rev. 7
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WEDPY256K72V-XBX
AC CHARACTERISTICS
-55°C ≤ TA ≤ +125°C
Symbol
100MHz
Min.
Max
Parameter
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time (6)
Clock LOW Time (6)
10
tKC
tKF
tKH
tKL
Output Times
Clock to output valid
Clock to output invalid (2)
Clock to output on Low-Z (2,3,4)
Clock to output in High-Z (2,3,4)
OE# to output valid (5)
OE# to output in Low-Z (2,3,4)
OE# to output in High Z (2,3,4)
Hold Times
Address (7) (7)
Address status (ADSC#, ADSP#) (7)
Address advance (ADV) (7)
Write Enable (WE#) (7)
Data-in (6,7)
Chip Enable (CS) (7)
150MHz
Min
Max
166MHz
Min
Max
200MHz*
Min
Max
7.5
7.0
6.0
5.0
100
3.0
3.0
133
2.5
2.5
5.0
tKQ
tKQX
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
Setup Time
Address (6,7)
Write Enable (WE#) (7)
Address status, (ADSC#, ADSP#) (7)
Address advance (ADV#) (7)
Data-in (6,7)
Chip enable (CE#) (7)
133MHz
Min
Max
1.5
1.5
150
2.5
2.5
4.0
1.5
0
5.0
5.0
0
4.5
2.3
2.3
3.8
1.5
0
4.2
4.2
0
166
2.0
2.0
3.5
15
0
4.0
4.0
0
4.2
200
3.1
1.0
0
3.5
3.5
0
4.0
3.1
3.1
0
3.5
3.0
Units
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
tADSS
tAAS
tDS
tCES
2.0
2.0
2.0
2.0
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tAH
tADSH
tAAH
tWH
tDH
tCEH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tAS
tWS
* Commercial and industrial temperatures only.
NOTES:
1. Test conditions as specified with the output loading as shown in test conditions unless otherwise noted.
2. This parameter is measured with output load as shown in test conditions.
3. This parameter is not tested.
4. Transition is measured ±500mV from steady state voltage.
5. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
6. Measured at HIGH above VIH and LOW below VIL
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK to remain enabled.
Output Loads
Output
+2.5V
Z0 = 50Ω
1,667Ω
50Ω
Output
1,538Ω
Vt = 1.25V for 2.5 V I/O
5pF
Vt = 1.25V
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
2.5V I/O
Unit
Vss to 2.5
V
1
ns
1.25
V
1.25
V
See figures, at left
AC Output Load Equivalent
August 2004
Rev. 7
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WEDPY256K72V-XBX
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode
in which the device is deselected and current is reduced
to ISB2Z. The duration of SNOOZE MODE is dictated by
the length of time ZZ is in a HIGH state. After the device
enters SNOOZE MODE, all inputs except ZZ become
gated inputs and a ignored.
ZZ is an asynchronous, active HIGH input that causes
the device to enter SNOOZE MODE. When ZZ becomes
a logic HIGH, ISB2Z is guaranteed after the setup time
tzz is met. Any READ or WRITE operation pending when
the device enters SNOOZE MODE is not guaranteed
to complete successfully. Therefore, SNOOZE MODE
must not be initiated until valid pending operations are
completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Description
Current during SNOOZE MODE
Conditions
Symbol
ZZ ≥ VIH
ISB2Z
ZZ active to input ignored
tZZ
ZZ inactive to input sampled
tRZZ
ZZ active to snooze current
tZZI
ZZ inactive to exit snooze current
tRZZI
Min
Max
Units
20
mA
2 (tKC)
ns
2 (tKC)
2 (tKC)
0
Notes
1
ns
1
ns
1
ns
1
NOTES:
1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLOCK
t ZZ
t RZZ
ZZ
t ZZI
ISUPPLY
ALL INPUTS
(except ZZ)
t RZZI
I ISB2Z
DESELECT or READ Only
Deselect or Read Only
Normal
Operation Cycle
Output (Q)
HIGH-Z
DON'T CARE
August 2004
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WEDPY256K72V-XBX
FIGURE 2 – READ TIMING3
tKC
CLK
tKH tKL
tADSS tADSH
ADSP#
tADSS tADSH
ADSC#
tAS tAH
Address
A1
A2
A3
Burst continued with new base address
tWS tWH
GW#, BWE#
BWa-BWd
Deselect cycle (Note 4)
tCES tCEH
CS1#
(Note 2)
tAAS tAAH
ADV#
ADV# suspends burst
OE#
(NOTE 3)
tKQLZ
Q#
tOEHZ
Q(A1)
High-Z
tOEQ
tOELZ
tKQ
tKQX
Q(A2)
tKQHZ
Q
(A2+1)
Q(A2+2)
Q(A2)
Q(A2+1)
Q(A3)
Burst wraps around
to its initial state
(NOTE 1)
tKQ
Single READ
Q(A2+3)
Burst Read Cycle
Don’t care
Undefined
NOTES:
1. DQ (A2) refers to output from address A2. DQ (A2+ 1) refers to output from the next internal burst address following A2.
2. CS2# and CS2# have timing identical to CS1#. On this diagram. When CS1 is LOW, CS2# is LOW and CS2# is HIGH.
When CS1# is HIGH, CS2# is HIGH and CS2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to
be driven until after the following clock rising edge.
4. Outputs are disabled within two clock cycles after deselect.
August 2004
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WEDPY256K72V-XBX
FIGURE 3 – WRITE TIMING
tKC
CLK
tKH
tKL
tADSS tADSH
ADSP#
ADSC# extends burst
tADSS tADSH
tADSS tADSH
ADSC#
tAS tAH
Address
A1
A2
A3
Byte write signals are ignored for first cycle
when ADSP# initiates burst.
tWS tWH
BWE#
BWa-BWd#
(Note 5)
tWS tWH
GW#
tCES tCEH
CS1#
(Note 2)
tAAS tAAH
ADV#
(Note 4)
OE#
ADV# suspends burst
(Note 3)
tDS
D
D(A1)
D(A1)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
(Note 1)
tQEHZ
Q
Burst Read Cycle
Single
Write
Extended Burst Write
Burst Write Cycle
Don’t care
Undefined
NOTES:
1. D(A2) refers to input for address A2. D(A2 +1) refers to input for the next internal burst address following A2.
2. CS2# and CS2 have timing identical to CS1#. On this diagram, when CS1# is LOW, CS2# is LOW and CS2#
is HIGH. When CS1# is HIGH, CS2 is HIGH and CS2 is LOW.
3. OE# msut be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
input/output data contentinon for th etime period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH, BWE# LOW and BWa#-BWd# LOW.
August 2004
Rev. 7
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WEDPY256K72V-XBX
FIGURE 5 – READ/WRITE TIMING3
tKC
CLK
tKH tKL
tADSS tADSH
ADSP#
ADSC#
tAS
Address
A1
tAH
A2
A3
A5
A4
A6
tWS tWH
BWE#, BWa#-BWd#
(Note 4)
tCES tCEH
CS#
(Note 2)
ADV#
OE#
tDS tDH
tKQ
D
High-Z
tKQLZ
Q#
High-Z
tOELZ
D(A2)
Q(A1)
Back-to-Back READs
(Note 5)
D(A5)
tOEHZ
D(A6)
(NOTE 1)
Q(A4)
Q(A2)
Single WRITE
Q
(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Burst Read
Don’t care
Undefined
NOTES:
1. Q(A4) refers to output from addrss A4. Q(A4 + 1) refers to output from the next internal burst address to following A4.
2. CS2# and CS2 have timing identical to CS1#. On this diagram, when CS1# is LOW, CS2# is LOW and CS2# is HIGH.
When CS1# is HIGH, CS2 is HIGH and CS2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to back READs may be controlled by either ADSP# or ADSC#.
August 2004
Rev. 7
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WEDPY256K72V-XBX
PACKAGE DIMENSION – 159 BUMP PBGA
Bottom View
22.1 (0.870) MAX
19.05 (0.750) NOM
1.27 (0.050) NOM
159x ? 0.762 (0.030) NOM
0.61 (0.024) NOM
1.27 (0.050) NOM
11.43 (0.450) NOM
2.03 (0.080) MAX
14.1 (0.555) MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P Y 256K72 V - X B X
DEVICE GRADE:
M = Military
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE:
B = 159 Plastic Ball Grid Array (PBGA)
FREQUENCY (MHz)
100 = 100MHz
133 = 133MHz
150 = 150MHz
166 = 166MHz
200 = 200MHZ
3.3V Power Supply
CONFIGURATION, 256k x 72
SSRAM, Pipeline Burst
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
August 2004
Rev. 7
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WEDPY256K72V-XBX
Document Title
256K x 72 Synchronous SRAM
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
July 2001
Advanced
Rev 1
Changes (Pg. 1, 5)
1.1 Add speed grades (100MHz-200MHz) to DC
Characteristics Table
Rev 2
Change (Pg. 1)
January 2002
Preliminary
September 2002
Preliminary
November 2002
Preliminary
May 2003
Preliminary
November 2003
Preliminary
August 2004
Final
1.1 Change product status from Advanced to Preliminary.
Rev 3
Change (Pg. 1, 11)
1.1 Change Package Dimension title from Top View to
Bottom View
Rev 4
Changes (Pg. 1, 5)
1.1 BGA Capacitance: Change CI from 10pF to 6pF
1.2 Change CIP to CIC, capacitance from 20pF to 15pF
1.3 Change CCK from 20pF to 12pF
1.4 Change CO from 12pF to 10pF
1.5 Change CSA from 20pF to 15pF
1.6 Add Note 2: Control Inputs = zz, ADV#, ADSP#, GW#,
ADSC#, MODE#, BWE#.
Rev 5
Changes (Pg. 1, 5, 7, 12)
1.1 Add Thermal Resistance Table
1.2 Correct formatting on page 7
Rev 6
Changes (Pg. 1, 11, 12)
1.1 Change mechanical drawing to new style
Rev 7
Changes (Pg. 1, 12
1.1 Change status to Final
August 2004
Rev. 7
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com