Rev 0; 4/08 5- to 10-Cell Li+ Protector with Cell Balancing The DS2726 provides full charge and discharge protection for 5- to 10-cell lithium-ion (Li+) battery packs. The protection circuit monitors individual cell voltages to detect overvoltage and undervoltage conditions. Protection against discharge overcurrent and short-circuit current is provided with user-selectable thresholds using external resistors. P-channel protection FETs are employed high side and driven from on-chip 10V FET drivers. Cell balancing can be enabled to ensure that all cells are equally charged. Applications Power Tools Features ♦ Complete Protection for 5- to 10-Cell Li+ Packs ♦ Pin Programmable for 5 to 10 Cells ♦ ±50mV Overvoltage Accuracy ♦ Internal Cell-Balancing Circuit, Shunts Up to 300mA ♦ Pin-Programmable VOV Threshold ♦ Pin-Programmable Cell-Balance Voltage ♦ Overdischarge Current and Short-Circuit Current Set with External Resistors ♦ Overdischarge Current and Short-Circuit Current Timeout Delay Set with External Capacitors Electric Bikes Home Appliances ♦ Low Power Consumption: 60µA (typ) Simplified Typical Application Circuit ♦ Low Shutdown Power Consumption: 5µA (typ) ♦ 7mm x 7mm, 32-Pin TQFN Lead-Free Package Ordering Information PKP+ VCC PKP VCC CC SNS DC VIN V10 V09 SEL0 PART TEMP RANGE PIN-PACKAGE DS2726G+ -20°C to +85°C 32 TQFN-EP* DS2726G+T&R -20°C to +85°C 32 TQFN-EP* +Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. V08 SEL1 OVS0 V07 OVS1 CBS0 CBS1 V06 CBCFG SLEEP SLEEP DS2726 V05 CSCD V04 VIN Pin Configuration appears at end of data sheet. V03 RSC RDOC V02 CDOCD V01 V00 GND PKP- ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS2726 General Description DS2726 5- to 10-Cell Li+ Protector with Cell Balancing ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Vx to Vx-1 (V10 to V09).......-0.3V to +12V Continuous Power Dissipation (TA = +70°C) 32-Pin, 7mm x 7mm Thin QFN (derate 37mW/°C above +70°C) ................................2963mW Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Voltage Range on V00–V10, PKP, RDOC, RSC Pins Relative to GND .....................-0.3V to +60V Voltage Range on DC Pin Relative to VIN ..............-12V to +0.3V Voltage Range on CC Pin Relative to PKP .............-12V to +0.3V Voltage Range on CSCD, SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP, CBCFG, VCC Pins Relative to GND ...................-0.3V to +6.0V Human Body Model (HBM) ESD Limit of V05–V09 Pins ...................................................................500V All Other Pins......................................................................2kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -20°C to +85°C.) PARAMETER Supply Range SYMBOL VIN Input Range: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, CSCD, CDOCD, SLEEP, CBCFG CONDITIONS (Notes 1, 2, 3, 4) (Note 1) MIN TYP MAX UNITS 5 50 V -0.3 VCC + 0.3 V MAX UNITS DC ELECTRICAL CHARACTERISTICS (TA = -20°C to +85°C.) PARAMETER SYMBOL IDD Supply Current CONDITIONS Protector mode, no fault (Notes 4, 9) IDD_BAL Load balancing (Note 11) I SLEEP Sleep mode V00–V10 Leakage Current MIN All cell voltages = 4.2V (Note 10) 70 5.0 -2 VIH ILOAD = 2μA (Notes 1, 5) VCC 0.4 Input Logic-Mid: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VIM ILOAD = 0 (Notes 1, 5) 1.30 Input Logic-Low: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VIL ILOAD = -2μA (Notes 1, 5) ILOAD = 1mA (Notes 1, 5, 8) VCC Dropout Voltage (Note 6) Output Low: CC Output Low: CC Driver Current 2 VOLCC I OL = -100μA, VPKP 13V (Notes 3, 5) 90 400 Input Logic-High: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VCC Output Voltage TYP 4.75 μA 7.5 +2 μA V 1.65 5.00 2.00 V GND + 0.4 V 5.25 V 5.5 V V PKP - 12 PKP - 8 CC = V OLCC + 2V -3 -1 CC = V OHCC - 1V -15 -7 _______________________________________________________________________________________ mA 5- to 10-Cell Li+ Protector with Cell Balancing DS2726 DC ELECTRICAL CHARACTERISTICS (continued) (TA = -20°C to +85°C.) PARAMETER Output High: CC SYMBOL VOHCC Output High: CC Driver Current Output Low: DC VOLDC VOHDC Output High: DC Driver Current Maximum Balancing Current MIN TYP PKP 0.5 I OH = 100μA UNITS PKP + 0.3 V CC = V OLCC + 2V 7 15 0.5 1.5 VIN 12 VIN 8 -3 -1 -15 -7 VIN 0.5 VIN + 0.3 I OL = -100μA, VVIN 13V (Notes 3, 5) I OH = 100μA DC = V OLDC + 2V 7 15 DC = V OHDC - 1V 0.5 1.5 IBAL Balance FET: On-Resistance MAX CC = V OHCC - 1V DC = V OLDC + 2V DC = V OHDC - 1V Output Low: DC Driver Current Output High: DC CONDITIONS mA V mA V mA 300 mA 1.7 3.2 7.0 MIN TYP MAX UNITS OVS1 = GND, OVS0 = GND 4.05 4.10 4.15 OVS1 = GND, OVS0 = N.C. 4.10 4.15 4.20 OVS1 = GND, OVS0 = VCC 4.15 4.20 4.25 OVS1 = N.C., OVS0 = GND 4.20 4.25 4.30 OVS1 = N.C., OVS0 = N.C. 4.25 4.30 4.35 OVS1 = N.C., OVS0 = VCC 4.30 4.35 4.40 OVS1 = VCC, OVS0 = GND 4.35 4.40 4.45 OVS1 = VCC, OVS0 = N.C. 4.40 4.45 4.50 OVS1 = VCC, OVS0 = VCC 4.45 4.50 4.55 IBAL = 180mA ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT (TA = 0°C to +50°C.) PARAMETER Overvoltage Detect SYMBOL VOV Charge-Enable Voltage Charge-Balance Voltage Undervoltage Release Undervoltage Detect RDOC, RSC Output Current RDOC, RSC Input Offset Voltage CONDITIONS VCE VBAL VBAL lowest typical set point limited to 3.75V VUVREL VOVMIN 0.15 VOVMAX 0.15 V VOVMIN CellBalancing Threshold VOVMAX CellBalancing Threshold V 2.7 VUV VVIN - VRDOC = V VIN - VRSC = 2V V 2.8 2.9 V 2.2 2.3 2.4 V 0.95 1.00 1.05 μA +3 mV -3 _______________________________________________________________________________________ 3 DS2726 5- to 10-Cell Li+ Protector with Cell Balancing ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT (continued) (TA = 0°C to +50°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Overvoltage Delay t OVD 128 x tDOCDMIN 128 x tDOCDMAX ms Undervoltage Delay tUVD 128 x tDOCDMIN 128 x tDOCDMAX ms Discharge Overcurrent Delay Short-Circuit Delay Charger-Detect Threshold (VPKP - VVIN) Test Threshold Test Current Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: 4 tDOCD t SCD CDOCD = 100pF (Notes 7, 12) 2.56 3.20 3.84 CDOCD = 1000pF (Notes 7, 12) 25.6 32.0 38.4 CSCD = 100pF (Notes 7, 12) 45 58 72 CSCD = 1000pF (Notes 7, 12) 405 508 612 VCDET VTP ITST 3 17 ms μs mV DOC conditions 0.8 1.2 1.7 V DOC condition, VIN - VPKP = 2V 68 120 200 μA DOC condition, VIN - VPKP = 50V 0.5 1.20 1.8 mA All voltages relative to GND. Voltages below this level cannot be monitored; therefore, CC and DC are off below this value. Full-gate drive is not achieved until the voltage source for the gate driver (VPKP or VVIN) is above 13V. With 10µF decoupling capacitor. ILOAD is the current load on the pin specified in the parameter. VCC cannot meet specification if VVIN is below this value. Capacitance tolerance introduces additional error. With ≥ 0.1µF decoupling capacitor. Current is an average. Spikes up to 200µA when measuring cell voltages. Current is an average. Spikes up to 15µA when measuring cell voltages. Current depends on the number of cells being balanced. Includes switching time and comparator delay with 25mV overdrive. _______________________________________________________________________________________ 5- to 10-Cell Li+ Protector with Cell Balancing UV ACCURACY vs. TEMPERATURE 0.014 0.001 -0.001 -0.003 0.010 0.8 ITST (mA) UV ACCURACY (V) 0.003 0.008 0.6 0.006 0.4 0.004 -0.005 0.2 0.002 -0.007 -0.009 10 35 85 60 -40 -15 TEMPERATURE (°C) 10 35 DS2726 toc04 50 DS2726 toc05 1 40 -1 DISCHARGE OVERCURRENT THRESHOLD 20 10 -7 LOAD CURRENT (A) 30 -3 VGS DISCHARGE FET (V) LOAD CURRENT 40 50 60 120 100 -3 80 LOAD CURRENT -5 60 SHORT-CIRCUIT THRESHOLD -7 VGS DISCHARGE FET 0 -9 -11 20 30 40 20 -11 50 40 VGS DISCHARGE FET -9 -10 10 30 (VVIN - VPKP) (V) SHORT-CIRCUIT CONDITION -1 0 0 TIME (ms) 50 100 TIME (μs) FET TURN-OFF TIME (WITH 460nC TOTAL GATE CHARGE) DS2726 toc06 40 35 30 25 5V/div 0 20 SHORT-CIRCUIT DELAY (CDOCD = 1000pF, RSC = 247.5kΩ WITH RDS_ON = 2.75MΩ) DOC CONDITION -5 10 TEMPERATURE (°C) DISCHARGE OVERCURRENT DELAY (CDOCD = 1000pF, RDOC = 110kΩ WITH RDS_ON = 2.75kΩ) 1 0 85 60 LOAD CURRENT (A) -15 VTP = 1.16V 0 0 -40 VGS DISCHARGE FET (V) OV ACCURACY (V) 1.0 0.012 0.005 DS2726 toc03 DS2726 toc01 0.007 TEST CURRENT vs. (VVIN - VPKP) 1.2 DS2726 toc02 OV ACCURACY vs. TEMPERATURE 0.009 20 15 10 5 20 40 60 80 100 120 140 160 180 200 20μs/div _______________________________________________________________________________________ 5 DS2726 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) DS2726 5- to 10-Cell Li+ Protector with Cell Balancing PKP+ PKP CC SNS VIN DC RTST DS2726 10V V10 10V VOV, VBAL, VCE, VUV V09 VIN VCC VCC VCDET VOV, VBAL, VCE, VUV V08 VREG VOV, VBAL, VCE, VUV V07 SEL0 VOV, VBAL, VCE, VUV SEL1 V06 OVS0 VOV, VBAL, VCE, VUV OVS1 LOGIC V05 CBS0 VOV, VBAL, VCE, VUV CBS1 V04 CBCFG SLEEP VOV, VBAL, VCE, VUV RSC V03 tSCD VOV, VBAL, VCE, VUV VIN V02 CSCD VOV, VBAL, VCE, VUV RDOC V01 tDOCD VOV, VBAL, VCE, VUV CDOCD V00 SNS GND PKP- Figure 1. Block Diagram 6 _______________________________________________________________________________________ 5- to 10-Cell Li+ Protector with Cell Balancing PIN NAME FUNCTION 1 RSC 2 RDOC Discharge Overcurrent Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for an overcurrent condition in the discharge direction. 3 VCC Regulator Supply Output. VCC supplies power to internal circuits and can be used to pull configuration pins to VIH. It should be bypassed to GND with at least a 0.1μF ceramic capacitor. 4, 5 SEL0, SEL1 Select Number of Cells in the Battery Stack. This input is a three-level input. Connect to ground or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 2 for how to drive this pin for a particular number of cells. 6 CDOCD 7 SLEEP Sleep-Mode Select Input. Driving this pin to a logic-low level forces the part into the lowest power state. The part exits Sleep Mode once a charge voltage is applied. When CBCFG is high, a logic-high on this pin enables cell balancing. 8 CSCD Short-Circuit Current Delay Time. Connect a capacitor from this pin to GND to select the amount of time for which a short-circuit current condition must persist before shutting off the DC FET. 9 CBCFG Charge-Balance Configuration Input. When this pin is at a logic-low, charge balancing is enabled if VPKP > VVIN + VCDET. When this pin is at a logic-high, charge balancing is enabled if the SLEEP pin is at a logic-high. 10, 11 CBS0, CBS1 Select Cell-Balancing Voltage. This input is a three-level input. Connect to ground or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 4 for how to drive this pin for a particular cell-balancing voltage threshold. 12, 13 OVS0, OVS1 Select Overvoltage Threshold. This input is a three-level input. Connect to ground or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 3 for how to drive this pin for a particular overvoltage threshold. Short-Circuit Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for a short-circuit condition in the discharge direction. Discharge Overcurrent Delay Time. Connect a capacitor from this pin to GND to select the amount of time for which a discharge overcurrent condition must persist before shutting off the DC FET. 14, 30 N.C. No Connection. Not internally connected. 15 GND Ground. Connect to the negative terminal of the lowest voltage cell. 16 V00 Negative Terminal Voltage Sense. Connect to the negative terminal of the 1st cell in the battery stack. 17 V01 Cell 01 Voltage Sense. Connect to the positive terminal of the 1st cell in the battery stack. 18 V02 Cell 02 Voltage Sense. Connect to the positive terminal of the 2nd cell in the battery stack. 19 V03 Cell 03 Voltage Sense. Connect to the positive terminal of the 3rd cell inf the battery stack. 20 V04 Cell 04 Voltage Sense. Connect to the positive terminal of the 4th cell in the battery stack. 21 V05 Cell 05 Voltage Sense. Connect to the positive terminal of the 5th cell in the battery stack. 22 V06 Cell 06 Voltage Sense. Connect to the positive terminal of the 6th cell in the battery stack. 23 V07 Cell 07 Voltage Sense. Connect to the positive terminal of the 7th cell in the battery stack. 24 V08 Cell 08 Voltage Sense. Connect to the positive terminal of the 8th cell in the battery stack. 25 V09 Cell 09 Voltage Sense. Connect to the positive terminal of the 9th cell in the battery stack. 26 V10 Cell 10 Voltage Sense. Connect to the positive terminal of the 10th cell in the battery stack. 27 VIN Connect to the Most Positive Cell Terminal 28 DC Discharge Control Output. DC controls the gate of the discharge FET. Driven from VIN to V OLDC to turn on and turn off the discharge FET. _______________________________________________________________________________________ 7 DS2726 Pin Description 5- to 10-Cell Li+ Protector with Cell Balancing DS2726 Pin Description (continued) PIN NAME FUNCTION 29 SNS Sense Input. Connect to the drains of the charge and discharge FETs. Used as a voltage reference for detecting short-circuit and discharge overcurrent conditions. 31 CC Charge Control Output. CC controls the gate of the charge FET. Driven from PKP to VOLCC to turn on and turn off the charge FET. 32 PKP Pack Positive. The voltage on PKP is used to detect charger-attach and protection-release conditions. — EP Exposed Pad Ground. Connect to the negative terminal of the lowest voltage potential cell. PKP+ 15Ω VIN 150Ω 1μF 150Ω 150Ω 10μF 150Ω 150Ω V10 V09 1μF 150kΩ VCC V09 V10 DC VIN SNS CC RSC RDOC VCC SEL0 SEL1 CDOCD SLEEP CSCD V07 V08 V07 V06 V06 V05 DS2726 V05 V04 V03 V04 V02 V03 V00 V01 GND 1μF N.C. 60V 1A CBCFG SLEEP 1kΩ N.C. 10kΩ 1kΩ OVS1 1kΩ 1kΩ OVS0 0.1μF 1kΩ CBS1 1kΩ 205kΩ CBS0 1kΩ 82.5kΩ PKP V08 0.1μF V02 6.2V 1μF V01 V00 PKP- Figure 2. Typical Application Circuit 8 _______________________________________________________________________________________ 5- to 10-Cell Li+ Protector with Cell Balancing The DS2726 provides the protection features for a 5-cell to 10-cell Li+ battery pack. The Li+ protection circuit allows for pin-configured selection of OV threshold and the cell-balancing threshold. DOC and SC thresholds and delays are component programmable. Sleep Mode Sleep Mode is a low-power state where the FETs are open and the IC is not monitoring voltages. During Wake Mode, the IC measures voltages and drives the FETs to the appropriate state. Upon initial connection to cells, the DS2726 enters Sleep Mode. The IC also enters Sleep Mode if a UV condition is detected. Sleep Mode can be initiated any time by pulling the SLEEP pin low while a chargerdetect condition does not exist. During Sleep Mode there is a pulldown current from PKP to GND. VPKP must be within VTP of VVIN (VPKP > VVIN - VTP) to exit wake from Sleep Mode. When a charger is detected and VCC achieves regulation, the part measures all cells for undervoltage and overvoltage. Then the IC begins controlling the CC and DC FETs as shown in Table 1. Care should be taken to ensure that the SLEEP pin is not held low during a wake condition. Charger Detect The DS2726 has two different methods for detecting a charger connection. The methods are pin programmable at the CBCFG pin. If CBCFG is pulled to GND, then charge detection occurs when VPKP > VVIN + VCDET. If CBCFG is pulled to VCC, then charge detection occurs when the SLEEP pin is driven to a logic-high state. Li+ Protection Circuitry In Active Mode, the DS2726 constantly monitors V00– V10 to protect the battery from overvoltage and undervoltage. The voltage on the SNS pin is monitored and compared to the voltages on RDOC and RSC to protect against excessive discharge currents (discharge overcurrent and short circuit). Table 1 summarizes the conditions that activate the protection circuit, the response of the DS2726, and the thresholds that release it from a protection state. Table 1. Li+ Protection Conditions and DS2726 Responses CONDITION* Overvoltage (OV) ACTIVATION THRESHOLD DELAY RESPONSE VCELL > V OV t OVD CC Off RELEASE THRESHOLD VCELL < VCE CBCFG < VIL and VCELL < VUV_REL, then VPKP > VVIN + VCDET (Note 13) Undervoltage (UV) (Note 15) VCELL < VUV tUVD CC Off, DC Off, Sleep Mode CBCFG < VIL and VCELL > VUV_REL, then VPKP > VVIN - VTP CBCFG > VIH then SLEEP > VIH and VPKP > VVIN - VTP Discharge Overcurrent (DOC) (Note 15) Short Circuit (SC) VSNS < VRDOC tDOCD DC Off VPKP > VVIN - VTP (Note 14) VSNS < VRSC t SCD DC Off VPKP > VVIN - VTP (Note 15) *All voltages are with respect to GND. CC Off: VCC = VPKP, DC Off: VDC = VVIN. Note 13: The DC FET remains off until VCELL > VUV_REL. Note 14: With test current ITST flowing from VIN to PKP. Note 15: If a DOC condition persists indefinitely and a UV condition is reached, the IC does not enter Sleep Mode. _______________________________________________________________________________________ 9 DS2726 Detailed Description DS2726 5- to 10-Cell Li+ Protector with Cell Balancing Li+ Protection Conditions Overvoltage, OV. If any cell voltage (VCELL) exceeds the overvoltage threshold, VOV, for a period longer than overvoltage delay, t OVD , the DS2726 shuts off the external charge FET. When V CELL falls below the charge-enable threshold VCE, the DS2726 turns the charge FET on. The discharge FET remains enabled during the overvoltage event. Care should be taken while discharging during an OV condition because the current drawn by the load is going through the body diode of the CC FET. Undervoltage, UV. If VCELL drops below the undervoltage threshold, VUV, for a period longer than undervoltage delay, tUVD, the DS2726 shuts off the charge and discharge FETs and enters Sleep Mode. The device remains in Sleep Mode until a charger is detected, at which point the DS2726 wakes up and enables the CC FET. The DC FET remains disabled until every cell is above the VUV_REL threshold. Care should be taken while charging during a UV event because the charge current is flowing through the body diode of the DC FET. Discharge Overcurrent, DOC. If V SNS is less than VRDOC for a period longer than tDOCD, the DS2726 shuts off the external discharge FET. The discharge current path is not reestablished until VPKP rises above VVIN - VTP. The DS2726 provides a test current of value I TST from the PKP pin to the V IN pin to detect the removal of the offending low-impedance load. ITST is not disabled if an undervoltage condition is reached. Short Circuit, SC. If VSNS is less than VRSC for a period longer than short-circuit delay tSCD, the DS2726 shuts off the external discharge FET. The discharge current path is not reestablished until VPKP rises above VVIN - VTP. The DS2726 provides a test current of value I TST from the PKP pin to the V IN pin to detect the removal of the short. ITST is disabled if an undervoltage condition is reached. Summary. All the protection conditions described are logic ORed to affect the CC and DC outputs: DC = (Undervoltage) or (Discharge Overcurrent) or (Short Circuit) CC = (Overvoltage) or (Undervoltage and Charger Detect) VOV VCE VCELL VUV_REL VUV CHARGE VVIN VRDOC VRSC VSNS DISCHARGE VOHCC CC tOVD tOVD tUVD VOLCC VOHDC DC tSCD tOCD tUVD VOLDC POWER MODE Figure 3. Li+ Protection Circuitry Example Waveforms 10 ______________________________________________________________________________________ ACTIVE SLEEP 5- to 10-Cell Li+ Protector with Cell Balancing 8 CELLS 7 CELLS DS2726 9 CELLS 5 CELLS 6 CELLS V10 V10 V10 V10 V10 V09 V09 V09 V09 V09 V08 V08 V08 V08 V08 V07 V07 V07 V07 V07 V06 V06 V06 V06 V06 V05 V05 V05 V05 V05 V04 V04 V04 V04 V04 V03 V03 V03 V03 V03 V02 V02 V02 V02 V02 V01 V01 V01 V01 V01 V00 V00 V00 V00 V00 Figure 4. Cell Bypassing Connection Configuration for Number of Cells for battery stacks with fewer than 10 cells should be shorted to the cell connection below it. For example, a stack with 9 cells would have V9 shorted to V8 and V8 connected to the positive terminal of the 8th cell; a stack with 8 cells would have V9 shorted to V8 shorted to V7 and V7 connected to the positive terminal of the 7th cell, and so on (see Figure 4). The DS2726 protects 5 to 10 Li+-based cells connected in series. The number of cells is configured using the SEL0 and SEL1 pins according to Table 2. Pin V10 should always be connected to the positive terminal of the battery stack regardless of the number of cells in the stack. Cell connections that are not in use Table 2. Number of Cells Configuration PIN NUMBER OF SERIES-CONNECTED CELLS 5 6 7 8 9 10 10 10 10 SEL0 VIL VIM VIH VIL VIM VIH VIL VIM VIH SEL1 VIL VIL VIL VIM VIM VIM VIH VIH VIH Note: The DC FET remains off until VCELL > VUV_REL. ______________________________________________________________________________________ 11 DS2726 5- to 10-Cell Li+ Protector with Cell Balancing Configuration of Overvoltage Threshold ancing voltage is never allowed a value below 3.75V. Setting the OVS0, OVS1, CBS0, and CBS1 pins high results in a cell-balancing voltage (VBAL) of 3.75V. Nominal Cell-Balancing Voltage: VBAL = VOV – Cell-Balancing Voltage Threshold The DS2726 allows the OV threshold to be set using the overvoltage select pins. The OV threshold is configured using the OVS0 and OVS1 pins according to Table 3. Balancing begins when any cell’s voltage is greater than VBAL. When the balancing condition is met and cell balancing is enabled, the corresponding internal FET (from Vx to Vx-1) is enabled, shunting a portion of the charge current around the cell. The external resistors on V00–V10 should be chosen to limit the balancing current to a maximum of 200mA. This prevents damaging the internal cell-balancing FETs. Enabling Cell Balancing For cell balancing to begin the DS2726 must detect a charger. The charge-balancing configuration pin (CBCFG) controls how the IC detects a charger. If CBCFG is pulled to GND, balancing is enabled when the charge-current comparator detects a charger. This detection occurs when VPKP > VVIN + VCDET. If CBCFG is pulled to VCC, cell balancing is enabled when the SLEEP pin is driven to a logic-high state. Note that cell balancing must be enabled and a valid cell-balancing voltage must exist for cell balancing to occur. The DS2726 has three distinct states during balancing. A voltage measurement state of 5/32 tOCD time periods is followed by a balancing state where even numbered cells are balanced for 123/32 t OCD time periods. Another voltage measurement state of 5/32 tOCD time periods then occurs. This is followed by a balancing state where odd numbered cells are balanced for 123/32 tOCD time periods. This gives an average balancing current of approximately half the maximum balance current. Cell balancing terminates when all cell voltages are greater than VBAL. See the Measurement Sequence section. Configuration of Cell Balancing Voltage Threshold The DS2726 allows the cell-balancing threshold to be set using the cell-balance select pins. The threshold is configured using the CBS0 and CBS1 pins according to Table 4. Setting the cell-balancing voltage threshold to zero disables the cell-balancing circuitry. The nominal cell-bal- Table 3. OV Threshold Configuration PIN NOMINAL OV THRESHOLD (V) 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50 OVS0 VIL VIM VIH VIL VIM VIH VIL VIM VIH OVS1 VIL VIL VIL VIM VIM VIM VIH VIH VIH Table 4. Cell-Balancing Threshold Configuration PIN 12 CELL-BALANCING VOLTAGE THRESHOLD (OFFSET FROM V OV) (V) 0.00 0.05 0.10 0.15 0.20 CBS0 VIL VIM VIH VIL VIM CBS1 VIL VIL VIL VIM VIM 0.25 0.30 0.35 0.40 VIH VIL VIM VIH VIM VIH VIH VIH ______________________________________________________________________________________ 5- to 10-Cell Li+ Protector with Cell Balancing The DS2726 allows the selection of a short-circuit current threshold. This threshold is set using a resistor from the RSC pin to the positive terminal of the cell stack. The RSC pin sinks 1µA (nominal). The short-circuit comparator triggers when the voltage on the SNS pin is less than the voltage on the RSC pin. For example, assume a 500kΩ resistor is used on RSC, along with a DC FET with an RDS_ON of 10mΩ. This corresponds to an RSC voltage of 500kΩ x 1µA = 0.5V. Because the FET is 10mΩ, the short-circuit threshold is 0.5V/10mΩ = 50A: I SC = 1µA × RSC R DS _ ON The DS2726 allows for a delayed reaction to a short-circuit event. The short threshold must persist for the entire delay time before the DC FET begins to turn off (actual turn-off time varies based on the gate capacitance of the DC FET; see the DC pin drive capabilities in the DC Electrical Characteristics table for more details). The short-circuit delay time is set using a capacitor on the CSCD pin. The short-circuit delay time can be calculated by the equation: tSCD = CSCD x 500kΩ Be sure to select threshold and delay times that fall within the safe operating area of the FETs chosen for DC and CC. Setting the Discharge Overcurrent Threshold and Delay Time The DS2726 allows the selection of a discharge overcurrent threshold. This threshold is set using a resistor from the RDOC pin to the positive terminal of the cell stack. The RDOC pin sinks 1µA (nominal). The overcur- rent circuit comparator triggers when the voltage on the SNS pin is less than the voltage on the RDOC pin. For example, assume a 200kΩ resistor is used on RDOC, along with a DC FET with an RDS_ON of 10mΩ. This corresponds to a voltage on RDOC of 200kΩ x 1µA = 0.2V. Because the FET is 10mΩ, the discharge overcurrent threshold is 0.2V/10mΩ = 20A: IDOC = 1µA × RDOC R DS _ ON The DS2726 allows for a delayed reaction to a discharge overcurrent event. The discharge overcurrent threshold must persist for the entire delay time before the DC FET begins to turn off (actual turn-off time varies based on the gate capacitance of the DC FET; see DC pin drive capabilities in the DC Electrical Characteristics table for more details). The discharge overcurrent delay time is set using a capacitor on the CDOCD pin. The discharge overcurrent delay can be calculated by the equation: tDOCD = CDOCD x 32MΩ Be sure to select threshold and delay times that fall within the safe operating area for the FETs chosen for DC and CC. If the voltage on the CDOCD pin is within approximately 1V of VCC or GND, the condition is considered to be a fault, and the CC and DC outputs are disabled. This results in a delay before enabling the FETs when the part awakens from Sleep Mode. This delay occurs until the voltage on CDOCD reaches an acceptable level. This is a function of the capacitor on CDOCD. The CDOCD startup delay is in addition to a typical regulator startup of 100µs, and is given by the equation: STARTUP DELAY ≈ 100µs + CDOCD x 1.65MΩ Be sure to select threshold and delay times that fall within the safe operating area for the FETs chosen for DC and CC. ______________________________________________________________________________________ 13 DS2726 Setting the Short-Circuit Threshold and Delay Time DS2726 5- to 10-Cell Li+ Protector with Cell Balancing Measurement Sequence The period with which the DS2726 measures voltages is a function of the discharge overcurrent delay time, tDOCD. Figure 5 illustrates the measurement sequence. One measurement period: 4 x tDOCD VUV, VUV_REL, VCE, VOV, and VBAL are measured for all cells: 5 x tDOCD/32 Chip performs balancing on even cells: 123 x tDOCD/32 One measurement period: 4 x tDOCD VUV, VUV_REL, VCE, VOV, and VBAL are measured for all cells: 5 x tDOCD/32 Chip performs balancing on odd cells: 123 x tDOCD/32 One cell-balancing period: 8 x tDOCD Overvoltage and Undervoltage Delay Time Cell voltages are measured simultaneously and then sequentially compared to each of the five thresholds VUV, VUV_REL, VCE, VOV, and VBAL. This sequence is repeated every four tDOCD intervals. Overvoltage and undervoltage conditions are time qualified and therefore not recognized immediately. If an overvoltage condition exists on any cell for 32 intervals consecutively (tOVD = 4 x 32 x tDOCD = 128 x tDOCD), an overvoltage condition is recognized, and the CC FET is turned off. If an undervoltage condition exists on any cell for 32 intervals consecutively (tUVD = 4 x 32 x tDOCD = 128 x tDOCD) an undervoltage condition is recognized, the CC and DC FETs are turned off, and Sleep Mode is entered. ONE CELL-BALANCING PERIOD ONE MEASUREMENT PERIOD tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 1 2 3 4 5 1 2 3 VUV, VUV_REL, VCE, VOV, AND VBAL ARE MEASURED FOR ALL CELLS 1 2 3 4 ... tDOCD/ 32 123 CELL BALANCING IS PERFORMED ON EVENNUMBERED CELLS 5 6 4 × tDOCD 4 × tDOCD 4 × tDOCD 4 × tDOCD 4 × tDOCD 4 × tDOCD tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 tDOCD/ 32 1 2 3 4 5 1 2 3 VUV, VUV_REL, VCE, VOV, AND VBAL ARE MEASURED FOR ALL CELLS 4 × tDOCD 128 × tDOCD, PART RESPONDS TO VUV, VUV_REL, VCE, VOV, AND VBAL CONDITION Figure 5. Cell Balancing and Measurement Periods 14 tDOCD/ 32 123 CELL BALANCING IS PERFORMED ON ODDNUMBERED CELLS 32 ... ... ______________________________________________________________________________________ 5- to 10-Cell Li+ Protector with Cell Balancing V08 V07 V06 V05 V04 V03 V02 V01 TOP VIEW Package Information For the latest package outline information, go to www.maxim-ic.com/packages. 24 23 22 21 20 19 18 17 V09 25 16 V10 26 15 GND VIN 27 14 N.C. 13 OVS1 12 OVS0 11 CBS1 10 CBS0 9 CBCFG DC 28 DS2726 SNS 29 N.C. 30 CC 31 *EP + 4 5 6 7 8 SEL1 CDOCD SLEEP CSCD RDOC 3 VCC 2 SEL0 1 RSC PKP 32 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN-EP T3277+2 21-0144 V00 TQFN (7mm × 7mm) *EXPOSED PAD. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. DS2726 Pin Configuration