ONSEMI NTD78N03

NTD78N03
Power MOSFET
25 V, 78 A, Single N−Channel, DPAK
Features
• Low RDS(on)
• Optimized Gate Charge
• Pb−Free Packages are Available
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Applications
RDS(on) TYP
V(BR)DSS
• Desktop VCORE
• DC−DC Converters
• Low Side Switch
ID MAX
4.6 @ 10 V
25 V
78 A
6.5 @ 4.5 V
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
25
V
Gate−to−Source Voltage
VGS
20
V
ID
14.8
A
Continuous Drain
Current (Note 1)
TA = 25°C
Power Dissipation
(Note 1)
TA = 25°C
Continuous Drain
Current (Note 2)
TA = 25°C
PD
2.3
4
W
4
4
TA = 85°C
A
11.4
1 2
8.8
PD
1.4
W
Continuous Drain
Current (RJC)
TC = 25°C
ID
78
A
Power Dissipation
(RJC)
TC = 25°C
Pulsed Drain Current
Current Limited by Package
TC = 85°C
tp = 10 s
TA = 25°C
Drain to Source dV/dt
Operating Junction and Storage Temperature
Source Current (Body Diode)
56
PD
64
W
IDM
88
A
IDmaxPkg
32
A
dV/dt
2.0
V/ns
TJ, Tstg
−55 to
175
°C
IS
78
A
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
L = 5.0 mH, IL(pk) = 17 A, RG = 25 )
EAS
722.5
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = TBD in sq).
 Semiconductor Components Industries, LLC, 2005
1
1
3
CASE 369C
DPAK
(Bend Lead)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
2 3
CASE 369AC
3 IPAK
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
YWW
78
N03
Steady
y
St t
State
ID
TA = 25°C
February, 2005 − Rev. 0
S
11.5
YWW
78
N03
Power Dissipation
(Note 2)
TA = 85°C
N−Channel
G
1
Gate
2
Drain
3
Source
1
Gate
3
Source
2
Drain
Y
= Year
WW
= Work Week
78N03 = Device Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTD78N03/D
NTD78N03
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RJC
1.95
°C/W
C/
Junction−to−Ambient − Steady State (Note 3)
RJA
65
Junction−to−Ambient − Steady State (Note 4)
RJA
110
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
25
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
24
VGS = 0 V,
VDS = 20 V
mV/°C
TJ = 25°C
1.5
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 A
A
100
nA
3.0
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
1.0
VGS(TH)/TJ
RDS(on)
( )
gFS
1.6
−5.0
mV/°C
m
VGS = 10 V, ID = 78 A
4.6
6.0
VGS = 4.5 V, ID = 36 A
6.5
7.8
VDS = 10 V, ID = 15 A
22
S
1920
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
VGS = 0 V,
V f = 1.0
1 0 MHz,
MH
VDS = 12 V
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
420
Total Gate Charge
QG(TOT)
25.5
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
18.2
td(on)
11
VGS = 4.5 V, VDS = 20 V,
ID = 20 A
960
35
nC
2.4
5.3
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = 4.5 V, VDS = 20 V,
ID = 20 A, RG = 3.0 tf
ns
68
23
42
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Time
3.
4.
5.
6.
VSD
VGS = 0 V,
IS = 20 A
TJ = 25°C
0.83
TJ = 125°C
0.7
tRR
ta
tb
39
VGS = 0 V, dIs/dt = 100 A/s,
IS = 20 A
QRR
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2
V
ns
17.8
21
33
Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = TBD in sq).
Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
Switching characteristics are independent of operating junction temperatures.
1.0
nC
NTD78N03
100
VGS = 4 V
80
3.8 V
4.5 V
5V
3.6 V
9V
3.4 V
70
60
50
3.2 V
40
30
3V
20
TJ = 25°C
10
2.6 V
0
2
0
4
6
8
10
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.01
VGS = 10 V
0.008
TJ = 125°C
0.007
0.006
TJ = 25°C
0.005
0.004
0.003
TJ = −55°C
0.002
20
30
40
50
60
70
80
TJ = 25°C
0.01
VGS = 4.5 V
VGS = 10 V
0.005
0
55
60
65
70
75
80
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus
Drain Current and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
3
2.5
0.015
ID, DRAIN CURRENT (A)
100000
VGS = 0 V
ID = 78 A
VDS = 4.5 V
10000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
0.001
6
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.009
0
10
160
150 VDS ≥ 10 V
140
130
120
110
100
90
80
70
60
50
TJ = 125°C
40
30
TJ = 25°C
20
TJ = −55°C
10
0
0
3
1
2
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
90
2
1.5
1
TJ = 150°C
TJ = 125°C
1000
100
0.5
0
−50
−25
0
25
50
75
100
125
150
175
10
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
25
VDS = 0 V
VGS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
5000
Ciss
4000
Crss
3000
2000
Ciss
1000
Coss
0
10
Crss
5
VGS
0
VDS
5
10
15
20
25
8
VDS
15
6
VGS
4
5
2
ID = 20 A
TJ = 25°C
0
0
5
10
15
20
25
30
0
35
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 7. Capacitance Variation
80
1000
100
IS, SOURCE CURRENT (AMPS)
VDS = 20 V
ID = 20 A
VGS = 4.5 V
t, TIME (ns)
10
Q2
Q1
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
tr
tf
td(off)
td(on)
10
1
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
10 s
100
100 s
1 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
1
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
60
50
40
30
20
10
0.6
0.7
0.8
0.9
1.1
1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
1.2
Figure 10. Diode Forward Voltage versus Current
1000
10
VGS = 0 V
70 T = 25°C
J
0
0.5
1
I D, DRAIN CURRENT (AMPS)
20
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
6000
VGS, GATE−TO−SOURCE VOLTAGE (V)
NTD78N03
800
ID = 78 A
700
600
500
400
300
200
100
0
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
10
100
http://onsemi.com
4
175
NTD78N03
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 13. Diode Reverse Recovery Waveform
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1000
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
DUTY CYCLE
100
D = 0.5
0.2
0.1
0.05
0.02
0.01
10
1
P(pk)
t1
0.1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
RθJA(t) = r(t) RθJA
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TA = P(pk) RθJA(t)
0.01
1E−05
1E−04
1E−03
1E−02
1E−01
t, TIME (seconds)
1E+00
1E+01
1E+02
1E+03
Figure 14. Thermal Response − Various Duty Cycles
ORDERING INFORMATION
Package
Shipping†
NTD78N03
DPAK
75 Units/Rail
NTD78N03T4
DPAK
2500 Tape & Reel
DPAK
(Pb−Free)
2500 Tape & Reel
NTD78N03−1
DPAK Straight Lead
75 Units/Rail
NTD78N03−1G
DPAK Straight Lead
(Pb−Free)
75 Units/Rail
NTD78N03−35
DPAK−3 Straight Lead
(3.5 0.15 mm)
75 Units/Rail
NTD78N03−35G
DPAK−3 Straight Lead
(3.5 0.15 mm)
(Pb−Free)
75 Units/Rail
Order Number
NTD78N03T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
NTD78N03
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
−T−
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD78N03
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
3 PL
0.13 (0.005)
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
T
http://onsemi.com
7
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
NTD78N03
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
B
V
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
H
D
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
3 PL
0.13 (0.005) W
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
http://onsemi.com
8
For additional information, please contact your
local Sales Representative.
NTD78N03/D