16-bit, 1 MSPS PulSAR® ADC in MSOP/QFN AD7980 Preliminary Technical Data APPLICATIONS Battery-powered equipment Communications ATE Data acquisitions Medical instruments Type 18Bit 16Bit 14Bit 1 AD7680 AD7683 AD7684 AD7940 250 kSPS 0.5V TO 5V 0 TO VREF IN+ IN– 5V REF VDD VIO SDI AD7980 SCK SDO GND 1.8V TO VDD 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) CNV Figure 1. GENERAL DESCRIPTION The AD7980 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to 5.5V. Its power scales linearly with throughput. Table 1. MSOP, QFN(LFCSP)/SOT-23 14, 16 and18-Bit ADC 100 kSPS APPLICATION DIAGRAM EXAMPLE 02969-002 16-bit resolution with no missing codes Throughput: 1MSPS Low Power dissipation: 7.5 mW @ 1MSPS, 75 μW @ 10kSPS INL: ±1 LSB typ, ±2 LSB max S/(N + D): 91.5 dB @ 20 kHz THD: −101 dB @ 20 kHz Pseudo-differential analog input range 0 V to VREF with VREF between 2.5V to 5.5V Any input range and easy to drive with the ADA4841 No pipeline delay Single-supply 2.5V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Daisy-chain multiple ADCs and BUSY indicator 10-lead package: MSOP (MSOP-8 size) and QFN (LFCSP), 3 mm × 3 mm same space as SOT-23 1 MSPS AD7691 1 400500 kSPS AD76901 AD76851 AD76871 AD7694 AD79421 AD76861 AD76881 AD76931 AD79461 AD79801 ADC Driver ADA4941 ADA4841 ADA4941 ADA4841 The SPI-compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single, 3-wire bus and provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. The AD7980 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Pin-for-pin compatible. Rev Pr C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD7980 Preliminary Technical Data TABLE OF CONTENTS Specifications..................................................................................... 3 Voltage Reference Input ............................................................ 13 Timing Specifications....................................................................... 5 Power Supply............................................................................... 13 Absolute Maximum Ratings............................................................ 6 Digital Interface.......................................................................... 13 ESD Caution.................................................................................. 6 CS MODE 3-Wire, No BUSY Indicator .................................. 14 Pin Configuration and Function Descriptions............................. 7 CS Mode 3-Wire with BUSY Indicator ................................... 15 Terminology ...................................................................................... 8 CS Mode 4-Wire with BUSY Indicator ................................... 17 Circuit Information.................................................................... 10 Chain Mode, No BUSY Indicator ............................................ 18 Converter Operation.................................................................. 10 Chain Mode with BUSY Indicator........................................... 19 Typical Connection Diagram ................................................... 11 Application Hints ........................................................................... 20 Analog Input ............................................................................... 11 Layout .......................................................................................... 20 Driver Amplifier Choice............................................................ 12 Evaluating the AD7980’s Performance.................................... 20 Voltage Reference Input............................................................. 13 Outline Dimensions ....................................................................... 21 REVISION HISTORY Rev Pr C | Page 2 of 22 Preliminary Technical Data AD7980 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5V, VREF = 5V, TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error 2 , TMIN to TMAX Gain Error Temperature Drift Zero Error2, TMIN to TMAX Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Conditions Min 16 IN+ − IN− IN+ IN− fIN = 1 MHz Acquisition phase 0 −0.1 −0.1 Typ REF = 5 V REF = 2.5 V VDD = 2.5V ± 5% ±0.5 ±1 0.58 1 ±2 ±1 ±0.5 ±1 ±0.1 0 1 +VREF VREF + 0.1 +0.1 V V V dB nA +1 +2 1 250 Full-scale step Intermodulation Distortion 3 Unit Bits 60 1 See the Analog Input section 16 −1 −2 fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V Max 91.5 87.5 −103.5 −101 91.5 87.5 -105 Bits LSB 1 LSB LSB LSB LSB ppm/°C mV ppm/°C LSB MSPS ns dB dB dB dB dB dB dB LSB means least significant bit. With the 5 V input range, one LSB is 76.3 μV. See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 fIN1 = 21.4 kHz, fIN2 = 16.9 kHz, each tone at −7 dB below full-scale. 2 Rev Pr C | Page 3 of 22 AD7980 Preliminary Technical Data VDD = 2.5 V, VIO = 2.3 V to 5.5V, VREF = 5V, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation Energy per conversion TEMPERATURE RANGE 3 Specified Performance Conditions Min Typ 2.3 Max Unit 5.5 1MSPS, REF = 5 V 500 V μA VDD = 2.5 V 10 2.5 MHz ns –0.3 0.7 × VIO −1 −1 ISINK= +500 μA ISOURCE= −500 μA Specified performance Serial 16 bits Straight Binary Conversion results available immediately after completed conversion 0.4 VIO − 0.3 2.37 2.3 1.8 VDD and VIO = 2.5 V, 25°C 10 kSPS throughput 1 MSPS throughput TMIN to TMAX 0.3 × VIO VIO + 0.3 +1 +1 2.5 1 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact sales for extended temperature range. 2 Rev Pr C | Page 4 of 22 V V 2.63 5.5 5.5 V V V nA μW mW nJ/sample +85 °C 1 75 7.5 7.5 −40 V V μA μA Preliminary Technical Data AD7980 TIMING SPECIFICATIONS −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated. Table 4. 1 Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width ( CS Mode ) SCK Period ( CS Mode or Chain mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.7 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.7 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY indicator) 1 See Figure 2 and Figure 3 for load conditions. Rev Pr C | Page 5 of 22 Symbol tCONV tACQ tCYC tCNVH tSCK tSCKL tSCKH tHSDO tDSDO Min 350 250 1000 10 Typ Max 750 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 7.5 8 9 10 13 ns ns ns ns ns 10 15 15 ns ns ns ns ns ns ns ns ns ns 10 10.5 11.5 12.5 14.5 3 3 3 tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 15 0 5 5 2.5 3 15 AD7980 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+ 2 , IN−1 to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) 2 Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +7V −0.3 V to +3V +2.7V to −7V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 200°C/W (MSOP-10) 44°C/W (MSOP-10) 215°C 220°C See the Analog Input section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 500μA IOL 1.4V TO SDO 500μA 02969-003 CL 20pF IOH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev Pr C | Page 6 of 22 02973-004 tDELAY Preliminary Technical Data AD7980 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 AD7980 9 SDI IN+ 3 TOP VIEW (Not to Scale) 8 SCK 7 SDO IN– 4 GND 5 6 REF 1 VDD 2 IN+ 3 IN– 4 CNV GND 5 10 VIO AD7980 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Figure 4. 10-Lead MSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 VDD IN+ P AI 4 5 6 IN− GND CNV AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P Function Reference Input Voltage. The REF range is from 2.3 V to 5.5V. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. Power Supply. Analog Input. It is referred to in IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V to VREF. Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power Rev Pr C | Page 7 of 22 AD7980 Preliminary Technical Data TERMINOLOGY Integral Nonlinearity Error (INL) It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 12). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level ½ LSB above analog ground (38.1 μV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula ENOB = (S/[N + D]dB − 1.76)/6.02 and is expressed in bits. Noise-free-code-resolution It is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as : Noise-Free Code resolution = log2(2N/peak-to-peak noise) and is expressed in bits. Effective resolution It is calculated as : Effective resolution = log2(2N/rms input noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Dynamic Range It is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in dB. It is measured with a signal at -60dBFs to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay The measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function was applied . Rev Pr C | Page 8 of 22 Preliminary Technical Data AD7980 TYPICAL PERFORMANCE CHARACTERISTICS: VDD=2.5V, VREF=5.0V, VIO=3.3V 2 2 POSITIVE INL: +0.23 LSB NEGATIVE INL: -0.68 LSB POSITIVE DNL: +0.32 LSB NEGATIVE DNL: -0.25 LSB 1.5 1 1 0.5 0.5 DNL (LSB) INL (LSB) 1.5 0 -0.5 0 -0.5 -1 -1 -1.5 -1.5 -2 -2 0 16384 32768 49152 65536 0 16384 32768 CODE 49152 65536 CODE Figure 9. Differential Nonlinearity vs. Code Figure 6. Integral Nonlinearity vs. Code 140000 200000 128289 123672 180726 180000 120000 160000 100000 120000 COUNTS COUNTS 140000 100000 80000 60000 80000 40000 45049 60000 34629 40000 20000 20000 0 1 543 172 0 0 0 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 0 fS = 1 MSPS fIN = 20kHz SNR = 91.5dB THD = -101.0dB SFDR = 103.5dB SINAD = 91.0dB AMPLITUDE (dB of Full Scale) -60 -80 -100 -120 -140 -160 -180 0 100 200 300 5 7FF9 7FFA 7FFB 3567 7FFC 7FFD 7FFE 7FFF 0 0 0 8000 8001 8002 Figure 10. Histogram of a DC Input at the Code Transition Figure 7. Histogram of a DC Input at the Code Center -40 0 CODE IN HEX CODE IN HEX -20 5587 0 0 400 500 FREQUENCY (kHz) Figure 8. FFT Plot Rev Pr C | Page 9 of 22 AD7980 Preliminary Technical Data IN+ SWITCHES CONTROL MSB 32,768C 16,384C LSB 4C 2C C SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C MSB CONTROL LOGIC OUTPUT CODE C LSB SW– CNV IN– Figure 11. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7980 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture. The AD7980 is a successive approximation ADC based on a charge redistribution DAC. Figure 11 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. The AD7980 is capable of converting 1,000,000 samples per second (1MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes 75 μW typically, ideal for battery-powered applications. The AD7980 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7980 can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7980 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev Pr C | Page 10 of 22 Preliminary Technical Data AD7980 Transfer Functions TYPICAL CONNECTION DIAGRAM ADC CODE (STRAIGHT BINARY) The ideal transfer characteristic for the AD7980 is shown in Figure 12 and Table 7. Figure 13 shows an example of the recommended connection diagram for the AD7980 when multiple supplies are available. 111...111 111...110 111...101 000...010 000...001 000...000 –FSR –FSR + 1 LSB +FSR – 1 LSB +FSR – 1.5 LSB –FSR + 0.5 LSB ANALOG INPUT Figure 12. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR Analog Input VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 μV 0V Digital Output Code Hexa FFFF1 8001 8000 7FFF 0001 00002 1. This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). 2. This is also the code for an underranged analog input (VIN+ − VIN− below VGND). V+ REF1 2.5V 10μF2 100nF V+ 1.8V TO 5V 100nF 15Ω REF 0 TO VREF VDD VIO SDI IN+ 2.7nF V- AD7980 SCK 3- OR 4-WIRE INTERFACE5 SDO 4 IN– CNV GND 1SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10μF CERAMIC CAPACITOR (X5R). 3SEE DRIVER AMPLIFIER CHOICE SECTION. 4OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 13. Typical Application Diagram with Multiple Supplies ANALOG INPUT Figure 14 shows an equivalent circuit of the input structure of the AD7980. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more Rev Pr C | Page 11 of 22 AD7980 Preliminary Technical Data than 0.3 V because this causes these diodes to begin to forwardbias and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit, current limitation can be used to protect the part. SNRLOSS D1 f–3dB is the input bandwidth in MHz of the AD7980 (10MHz) or the cutoff frequency of the input filter, if one is used. CIN D2 N is the noise gain of the amplifier (for example, +1 in buffer configuration). 02973-026 CPIN RIN ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ where: VDD IN+ OR IN– ⎛ ⎜ 44 = 20log ⎜ ⎜ π 2 2 ⎜ 44 + f −3dB ( Ne N ) 2 ⎝ GND eN is the equivalent input noise voltage of the op amp, in nV/√Hz. Figure 14. Equivalent Analog Input Circuit The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. • For ac applications, the driver should have a THD performance commensurate with the AD7980. During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. • For multichannel multiplexed applications, the driver amplifier and the AD7980 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. When the source impedance of the driving circuit is low, the AD7980 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. ADA4841 AD8021 AD8022 OP184 AD8655 AD8605, AD8615 Table 8. Recommended Driver Amplifiers Amplifier ADA4941 DRIVER AMPLIFIER CHOICE Although the AD7980 is easy to drive, the driver amplifier needs to meet the following requirements: • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7980. The noise coming from the driver is filtered by the AD7980 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7980 is 38 μV rms, the SNR degradation due to the amplifier is Rev Pr C | Page 12 of 22 Typical Application Very low noise, low power single to Differential Very low noise, small and low power Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low noise 5 V single-supply, low power Preliminary Technical Data AD7980 VOLTAGE REFERENCE INPUT DIGITAL INTERFACE The AD7980 voltage reference input, REF, has a dynamic, input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. Though the AD7980 has a reduced number of pins, it offers flexibility in its serial interface modes. When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. POWER SUPPLY It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7980 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range. The AD7980 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. This makes the part ideal for low sampling rate (even a few Hz) and low battery-powered applications. The AD7980, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP219x. This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7980, when in chain mode, provides a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7980 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback. The BUSY indicator feature is enabled as: • In the CS mode, if CNV or SDI is low when the ADC conversion ends (Figure 18 and Figure 22). • In the chain mode, if SCK is high during the CNV rising edge (Figure 26). Rev Pr C | Page 13 of 22 AD7980 Preliminary Technical Data valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7980 is connected to an SPI compatible digital host. The connection diagram is shown in Figure 15 and the corresponding timing is given in Figure 16. CONVERT With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it will continue to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7980 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is DIGITAL HOST CNV VIO SDI AD7980 DATA IN SDO SCK CLK Figure 15. CS Mode 3-Wire, No BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL SCK 1 2 3 14 tHSDO 16 tSCKH tDSDO tEN SDO 15 D15 D14 D13 tDIS D1 Figure 16. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev Pr C | Page 14 of 22 D0 Preliminary Technical Data AD7980 edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7980 is connected to an SPI compatible digital host having an interrupt input. The connection diagram is shown in Figure 17 and the corresponding timing is given in Figure 18. If multiple AD7980s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7980 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK CONVERT VIO CNV VIO DIGITAL HOST 47kΩ SDI AD7980 DATA IN SDO SCK IRQ CLK Figure 17. CS Mode 3-Wire with BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL SCK 1 2 3 tHSDO 15 16 17 tSCKH tDSDO SDO tDIS D15 D14 D1 D0 Figure 18. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev Pr C | Page 15 of 22 AD7980 Preliminary Technical Data time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7980 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7980 can be read. CS Mode 4-Wire, No BUSY Indicator This mode is usually used when multiple AD7980s are connected to an SPI compatible digital host. A connection diagram example using two AD7980s is shown in Figure 19 and the corresponding timing is given in Figure 20. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV SDI AD7980 DIGITAL HOST CNV SDO SDI SCK AD7980 SDO SCK DATA IN CLK Figure 19. CS Mode 4-Wire, No BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL SCK 1 2 3 14 tHSDO 16 17 18 D1 D0 D15 D14 30 31 32 D1 D0 tDSDO tEN SDO 15 tSCKH D15 D14 D13 tDIS Figure 20. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev Pr C | Page 16 of 22 Preliminary Technical Data AD7980 as an interrupt signal to initiate the data readback controlled by the digital host. The AD7980 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance. CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7980 is connected to an SPI compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 21 and the corresponding timing is given in Figure 22. CS1 CONVERT With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used VIO CNV DIGITAL HOST 47kΩ SDI AD7980 DATA IN SDO SCK IRQ CLK Figure 21. CS Mode 4-Wire with BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL SCK 1 2 3 tHSDO 15 16 17 tSCKH tDSDO tDIS tEN SDO D15 D14 D1 Figure 22. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev Pr C | Page 17 of 22 D0 AD7980 Preliminary Technical Data readback. When the conversion is complete, the MSB is output onto SDO and the AD7980 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate and, consequently more AD7980s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. CHAIN MODE, NO BUSY INDICATOR This mode can be used to daisy chain multiple AD7980s on a 3wire serial interface. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7980s is shown in Figure 23 and the corresponding timing is given in Figure 24. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the BUSY indicator. In this mode, CNV is held high during the conversion phase and the subsequent data CONVERT CNV CNV SDI AD7980 AD7980 SDI SDO DIGITAL HOST A SCK DATA IN SDO B SCK CLK Figure 23. Chain Mode, No BUSY Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 14 15 tSSDISCK 16 17 18 DA15 DA14 30 31 32 D A1 DA0 tSCKH tHSDISC tEN SDOA = SDIB DA15 DA14 DA13 DA1 DA0 DB15 DB14 DB13 D B1 D B0 tHSDO tDSDO SDOB Figure 24. Chain Mode, No BUSY Indicator Serial Interface Timing Rev Pr C | Page 18 of 22 Preliminary Technical Data AD7980 subsequent data readback. When all ADCs in the chain have completed their conversions, the nearend ADC ( ADC C in Figure 25) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7980 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently more AD7980s in the chain, provided the digital host has an acceptable hold time. CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy chain multiple AD7980s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7980s is shown in Figure 25 and the corresponding timing is given in Figure 26. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the CONVERT CNV SDI AD7980 CNV CNV SDO SDI AD7980 A SCK SDI SDO DIGITAL HOST AD7980 B SCK DATA IN SDO C SCK IRQ CLK Figure 25. Chain Mode with BUSY Indicator Connection Diagram tCYC CNV = SDIA ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tSCKH 1 tHSCKCNV 2 tSSDISCK tEN SDOA = SDIB 3 4 tSCK 15 16 17 18 19 31 32 33 34 35 tSCKL tHSDISC tDSDOSDI DA15 DA14 DA13 DA1 DA0 DB15 DB14 DB13 DB1 DB0 DA15 DA14 D A1 DA0 49 DC15 DC14 DC13 DC1 DC0 DB15 DB14 D B1 DB0 DA15 DA14 tDSDOSDI tDSDOSDI SDOC 48 tDSDOSDI tHSDO tDSDO SDOB = SDIC 47 tDSDOSDI Figure 26. Chain Mode with BUSY Indicator Serial Interface Timing Rev Pr C | Page 19 of 22 DA1 D A0 AD7980 Preliminary Technical Data APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7980 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7980, with all its analog signals on the left side and all its digital signals on the right side, eases this task. AD7980 Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7980 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided At least one ground plane should be used. It could be common or split between the digital and analog section. In the latter case, the planes should be joined underneath the AD7980s. The AD7980 voltage reference input REF has a dynamic, input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connected with wide, low impedance traces. Figure 27. Example of Layout of the AD7980 (Top Layer) Finally, the power supplies VDD and VIO of the AD7980 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7980 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 27 and Figure 28. EVALUATING THE AD7980’S PERFORMANCE Other recommended layouts for the AD7980 are outlined in the documentation of the evaluation board for the AD7980 (EVAL-AD7980-CB). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev Pr C | Page 20 of 22 Figure 28. Example of Layout of the AD7980 (Bottom Layer) Preliminary Technical Data AD7980 OUTLINE DIMENSIONS 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.27 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 29.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters INDEX AREA PIN 1 INDICATOR 3.00 BSC SQ 10 1.50 BCS SQ 0.50 BSC 1 TOP VIEW (BOTTOM VIEW) 6 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP SIDE VIEW 0.30 0.23 0.18 2.48 2.38 2.23 EXPOSED PAD 0.50 0.40 0.30 5 1.74 1.64 1.49 0.05 MAX 0.02 NOM PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES 0.20 REF Figure 30. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev Pr C | Page 21 of 22 AD7980 Preliminary Technical Data Rev Pr C | Page 22 of 22 PR06392-0-9/06(PrC)