Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
ZL30462
Compact Timing Module
Data Sheet
Features
January 2005
•
Complete timing solution in a small outline
package
•
8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input
reference frequencies
•
8 kHz (frame pulse), 2.048 MHz, 8.192 MHz,
16.384 MHz, 19.44 MHz and two 155.52 MHz
(LVPECL) output clock frequencies
•
Low intrinsic jitter and wander generation
•
Automatic Holdover modes
•
Holdover and lock indication
•
Selectable operation modes
•
Accepts reference inputs from two independent
sources
•
3.3 V Supply Voltage
Ordering Information
ZL30462MCF 40 SMTDIL
0°C to +70°C
Description
The ZL30462 is a Timing Module, which functions as a
complete system clock solution for general timing
applications.
The ZL30462 has been designed around Zarlink's
Digital and Analog Phase Locked Loop (DPLL and
APLL) technology and can lock to one of two inputs
that can be derived from two independent sources.
The inputs automatically detect if one of four
frequencies is present, 8 kHz, 1.544 MHz, 2.048 MHz
or 19.44 MHz. The module has three jitter attenuated
output clocks one 19.44 MHz (CMOS) and two
155.52 MHz (LVPECL). In addition to these outputs the
module also supplies an 8 kHz frame pulse plus
2.048 MHz, 8.192 MHz and 16.384 MHz clocks.
Applications
•
SDH Add/Drop multiplexers
•
Next Gen. Digital Loop Carriers
•
ATM edge switches
•
Line cards
TVdd
TGND
OSC
Vdd
AGND
M a s te r
O s c illa to r
/C 1 6 o
C8o
O u tp u t
In te rfa c e
C irc u it
C2o
/F 1 6 o
LK1
(1 9 .4 4 M H z )
D PLL
PRI
SEC
R e fe re n c e
S e le c t
MUX
T IE
C o rre c to r
C irc u it
LK2
JA19M o
In p u t
Im p ra irm e n t
M o n ito r
RSEL
APLL
J A 1 5 5 P /N -1
C o n v e rte r
J A 1 5 5 P /N -2
C o n tro l S ta te M a c h in e
MS1
MS2
/R E S E T /T C L R
LO C K
H O LD O V E R
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30462
40
1
1
Data Sheet
20
21
Figure 2 - 40 Pin SMT DIL Top View
Pin Description Table
Pin Number
Name
Description
1
C16o
Clock 16.384 MHz (CMOS Output). This general purpose output may be used
for ST-BUS operation with a 16.384 MHz clock.
2
C8o
Clock 8.192 MHz (CMOS Output). This general purpose output may be used for
ST-BUS operation at 8.192 Mb/s.
3
C2o
Clock 2.048 MHz (CMOS Output). This general purpose output may be used for
ST-BUS operation at 2.048 Mb/s.
4
F16o
Frame Pulse ST-BUS 16.384 Mb/s (CMOS Output). This is an 8 kHz 61 ns
active low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 16.384 Mb/s.
5
LK1
(19.44MHz)
6
LK2
7
AGND1
8
NC
No Connection. This pin is unused and has no internal connection.
9
NC
No Connection. This pin is unused and has no internal connection.
10
AGND1
11
12
JA155N-2
JA155P-2
13
VDD2
Positive Power Supply. 3.3 V
14
LOCK
Lock Indicator (CMOS Output). This output goes high when the PLL is
frequency locked to the input reference.
15
JA19Mo
Link1. Connect this pin to pin 6. This 19.44 MHz signal must not be used for
external applications.
Link2. Connect this pin to pin 5.
Ground.
Ground.
JA 155-2 Clock (LVPECL Output). This differential output provides a low jitter
155.52 MHz clock.
Clock 19.44 MHz (CMOS Output). This output provides a low jitter 19.44 MHz
clock.
2
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
Pin Description Table (continued)
Pin Number
Name
Description
16
17
JA155N-1
JA155P-1
18
AGND2
19
VDD3
20
AGND1
21
TVDD
Oscillator Positive Power Supply. 3.3 V
22
TGND
Oscillator Ground.
23
OSC
Oscillator Master Clock (CMOS Output). This pin can be used to monitor the
output of the on-board master oscillator.
24
VDD1
Positive Power Supply. 3.3 V
25
PRI
Primary Reference (Input). This input is a Primary reference source for
synchronization. The module can synchronize to falling edge of the following
reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or the rising edge of 19.44 MHz.
This pin is selected when a logic 0 is applied to the RSel input pin. This pin is
internally pulled up to VDD.
26
SEC
Secondary Reference (Input). This input is a Secondary reference source for
synchronization. The module can synchronize to falling edge of the following
reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or the rising edge of 19.44 MHz.
This pin is selected when a logic 1 is applied to the RSel input pin. This pin is
internally pulled up to VDD.
27
IC
28
TCLR
TIE Circuit Reset (Input). A high to low transition at this input initiates phase
realignment between the input reference and the generated output clocks. This
pin is internally pulled to GND.
29
RESET
Reset (Input). Logic 0 will forces the module into a reset state. This pin must be
held to logic 0 for a minimum of 1µs to reset the module properly. The module
must be reset after power-up.
30
AGND1
Ground.
31
IC
Internal Connection. Do not connect to this pin.
32
NC
No Connection. This pin is unused and has no internal connection.
33
NC
No Connection. This pin is unused and has no internal connection.
34
RSEL
Reference Source Select (Input). A logic low selects the PRI (primary) reference
source as the input reference signal and a logic high selects the SEC (secondary)
input. This pin is internally pulled down to GND. See Table 1.
35
MS1
Mode/Control Select 1 (Input). This input, in conjunction with MS2, determines
the state (Normal, Holdover or Freerun) of operation. See Table 2.
36
MS2
Mode/Control Select 2 (Input). This input, in conjunction with MS1, determines
the state (Normal, Holdover or Freerun) of operation. See Table 2.
37
NC
38
HOLDOVER
39
NC
JA 155-1 Clock (LVPECL Output). This differential output provides a low jitter
155.52 MHz clock.
Ground.
Positive Power Supply.3.3 V
Ground.
Internal Connection. Do not connect to this pin.
No Connection. This pin is unused and has no internal connection.
HOLDOVER (CMOS Output). This output goes to a logic high whenever the PLL
goes into holdover mode.
No Connection. This pin is unused and has no internal connection.
3
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
Pin Description Table (continued)
Pin Number
Name
40
VDD
1.0
Description
Positive Power Supply. 3.3 V
Functional Description
The ZL30462 offers a complete timing solution in a 1.2” x 1” module package. The module comprises three main
components, a DPLL which performs the main operational functions, an APLL which provides three low jitter output
clocks and an on-board master oscillator. Figure 1 shows a functional block diagram of the module, which is
described in the following sections.
1.1
Reference Select MUX Circuit
The ZL30462 accepts two simultaneous reference input signals which can be derived from independent sources.
Both reference inputs will automatically accept one of four frequencies, 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz. The 8 kHz, 1.544 MHz and 2.048 MHz input clocks are all triggered on the falling edge and the
19.44 MHz is triggered on the rising edge. The primary reference (PRI) signal or the secondary reference (SEC)
signal can be selected by simply using the RSEL pin, see Table 1.
RSEL
Input Reference
0
PRI
1
SEC
Table 1 - Input Reference Selection
1.2
Time Interval Error (TIE) Corrector Circuit
When the ZL30462 finishes locking to a reference an arbitrary phase difference will remain between its output
clocks and its reference; this phase difference is part of the normal operation of the ZL30462. If so desired, the
output clocks can be brought into phase alignment with the PLL reference by using the TCLR control pin.
Using TCLR
If the ZL30462 is locked to a reference, then the output clocks can be brought into phase alignment with the PLL
reference by using the TCLR control pin according to the procedure below:
•
Wait until the ZL30462 LOCK indicator is high, indicating that it is locked
•
Pull TCLR low
•
Hold TCLR low for 250 µs for 1.544 MHz, 2.048 MHz or 19.44 MHz, or 10 sec for 8 kHz (input frequency).
•
Pull TCLR high
This sequence re-initiates the ZL30462 locking procedure; the LOCK indicator will go low 5 sec after TCLR is pulled
low and will remain low for 10 sec.
1.3
Core PLL
The most critical element of the ZL30462 is the Core PLL. This generates a phase-locked clock filters wander and
suppresses input phase transients.The Core PLL supports three mandatory modes of operation: Free-run, Normal
(Locked) and Holdover.
Each of these modes places specific requirements on the building blocks of the Core PLL.
4
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
•
In Free-run Mode, the Core PLL locks to the 20 MHz Master Clock Oscillator (OSC). The stability of the
generated clock remains the same as the stability of the Master Clock Oscillator.
•
In Normal Mode, the Core PLL locks to one of the input reference clocks. Both inputs provide preprocessed
phase data to the Core PLL including detection of reference clock quality. This preprocessing reduces the
load on the Core PLL and improves quality of the generated clock.
•
In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The
Core PLL enters Holdover mode if the selected reference input is lost, or under external hardware control.
Table 2 shows how each of these modes can be selected via the external hardware pins MS1 and MS2.
MS2
MS1
Mode of Operation
0
0
Normal mode
0
1
Holdover mode
1
0
FreeRun mode
1
1
Reserved
Table 2 - Operating Modes
Within the DPLL there are a number of key components, which include a Phase Detector, Limiter, Loop Filter,
Digitally Controlled Oscillator, Clock Synthersizer and Lock Indicator.
1.3.1
Phase Detector
The Phase Detector compares the virtual reference signal from the TIE Corrector circuit, with its internal input
frequency select circuit and provides an error signal corresponding to the phase difference between the two. This
error signal is passed to the Limiter circuit.
1.3.2
Limiter
The Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input
transient conditions with a maximum output phase slope of 41 ns per 1.326 ms.
1.3.3
Loop Filter
In Normal mode, the clocks generated by the ZL30462 are phase-locked to the input reference signal. The DPLL
Loop Filter is similar to a first order low pass filter with a 1.5 Hz cutoff frequency for all four reference frequency
selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the wander transfer requirements
in ETS 300 011 and AT&T TR62411 are met.
1.3.4
Digitally Controlled Oscillator (DCO)
The DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a
corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the
ZL30462.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (30 ms to 60 ms) frequency the DCO
was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSC 20 MHz source.
5
Zarlink Semiconductor Inc.
ZL30462
1.3.5
Data Sheet
Clock Synthesizer
The output of the DCO is connected to the Clock Synthesizer that generates the output clocks and frame pulse.
•
C2o: 2.048 MHz clock with nominal 50% duty cycle
•
C8o: 8.192 MHz clock with nominal 50% duty cycle
•
C16o: 16.384 MHz clock with nominal 50% duty cycle
•
F16o: 8 kHz frequency, with 61 ns wide, logic low frame pulse
In addition to the above, LK1 also generates a 19.44 MHz clock, which is linked externally to LK2. This clock drives
the APLL stage which generates the low jitter 19.44 MHz and 155.52 MHz clock outputs (see Section 1.4).
LK1:
1.3.6
19.44 MHz clock with nominal 50% duty cycle
Lock Indicator (LOCK)
The ZL30462 is considered locked (LOCK=1) when the residual phase movement after declaring locked condition
does not exceed 20 ns; as required by standard wander generation MTIE and TDEV tests. To ensure the integrity of
the LOCK status indication, the ZL30462 holds the LOCK pin low for a minimum of 10 sec.
1.4
Jitter Attenuator
The ZL30462 output driver circuit provides two LVPECL jitter attenuated outputs at 155.52 MHz and one CMOS
output at 19.44 MHz.
There are no external components or adjustments required to support this part of the circuit, as the loop filter and
additional power supply decoupling circuitry has been built into the module.
The on-board loop filter has been optimized to ensure the quality of the jitter attenuated output. But to maintain the
quality of these outputs it is extremely important that they are terminated correctly and the track impedance is
50 Ohms. Failure to do so will affect the modules performance will affect the quality of these clocks. Figure 3 shows
one method of terminating one of the LVPECL outputs, further termination information can be found in the ZL30462
Applications Note.
The input to the APLL stage can be isolated from the DPLL, by removing the link connection between LK1 (pin 5)
and LK2 (pin 6), this may be useful for product verification or test purposes.
6
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
Vcc
Output Driver
127Ω
127Ω
Ζ = 50Ω
LVPECL
Driver
LVPECL
Receiver
Ζ = 50Ω
82.5Ω
82.5Ω
Note : Vcc = +3.3V
Figure 3 - LVPECL Output Termination Circuit
1.5
Input Impairment Monitor
This circuit monitors both the input reference signals and reports their status automatically to the DPLL. This block
automatically enables the Holdover Mode (Auto-Holdover) when the selected reference is outside the AutoHoldover capture range. (See AC Electrical Characteristics - Performance). This includes a complete loss of
incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the
DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the
ZL30462 is based on the incoming signal 30 ms minimum to 60 ms prior to entering the Holdover Mode. The
amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g., <±0.01 ppm,
relative to the master oscillator frequency). Consequently, the phase delay between the input and output after
switching back to Normal Mode is preserved.
1.6
Control State Machine
The ZL30462 Control State Machine supporting the three mandatory clock modes required by any Network
Element that operates in a synchronous network. The simplified version of this state machine is shown in Figure 4
and includes the mandatory states: Free-run, Normal and Holdover. These states are complemented by two
additional states: Reset and Auto Holdover, which are critical to the ZL30462 operation under the changing external
conditions.
These clock modes determine the behavior of a Network Element to the unforeseen changes in the network
synchronization hierarchy. Requirements for clock modes are defined in the international standards e.g.: G.812,
G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators.
Figure 4 also shows how the control input pins - RSEL, MS1, MS2 and RESET interact with the Control State
Machine.
7
Zarlink Semiconductor Inc.
ZL30462
MS2, MS1 == 01 or
RSEL change
______
RESET == 1
Reset
Ref: OK &
MS2, MS1 == 00
{Auto}
Data Sheet
Normal
(Locked)
00
MS2, MS1 != 10
FreeRun
10
Holdover
01
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: OK --> Fail
&
MS2, MS1 == 00
{Auto}
RSEL change
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Auto
Holdover
MS2, MS1 == 10 forces
unconditional return from
any state to FreeRun
Notes:
== : equal
!= : not equal
&= : AND operation
0 --> 1 : transition from 0 to 1
{Auto} : Automatic transition
{Manual} : Manual transition
Auto Holdover: Automatic Holdover
{AHRD} : Automatic Holdover
{MHR} : Manual Holdover
State
MS2, MS1
Figure 4 - ZL30462 State Machine
1.6.1
Reset State
In this state, the DPLL clocks are stopped and all functions are initialized. The Reset state is entered by pulling the
RESET pin to logic 0 for a minimum of 1 µs. When the RESET pin is pulled back to logic 1, internal logic starts a
625 µs initialization process before switching into the Free-run state (MS2, MS1 = 10). It is recommended that a
module reset is performed immediately after power up, to ensure the ZL30462 is set to a know state.
The RESET function would normally be under the control of the system or host controller, usually in the form of a
microprocessor or FPGA. Alternatively, Figure 5 shows how to connect a simple hardware reset circuit to the
ZL30462.
Vdd
ZL30462
R
10k
______
RESET
Rp
1k
C
10nF
Figure 5 - Simple Reset Circuit
8
Zarlink Semiconductor Inc.
ZL30462
1.6.2
Data Sheet
Free-Run State
The Free-run state is entered when synchronization to the network is not required or is not possible. Typically this
occurs during installation, repairs or when a Network Element operates as a master node in an isolated network. In
the Free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30462
Master Crystal Oscillator. When powering up the equipment, it is recommended that the module has at least 2
hours to stabilize after the equipment has reached its normal operating temperature.
1.6.3
Normal State (Locked State)
The Normal State is entered when Normal mode is selected and a good quality reference clock is available. The
ZL30462 automatically detects the frequency of the reference clock (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz)
and sets the LOCK status pin to logic 1 after acquiring synchronization. In the Normal state all generated clocks
(C2o, C8o, C16o, JA19Mo, JA155P/N-1 and JA155P/N-2) and frame pulse (F16o) are derived from network timing.
To guarantee uninterrupted synchronization, the ZL30462 continuously monitors the quality of both input reference
clocks. This dual architecture enables quick replacement of a poor or failed reference and minimizes the time spent
in other states.
During this state the ZL30462 can tolerate a 17 ppm/s frequency change (on the active input) without generating an
alarm or changing state.
1.6.4
Holdover State
The Holdover State is typically entered for short durations while network synchronization is temporarily disrupted. In
Holdover Mode, the ZL30462 generated clocks are not locked to an external reference signal, but these outputs are
based on stored coefficients in memory. These coefficients are determined while the module is in Normal State for
at least 10 minute after the modules stabilization period.”
The initial frequency offset of the ZL30462’s DPLL in Holdover Mode is ±1x10-10. Once the ZL30462 has
transitioned into Holdover Mode, holdover stability is determined by the stability of the 20 MHz Master Clock
Oscillator (OSC pin), which is a ±20 ppm crystal oscillator.
1.6.5
Auto Holdover State
The Auto Holdover state is a transitional state that the ZL30462 enters automatically when the active reference fails
unexpectedly. When the ZL30462 detects loss of reference it waits in Auto Holdover state until the failed reference
recovers. The HOLDOVER status pin may be used to alert the system controller about the failure and in response
the controller may switch to the secondary reference clock. The HOLDOVER pin indicates when you are in either
Auto Holdover and Holdover states.
If the selected input fails (or becomes invalid for any reason) the ZL30462 will transition into Auto-Holdover. If the
system controller then elects to switch to the other input and that input is also invalid, then the ZL30462 will remain
in Auto Holdover until that input becomes valid. This is an internal protection system, to ensure that the module
does not use an invalid reference.
If the ZL30462 is reset at any time (e.g., during power-up) and mode select pins are trying to force the module to
lock to an invalid input (MS1, MS2 == 00) the module will transition into Auto Holdover and the HOLDOVER pin will
be asserted. Because the reset function clears the ZL30462’s memory, then there will be no holdover history. In this
case, even though the output status pin is showing that the module is in Holdover, the output clock accuracy will
default to that of Freerun mode.
So to summarise the above, in a typical Network Element application, the ZL30462 will typically operate in Normal
mode (MS2, MS1 == 00) generating synchronous clocks. The State Machine is designed to perform some
transitions automatically, leaving other, less time dependent tasks to the system controller. The state machine
includes two stimulus signals which are critical to automatic operation: “OK --> FAIL” and “FAIL --> OK” that
represent loss (and recovery) of the reference signal or its drift by more than ±30000 ppm. Their transitions force
9
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
the DPLL to move into and out of the Auto Holdover state. The ZL30462 State Machine may also be driven by
controlling the mode select pins MS2, MS1. To avoid network synchronization problems, the State Machine has
built-in basic protection that does not allow switching the DPLL into a state where it cannot operate correctly e.g., it
is not possible to force the DPLL into Normal mode when all references are lost.
2.0
Applications
This section details how to control and monitor the hardware pins of the ZL30462 and general power supply
decoupling information. More detailed application information can be found in the ZL30462 Applications Note.
2.1
ZL30462 Mode Switching - Examples
The ZL30462 is designed to transition from one mode to the other driven by the internal State Machine or by
manual control. The following examples present a couple of typical scenarios of how the ZL30462 can be employed
in network synchronization equipment (e.g., timing modules, line cards or stand alone synchronizers).
2.1.1
System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL
The Free-run to Holdover to Normal transition represents a sequence of steps that will most likely occur during a
new system installation or scheduled maintenance of timing cards. The process starts from the RESET state and
then transitions to Free-run when the device is being initialized. At the end of this process the ZL30462 should be
switched into Normal mode (with MS2, MS1 set to 00) instead of Holdover mode. If the reference clock is available,
the ZL30462 will transition briefly into Holdover state to acquire synchronization and switch automatically to Normal
state. If the reference clock is not available the ZL30462 will stay in Holdover state indefinitely. Whilst in Holdover
state, the DPLL will continue generating clocks with the same accuracy as in the Free-run mode, waiting for a valid
reference clock. When the system is connected to the network (or timing card switched to a valid reference) this will
enable the DPLL to start the synchronization process. After acquiring lock, the ZL30462 will automatically switch
from Holdover state to Normal state without system intervention. This transition to the Normal state will be flagged
by the LOCK status pin.
MS2, MS1 == 01 or
RSEL change
______
RESET == 1
Reset
Ref: OK &
MS2, MS1 == 00
{Auto}
Normal
(Locked)
00
MS2, MS1 != 10
FreeRun
10
Holdover
01
RSEL change
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: OK --> Fail
&
MS2, MS1 == 00
{Auto}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Auto
Holdover
MS2, MS1 == 10 forces
unconditional return from
any state to FreeRun
Figure 6 - Transition from Free-run to Normal mode
10
Zarlink Semiconductor Inc.
ZL30462
2.1.2
Data Sheet
Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL
The Normal to Auto-Holdover to Normal transition will usually happen when the Network Element loses its single
reference clock unexpectedly or when it has two references but switching to the secondary reference is not a
desirable option.
The sequence starts with the unexpected failure of a reference signal shown as transition OK --> FAIL in Figure 7
at a time when ZL30462 operates in Normal mode. This failure is detected at the active input based on the following
FAIL criteria:
•
Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm
(±3%).
•
Phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock.
After detecting any of these anomalies on a reference clock the Control State Machine will force the DPLL to
automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0 and HOLDOVER = 1.
MS2, MS1 == 01 or
RSEL change
______
RESET == 1
Reset
Ref: OK &
MS2, MS1 == 00
{Auto}
Normal
(Locked)
00
MS2, MS1 != 10
FreeRun
10
Holdover
01
RSEL change
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: OK --> Fail
&
MS2, MS1 == 00
{Auto}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Auto
Holdover
Automatic return to Normal: AHDR=0
or
Manual return to Normal: AHRD=1 & MHR 0--> 1
MS2, MS1 == 10 forces
unconditional return from
any state to FreeRun
Figure 7 - Automatic entry into Auto Holdover State and recovery into Normal mode
The ZL30462 will automatically return to the Normal state after the reference signal recovers from failure. This
transition is shown on the state diagram as a FAIL --> OK change. This change becomes effective when the
reference is restored and there have been no phase hits detected for at least 64 clock cycles.
This transition from Auto Holdover to Normal state is performed as “hitless” reference switching.
2.1.3
Dual Reference Operation: NORMAL --> AUTO HOLDOVER --> HOLDOVER --> NORMAL
The Normal to Auto-Holdover to Holdover to Normal sequence represents the most likely operation of ZL30462 in
Network Equipment.
The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of
reference. The failure conditions triggering this transition were described in Section 2.1.2. When in the Auto
Holdover state, the ZL30462 can return to Normal state automatically if the lost reference is restored. If the
reference clock failure persists for a period of time that exceeds the system design limit, the system control
processor may initiate a reference switch. If the secondary reference is available the ZL30462 will briefly switch into
Holdover state and then transition to Normal state.
11
Zarlink Semiconductor Inc.
ZL30462
MS2, MS1 == 01 or
RSEL change
______
RESET == 1
Reset
Ref: OK &
MS2, MS1 == 00
{Auto}
Data Sheet
Normal
(Locked)
00
MS2, MS1 != 10
FreeRun
10
Holdover
01
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: OK --> Fail
&
MS2, MS1 == 00
{Auto}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Auto
Holdover
RSEL change
AHRD=0
(automatic return enabled)
MS2, MS1 == 10 forces
unconditional return from
any state to FreeRun
Figure 8 - Entry into Auto Holdover state and recovery into Normal mode by switching
references
The new reference clock will most likely have a different phase but it may also have a different fractional frequency
offset. To lock to a new reference with a different frequency, the DPLL will step gradually towards the new
frequency. The frequency slope will be limited to less than 2.0 ppm/sec.
2.1.4
Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL
The Normal to Holdover to Normal sequence switching can be performed at any time. An example of this could be
during routine maintenance or an upgrade of equipment, where the active input references is going to be affected.
So, changing the input reference under controlled conditions should avoid any unnecessary chances of generating
a phase hit.
MS2, MS1 == 01 or
RSEL change
______
RESET == 1
Reset
Ref: OK &
MS2, MS1 == 00
{Auto}
Normal
(Locked)
00
MS2, MS1 != 10
FreeRun
10
Holdover
01
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: OK --> Fail
&
MS2, MS1 == 00
{Auto}
RSEL change
MS2, MS1 == 10 forces
unconditional return from
any state to FreeRun
Figure 9 - Manual Reference Switching
12
Zarlink Semiconductor Inc.
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Auto
Holdover
ZL30462
Data Sheet
Two types of transitions are possible:
•
Semi-automatic transition, which involves changing the RSEL input to select the other reference clock,
without changing the mode select inputs MS2, MS1 = 00 (Normal mode). This forces ZL30462 to
momentarily transition through the Holdover state and automatically return to Normal state after
synchronizing to the other reference clock.
•
Manual transition, which involves switching into Holdover mode (MS2, MS1 = 01), changing references with
RSEL, and manual return to the Normal mode (MS2, MS1 = 00).
In both cases, the change of references provides “hitless” switching.
2.2
Power Supply Decoupling
Figure 10 shows the recommended power supply decoupling requirements of the ZL30462. The ZL30462 does
have a level of internal decoupling components built in to the module, but to ensure optimum performance these
external components are required.
L1
3.3V
L1 & L2 : 10µH
C2 & C5 : 10µF
C1, C3, C4, C6 - C9 : 100nF
TVdd
C1
C2
C3
TGnd
L2
C4
Vdd
C5
C6
AGnd1
Vdd1
C7
ZL30462
AGnd1
Vdd2
C8
AGnd1
Vdd3
C9
AGnd2
Figure 10 - Power Supply Decoupling
13
Zarlink Semiconductor Inc.
ZL30462
3.0
Characteristics
3.1
AC and DC Electrical Characteristics
Data Sheet
Absolute Maximum Ratings*
Parameter
1
Symbol
Min.
Max.
Units
VDD
TVDD
-0.3
-0.3
5.0
5.0
V
V
Supply Voltages
2
Input Voltage
VIN
-0.05
VDD+0.5
* Voltages are with respect to ground (GND) unless otherwise stated.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
V
Recommended Operating Conditions*
Parameter
1
Supply Voltages
2
Operating Temperature
Symbol
Min
Typ.
Max.
Units
VDD
TVDD
3.0
3.3
3.6
V
TA
0
25
70
ºC
Typ.
Max.
Units
Test Conditions
* Voltages are with respect to ground (GND) unless otherwise stated.
DC Electrical Characteristics*
Characteristics
Symbol
Min.
1
Supply Current
IDD
325
450
mA
Output unloaded
2
Supply Current
TIDD
5
10
mA
Output unloaded
3
CMOS: High-level input voltage
VIH
0.7VDD
4
CMOS: Low-level input voltage
VIL
0
5
CMOS: Input leakage current
IIL
6
CMOS: High-level output
voltage
VOH
7
CMOS: Low-level output
voltage
VOL
8
LVPECL: Differential output
voltage
|VOD|
9
LVPECL: High-level output
voltage
VOH
10
LVPECL: Low-level output
voltage
VOL
11
LVPECL: Output rise and fall
times
TRF
V
0.3VDD
V
15
µA
VI=VDD or GND
V
IOH = 8mA
0.4
V
IOL = 8mA
720
mVp
ZT=100 Ohms
VDD-0.9
V
ZT=100 Ohms
VDD-1.5
V
2.4
480
250
600
300
* Voltages are with respect to ground (GND) unless otherwise stated.
Note 1: Rise and fall times are measured at 20% and 80% levels.
14
Zarlink Semiconductor Inc.
700
ps
Note 1
ZL30462
Data Sheet
AC Electrical Characteristics*
Parameter
Symbol
Min.
Max.
Units
Test Conditions
FA
-20
20
ppm
Note 2
1
Freerun Mode accuracy
2
Holdover Mode accuracy
FA-0.01
FA+0.01
ppm
Note 3
3
Lock range
FA-104
FA+104
ppm
Note 4
4
Wander Generation
5
WGEN
ITU-T G.813 Option1
Wander Transfer
WTR
ITU-T G.813 Option1
6
Phase response to input signal
interruptions
PTT
ITU-T G.813 Option1
7
Phase Transients
PT
ITU-T G.813 Option1
8
Holdover Entry Phase Transients
HEPT
ITU-T G.813 Option1
9
Lock Time
30
LT
s
* Voltages are with respect to ground (GND) unless otherwise stated.
Note 2:
The Freerun accuracy is directly related to the accuracy of the master oscillator.
Note 3:
The DPLL Holdover accuracy is also affected by the holdover stability of the master oscillator.
Note 4:
This figure is offset by the accuracy of the master oscillator.
AC Electrical Characteristics* - Timing Parameter Measurements - CMOS Voltage Levels*
Characteristics
Symbol
Typical
Units
VT
0.5VDD
V
1
Threshold voltage
2
Rise and fall threshold voltage High
VHM
0.7VDD
V
3
Rise and fall threshold voltage Low
VLM
0.3VDD
V
* Voltages are with respect to ground (GND) unless otherwise stated.
Timing Reference Points
V HM
VT
V LM
All Signals
T IF, TOF
T IR, TOR
Figure 11 - Timing Parameters Measurement Voltage Levels
15
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
AC Electrical Characteristics - Input Phase Alignment
Characteristics
Symbol
Min.
1
8 kHz ref. pulse width high
tR8H
100
2
8 kHz ref. input to F16o delay
tR8D
43
3
1.544 MHz ref. pulse width high
tR1.5H
100
4
1.544 MHz ref. input to F16o delay
tR1.5D
360
5
2.048 MHz ref. pulse width high
tR2H
100
6
2.048 MHz ref. input to F16o delay
tR2D
252
7
19.44 MHz ref. pulse width high
tR19H
23
8
19.44 MHz ref. input to F16o delay
tR19D
30
9
Reference input rise and fall time
tIR, tIF
t R8H
Max.
Units
Test Conditions
ns
61
ns
ns
393
ns
ns
288
ns
ns
51
ns
10
ns
t R8D
PRI/SEC
8kHz
VT
tR1.5H
tc = 125µs
tR1.5D
PRI/SEC
1.544MHz
VT
t R2H
tc = 647.67ns
t R2D
PRI/SEC
2.048MHz
VT
tc = 488.28ns
t R19H
t R19D
PRI/SEC
19.44MHz
VT
tc = 51.44ns
VT
/F16o
tc = 125µs
Figure 12 - Input to Output Timing (Normal Mode)
16
Zarlink Semiconductor Inc.
ZL30462
Data Sheet
AC Electrical Characteristics - Input Control Signals
Characteristics
Symbol
Min.
Max.
Units
1
Input Controls Setup Time
tS
100
ns
2
Input Controls Hold Time
tH
100
ns
/F16o
Test Conditions
VT
tS
tH
MS1, MS2,
RSEL,
VT
Figure 13 - Input Control Signal Setup and Hold Time
AC Electrical Characteristics - Outputs Timing
Characteristics
Symbol
Min.
Max.
Units
1
F16o to JA19Mo delay
tJ19D
-35
-25
ns
4
F16o to C16o delay
tC16D
-35
-25
ns
5
F16o to C8o delay
tC8D
-35
-25
ns
6
F16o to C2o delay
tC2D
-35
-25
ns
17
Zarlink Semiconductor Inc.
Test Conditions
ZL30462
/F16o
Data Sheet
VT
tc = 125µs
t J19D
JA19Mo
VT
tc = 51.44ns
t C16D
/C16o
VT
tc = 61.035ns
t C8D
C8o
VT
tc = 122.07ns
t C2D
C2o
VT
tc = 488.28ns
Figure 14 - Output Timing
18
Zarlink Semiconductor Inc.
ZL30462
3.2
Data Sheet
Performance Characteristics
Performance Characteristics: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance*
Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation
Requirements
Interface
Jitter
Measurement
Filter
Equivalent
limit in
time
domain
Limit in
UI
ZL30462 Jitter Generation
Performance
TYP
Units
Notes
JA155P/N Clock Output
1
OC-12
622.08 Mbit/s
12 kHz to 5 MHz
(Category II)
0.1 UIPP
161
24.2
psP-P
1.905
psRMS
JA19Mo Clock Output
2
OC-3
155.54 Mbit/s
3
65 kHz to 1.3 MHz
12 kHz to 1.3 MHz
(Category II)
964
0.15 UIPP
0.1 UIPP
643
283.1
psP-P
22.89
psRMS
209.4
psP-P
16.49
psRMS
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Measured Output Jitter - G.732, G.735 to G.739 conformance*
ITU-T G.732, G.735, G.736, G.737, G.738, G739
Jitter Generation Requirements
Interface
Jitter
Measurement
Filter
Equivalent
limit in
time
domain
Limit in
UI
ZL30462 Jitter Generation
Performance
TYP
Units
Notes
C16o, C8 and C2 Clock Outputs
1
E1
2048 kbits/s
20 Hz to 100 kHz
0.05 UIPP
24.4
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
19
Zarlink Semiconductor Inc.
1.26
nsP-P
ZL30462
Data Sheet
Performance Characteristics: Measured Output Jitter - G.813 conformance - Option 1
ITU-T G.813
Jitter Generation Requirements
Jitter
Measurement
Filter
Interface
Limit in
UI
ZL30462 Jitter Generation Performance
Equivalent
limit in
time
domain
TYP
Units
Notes
JA155P/N Clock Output
1
STM-4
622.08 Mbit/s
250 kHz to
5 MHz
0.1 UIPP
161
11.9
psP-P
0.94
psRMS
JA19Mo Clock Output
2
STM-1
155.54 Mbit/s
65 kHz to
1.3 MHz
0.1 UIPP
643
283.1
psP-P
22.89
psRMS
C16o, C8o and C2o Clock Output
3
E1
2048 kbit/s
20 Hz to
100 kHz
0.05 UIPP
24.4
1.26
nsP-P
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Measured Output Jitter - G.813 conformance - Option 2
ITU-T G.813
Jitter Generation Requirements
Interface
Jitter
Measurement
Filter
ZL30462 Jitter Generation
Performance
Equivalent
limit in
time
domain
Limit in
UI
TYP
Units
JA155P/N Clock Output
1
STM-4
622.08 Mbit/s
12 kHz to 5 MHz
161
0.1 UIPP
24.2
psP-P
1.905
psRMS
JA19Mo Clock Output
2
STM-1
155.54 Mbit/s
65 kHz to 1.3 MHz
643
0.1 UIPP
20
Zarlink Semiconductor Inc.
283.1
psP-P
22.89
psRMS
Notes
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
1
ACN
---
DATE
15 Oct 03
APPRD.
Previous package codes
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE