PD - 95662
IRFP17N50LPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
VDSS RDS(on) typ. Trr typ. ID
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
0.28Ω
500V
170ns 16A
• Motor Control applications
• Lead-Free
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise
TO-247AC
immunity.
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
Max.
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
11
IDM
64
Pulsed Drain Current
c
PD @TC = 25°C Power Dissipation
VGS
Linear Derating Factor
Gate-to-Source Voltage
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
Units
16
e
A
220
W
1.8
± 30
W/°C
V
13
-55 to + 150
V/ns
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
10lb in (1.1N m)
x
Mounting torque, 6-32 or M3 screw
x
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
16
ISM
(Body Diode)
Pulsed Source Current
–––
–––
64
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.5
V
p-n junction diode.
TJ = 25°C, IS = 16A, VGS = 0V
trr
Reverse Recovery Time
–––
170
250
ns
TJ = 25°C, IF = 16A
–––
220
330
710
Qrr
c
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
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MOSFET symbol
A
–––
470
–––
810 1210
–––
7.3
11
showing the
integral reverse
TJ = 125°C, di/dt = 100A/µs
nC
TJ = 25°C, IS = 16A, VGS = 0V
TJ = 125°C, di/dt = 100A/µs
A
f
f
f
f
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
1
07/30/04
IRFP17N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
500
–––
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.60
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
0.28
0.32
VGS(th)
Gate Threshold Voltage
3.0
–––
5.0
IDSS
Drain-to-Source Leakage Current
IGSS
RG
–––
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, I D = 1mA
Ω
V
VGS = 10V, ID = 9.9A
f
VDS = VGS, ID = 250µA
–––
–––
50
µA
VDS = 500V, VGS = 0V
–––
–––
2.0
mA
VDS = 400V, VGS = 0V, TJ = 125°C
nA
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
1.4
–––
VGS = 30V
VGS = -30V
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Qg
Forward Transconductance
11
Total Gate Charge
Qgs
Gate-to-Source Charge
Qgd
Gate-to-Drain ("Miller") Charge
td(on)
S
Conditions
–––
–––
VDS = 50V, ID = 9.9A
–––
–––
130
–––
–––
33
–––
–––
59
VGS = 10V, See Fig. 7 & 15
Turn-On Delay Time
–––
21
–––
VDD = 250V
tr
Rise Time
–––
51
–––
td(off)
Turn-Off Delay Time
–––
50
–––
RG = 7.5Ω
tf
Fall Time
–––
28
–––
VGS = 10V, See Fig. 14a & 14b
Ciss
Input Capacitance
–––
2760
–––
VGS = 0V
Coss
Output Capacitance
–––
325
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
37
–––
Coss
Output Capacitance
–––
3690
–––
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
84
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
159
–––
VGS = 0V,VDS = 0V to 400V
Coss eff. (ER)
Effective Output Capacitance
–––
120
–––
ID = 16A
nC
ns
pF
VDS = 400V
f
ID = 16A
f
g
(Energy Related)
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
Typ.
–––
Max.
390
IAR
Avalanche Current
–––
16
A
EAR
Repetitive Avalanche Energy
–––
22
mJ
Units
c
d
c
Units
mJ
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case
Parameter
–––
0.56
RθCS
Case-to-Sink, Flat, Greased Surface
0.50
–––
RθJA
Junction-to-Ambient
–––
62
°C/W
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting TJ = 25°C, L = 3.0mH, RG = 25Ω,
IAS = 16A. (See Figure 12).
ISD = 16A, di/dt ≤ 347A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS.
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IRFP17N50LPbF
10
100
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
1
5.0V
0.1
10
5.0V
1
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.01
0.1
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
I D , Drain-to-Source Current (A)
100
TJ = 150 ° C
10
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
9.0
10.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 1. Typical Output Characteristics
0.1
4.0
1
VDS, Drain-to-Source Voltage (V)
3.0
ID = 16A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60
80 100 120 140 160
TJ , Junction Temperature ( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFP17N50LPbF
20
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Energy (µJ)
C, Capacitance(pF)
15
Coss = Cds + Cgd
10000
Ciss
1000
10
Coss
5
100
Crss
0
10
1
10
100
0
1000
VDS, Drain-to-Source Voltage (V)
ISD , Reverse Drain Current (A)
VGS , Gate-to-Source Voltage (V)
12
8
4
30
60
90
120
QG , Total Gate Charge (nC)
Fig 7. Typical Gate Charge Vs.
Gate-to-Source Voltage
4
400
500
600
100
V DS= 400V
V DS= 250V
V DS= 100V
0
300
Fig 6. Typ. Output Capacitance
Stored Energy vs. VDS
ID = 16A
16
0
200
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
20
100
150
TJ = 150 ° C
10
TJ = 25 ° C
1
0.1
0.2
V GS = 0 V
0.6
0.9
1.3
1.6
VSD ,Source-to-Drain Voltage (V)
Fig 8. Typical Source-Drain Diode
Forward Voltage
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IRFP17N50LPbF
20
V GS
16
ID , Drain Current (A)
RD
VDS
RG
12
D.U.T.
+
- VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
8
Fig 10a. Switching Time Test Circuit
4
VDS
90%
0
25
50
75
100
125
150
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response(Z thJC )
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
PDM
0.01
t1
t2
0.001
0.00001
Notes:
1. Duty factor D =t 1 / t 2
2. Peak TJ = P DM x ZthJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
EAS , Single Pulse Avalanche Energy (mJ)
IRFP17N50LPbF
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ID , Drain Current (A)
100
10us
10
100us
1ms
1
0.1
10ms
TC = 25 °C
TJ = 150 °C
Single Pulse
10
100
1000
800
ID
7A
10A
BOTTOM 16A
TOP
640
480
320
160
0
10000
25
50
75
100
125
150
Starting T J , Junction Temperature ( ° C)
VDS , Drain-to-Source Voltage (V)
Fig 13. Maximum Avalanche Energy
vs. Drain Current
Fig 12. Maximum Safe Operating
Area
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
tp
0.01Ω
A
I AS
Fig 14a. Unclamped Inductive Test Circuit
Fig 14b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 15a. Gate Charge Test Circuit
6
Charge
Fig 15b. Basic Gate Charge Waveform
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IRFP17N50LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 16. For N-Channel HEXFET® Power MOSFETs
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7
IRFP17N50LPbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30
WITH AS SEMBLY
LOT CODE 5657
ASSEMBLED ON WW 35, 2000
IN THE ASSEMBLY LINE "H"
Note: "P" in assembly line
position indicates "Lead-Free"
PART NUMBER
INT ERNATIONAL
RECTIF IER
LOGO
IRFPE30
56
AS SEMBLY
LOT CODE
035H
57
DATE CODE
YEAR 0 = 2000
WEEK 35
LINE H
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.07/04
8
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