19-2175; Rev 2; 4/10 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Ultrasound 37 38 39 40 41 42 43 44 45 46 47 48 REFN REFP REFIN REFOUT D9A/B D8A/B D7A/B D6A/B D5A/B D4A/B D3A/B D2A/B Pin Configuration COM VDD 1 36 D1A/B 2 35 GND INA+ 3 34 4 33 D0A/B OGND OVDD INAVDD GND INB- 5 32 6 31 8 29 INB+ GND VDD 9 28 10 CLK 12 MAX1185 7 30 19 20 21 22 PD OE N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 25 N.C. 24 18 SLEEP 23 17 OVDD OGND A/B 26 27 EP 11 T/B Video Application MAX1185ECM/V+ -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin-Compatible Versions table at end of data sheet. 16 Instrumentation 48 TQFP-EP* 48 TQFP-EP* 15 Multichannel IF Sampling -40°C to +85°C -40°C to +85°C VDD I/Q Channel Digitization MAX1185ECM GND High Resolution Imaging PIN-PACKAGE MAX1185ECM+ 14 Applications TEMP RANGE PART 13 The MAX1185 features parallel, multiplexed, CMOScompatible three-state outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1185 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible, nonmultiplexed. high-speed versions of the MAX1185 are also available. Please refer to the MAX1180 data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, the MAX1183 data sheet for 40Msps, and the MAX1184 data sheet for 20Msps. Ordering Information VDD An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. o Single 3V Operation o Excellent Dynamic Performance: 59.5dB SNR at fIN = 7.5MHz 74dB SFDR at fIN = 7.5MHz o Low Power: 35mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) o 0.02dB Gain and 0.25° Phase Matching o Wide ±1Vp-p Differential Analog Input Voltage Range o 400MHz, -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o Single 10-Bit Bus for Multiplexed, Digital Outputs o User-Selectable Output Format—Two’s Complement or Offset Binary o 48-Pin TQFP Package with Exposed Paddle For Improved Thermal Dissipation COM The MAX1185 is a 3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband trackand-hold (T/H) inputs, driving two pipelined, nine-stage ADCs. The MAX1185 is optimized for low-power, high dynamic performance applications in imaging, instrumentation, and digital communication applications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 105mW while delivering a typical signal-tonoise ratio (SNR) of 59.5dB at an input frequency of 7.5MHz and a sampling rate of 20Msps. Digital outputs A and B are updated alternating on the rising (CHA) and falling (CHB) edge of the clock. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1185 features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods. Features 48 TQFP-EP NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A "+" SIGN. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX1185 General Description MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND............................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A/B–D0A/B, A/B to OGND .......................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP-EP (derate 30.4mW/°C above +70°C)............................................................2430mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) Lead(Pb)-free..............................................................+260°C Containing lead(Pb) ....................................................+240°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1.5 LSB DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL fIN = 7.5MHz ±0.5 Differential Nonlinearity DNL fIN = 7.5MHz, no missing codes guaranteed ±0.25 ±1.0 LSB Offset Error < ±1 ±1.9 % FS Gain Error 0 ±2 % FS ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCM Input Resistance RIN Input Capacitance CIN Differential or single-ended inputs Switched capacitor load ±1.0 V VDD / 2 ± 0.5 V 100 kΩ 5 pF CONVERSION RATE Maximum Clock Frequency fCLK Data Latency 20 MHz CHA 5 CHB 5.5 Clock cycles DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio (Note 3) SNR Signal-to-Noise and Distortion (Note 3) SINAD Spurious-Free Dynamic Range (Note 3) SFDR 2 fINA or B = 7.5MHz, TA = +25°C 57.3 fINA or B = 12MHz fINA or B = 7.5MHz, TA = +25°C 59.4 57 fINA or B = 12MHz fINA or B = 7.5MHz, TA = +25°C fINA or B = 12MHz 59.5 59.4 59.2 64 74 72 _______________________________________________________________________________________ dB dB dBc Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL Total Harmonic Distortion (First 4 Harmonics) (Note 3) THD Third-Harmonic Distortion (Note 3) HD3 Intermodulation Distortion IMD Small-Signal Bandwidth Full-Power Bandwidth FPBW CONDITIONS MIN TYP MAX -64 fINA or B = 7.5MHz, TA = +25°C -72 fINA or B = 12MHz -71 UNITS dBc fINA or B = 7.5MHz -74 fINA or B = 12MHz -72 fINA or B = 11.9852MHz at -6.5dBFS, fINA or B = 12.8934MHz at -6.5dBFS (Note 4) -76 dBc Input at -20dBFS, differential inputs 500 MHz Input at -0.5dBFS, differential inputs 400 MHz dBc Aperture Delay tAD 1 ns Aperture Jitter tAJ 2 psRMS 2 ns Overdrive Recovery Time For 1.5x full-scale input ±1 % ±0.25 Degrees 0.2 LSBRMS REFOUT 2.048 ±3% V TCREF 60 ppm/°C Load Regulation 1.25 mV/mA BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Voltage VREFIN 2.048 V Differential Gain Differential Phase Output Noise INA+ = INA- = INB+ = INB- = COM INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Positive Reference Output Voltage VREFP 2.012 V Negative Reference Output Voltage VREFN 0.988 V Differential Reference Output Voltage Range ∆VREF REFIN Resistance RREFIN ∆VREF = VREFP - VREFN 0.95 1.024 > 50 1.10 V MΩ _______________________________________________________________________________________ 3 MAX1185 ELECTRICAL CHARACTERISTICS (continued) MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL CONDITIONS MIN TYP MAX UNITS ISOURCE 5 mA ISINK -250 µA ISOURCE 250 µA ISINK -5 mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance RREFP, RREFN Measured between REFP and COM, and REFN and COM Differential Reference Input Voltage ∆VREF ∆VREF = VREFP - VREFN COM Input Voltage 4 kΩ 1.024 ±10% V VCOM VDD / 2 ±10% V REFP Input Voltage VREFP VCOM + ∆VREF / 2 V REFN Input Voltage VREFN VCOM ∆VREF / 2 V DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold VIH PD, OE, SLEEP, T/B ✕ 0.8 VDD V 0.8 ✕ OVDD CLK Input Low Threshold ✕ VIL Input Leakage Input Capacitance V 0.2 ✕ OVDD PD, OE, SLEEP, T/B Input Hysteresis 0.2 VDD VHYST 0.1 V IIH VIH = OVDD or VDD (CLK) ±5 IIL VIL = 0 ±5 CIN 5 µA pF DIGITAL OUTPUTS (D0A/B–D9A/B, A/B) Output-Voltage Low VOL ISINK = -200µA Output-Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD 4 0.2 OVDD - 0.2 V V ±10 5 _______________________________________________________________________________________ µA pF Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.7 3.0 3.6 V 1.7 V POWER REQUIREMENTS Analog Supply Voltage Range VDD Output Supply Voltage Range OVDD Analog Supply Current Output Supply Current IVDD IOVDD 2.5 3.6 Operating, fINA or B = 7.5MHz at -0.5dBFS 35 50 Sleep mode 2.8 Shutdown, clock idle, PD = OE = OVDD 1 Operating, CL = 15pF, fINA or B = 7.5MHz at -0.5dBFS 9 Sleep mode Shutdown, clock idle, PD = OE = OVDD Power Dissipation PDISS PSRR 100 10 Operating, fINA or B = 7.5MHz at -0.5dBFS 105 150 Sleep mode 8.4 3 µA mA 2 Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio 15 mA 45 µA mW µW Offset ±0.2 mV/V Gain ±0.1 %/V TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid tDOA Figure 3 (Note 5) 5 8 ns CLK Fall to CHB Output Data Valid tDOB Figure 3 (Note 5) 5 8 ns Clock Rise/Fall to A/B Rise/Fall Time tDA/B 6 ns Output Enable Time tENABLE Figure 4 10 ns Output Disable Time tDISABLE Figure 4 CLK Pulse Width High tCH Figure 3, clock period: 50ns 1.5 25 ± 7.5 ns CLK Pulse Width Low tCL Figure 3, clock period: 50ns 25 ± 7.5 ns Wake-Up Time tWAKE Wake-up from sleep mode (Note 6) 0.51 Wake-up from shutdown (Note 6) 1.5 ns µs CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 7.5MHz at -0.5dBFS -70 Gain Matching fINA or B = 7.5MHz at -0.5dBFS 0.02 Phase Matching fINA or B = 7.5MHz at -0.5dBFS 0.25 dB ±0.2 dB Degrees Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization. Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale input voltage range. Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down. _______________________________________________________________________________________ 5 MAX1185 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -40 -50 HD3 -70 HD2 -50 -60 HD3 -30 -50 -90 -90 -100 -100 3 4 5 6 7 8 9 3 4 5 6 7 8 9 10 0 3 4 5 6 7 8 9 TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY HD3 -60 -70 fCLK = 20.0005678MHz fIN1 = 11.9852035MHz fIN2 = 12.8934324MHz AIN = -6.5dBFS -10 -20 -30 60 CHB SNR (dB) -40 fIN2 -50 -80 -90 -90 1 2 3 4 5 6 7 8 9 CHA 57 IM3 IM3 IM2 56 55 -100 -100 58 -60 -80 0 10 1 2 3 4 5 6 7 8 9 0 10 5 10 15 20 25 30 35 40 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY -64 THD (dBc) 58 CHA 56 -68 CHB -72 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 40 45 72 68 CHA 64 -80 54 45 CHB -76 5 76 CHA CHB SFDR (dBc) 60 80 MAX1185 toc08 -60 MAX1185 toc07 62 10 59 -70 HD2 fIN1 61 MAX1185 toc05 0 MAX1185 toc04 CHB -50 0 2 FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -40 0 1 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -30 2 ANALOG INPUT FREQUENCY (MHz) fCLK = 20.0005678MHz fINA = 7.5343935MHz fINB = 11.9852035MHz AINA = -0.471dBFS -20 1 ANALOG INPUT FREQUENCY (MHz) 0 -10 0 10 HD2 -80 -90 2 HD3 -60 -70 HD2 CHA -40 -100 1 fCLK = 20.0005678MHz fINA = 7.5343935MHz fINB = 11.9852035MHz AINA = -0.489dBFS -20 -80 0 AMPLITUDE (dB) -40 -70 -80 6 -30 0 -10 MAX1185 toc03 -20 CHB MAX1185 toc06 -60 fCLK = 20.0005678MHz fINA = 5.9742906MHz fINB = 7.5243935MHz AINA = -0.462dBFS MAX1185 toc09 -30 0 -10 AMPLITUDE (dB) AMPLITUDE (dB) -20 CHA AMPLITUDE (dB) fCLK = 20.0005678MHz fINA = 5.9742906MHz fINB = 7.5343935MHz AINA = -0.525dBFS MAX1185 toc01 0 -10 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1185 toc02 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) SINAD (dB) MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs 60 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 40 45 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 40 45 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs VIN = 100mVP-P 4 -2 55 SNR (dB) 0 0 -2 -4 -4 -6 -6 -8 10 100 1000 40 35 1 10 100 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER (fIN = 7.53MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 7.53MHz) -60 40 -80 0 85 SFDR (dBc) THD (dBc) -75 -4 80 -70 45 -8 90 -65 50 -12 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 7.53MHz) MAX1185 toc14 MAX1185 toc13 -55 55 -16 ANALOG INPUT POWER (dBFS) ANALOG INPUT FREQUENCY (MHz) 60 -20 1000 ANALOG INPUT FREQUENCY (MHz) 65 50 45 -8 1 SINAD (dB) 60 2 GAIN (dB) GAIN (dB) 2 65 MAX1185 toc12 4 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 7.53MHz) MAX1185 toc11 6 MAX1185 toc10 6 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1185 toc15 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED 75 70 65 60 -85 35 -16 -12 -8 -4 55 -20 0 INTEGRAL NONLINEARITY (BEST END-POINT FIT) -4 0 0 -0.1 -0.1 -0.2 -0.2 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -4 0.3 0 0.2 CHB 0.1 0 -0.1 CHA -0.2 -0.3 -0.3 -8 GAIN ERROR vs. TEMPERATURE GAIN ERROR (%FS) DNL (LSB) 0 -12 0.4 MAX1185 toc17 0.2 -16 ANALOG INPUT POWER (dBFS) 0.1 0 -20 DIFFERENTIAL NONLINEARITY 0.1 INL (LSB) -8 0.3 MAX1185 toc16 0.2 -12 ANALOG INPUT POWER (dBFS) ANALOG INPUT POWER (dBFS) 0.3 -16 MAX1185 toc18 -20 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1185 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 20MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) 37 MAX1185 toc21 38 MAX1185 toc20 0.1 36 0 -0.1 CHB -0.2 -0.3 36 IVDD (mA) IVDD (mA) OFFSET ERROR (%FS) 38 MAX1185 toc19 0.2 ANALOG SUPPLY CURRENT vs. TEMPERATURE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE 34 35 32 34 30 CHA 28 33 -0.4 -15 10 35 60 2.70 85 2.85 3.00 3.15 3.30 3.45 -15 10 35 TEMPERATURE (°C) ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE SNR/SINAD, -THD/SFDR vs. CLOCK DUTY CYCLE INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 0.15 0.10 0.05 74 THD 68 SNR 62 56 3.00 3.15 3.30 3.45 2.0040 2.0000 35 3.60 2.0060 40 45 50 55 60 65 70 2.70 2.85 3.00 CLOCK DUTY CYCLE (%) VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.010 64,515 63,000 56,000 COUNTS VREOUT (V) 49,000 2.006 42,000 35,000 28,000 2.002 21,000 1.998 14,000 7,000 1.994 0 -40 -15 10 35 TEMPERATURE (°C) 60 3.30 OUTPUT NOISE HISTOGRAM (DC INPUT) 70,000 MAX1185 toc25 2.014 3.15 VDD (V) MAX1185 toc26 2.85 2.0080 2.0020 SINAD 50 0 2.0100 85 MAX1185 toc24 fINA/B = 7.53MHz SFDR MAX1185 toc23 0.20 80 VREFOUT (V) MAX1185 toc22 OE = PD = OVDD 8 60 VDD (V) 0.25 2.70 -40 3.60 TEMPERATURE (°C) SNR/SINAD, -THD/SFDR (dB, dBc) -40 IVDD (µA) MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs 85 0 869 N-2 N-1 N 152 0 N+1 N+2 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 3.45 3.60 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs PIN NAME 1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor. FUNCTION 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog supply accepts a 2.7V to 3.6V input range. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. 5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. 8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. 9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary. 18 SLEEP 19 PD Power-Down Input. High: Power-down mode. Low: Normal operation. 20 OE Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. 21–29 N.C. Do not connect. 30 A/B A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be present on the output. A/B follows the external clock signal with typically 6ns delay. 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. Output driver supply accepts a 1.7V to 3.6V input range. 35 D0A/B Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects channel A or channel B data. 36 D1A/B Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or channel B data. 37 D2A/B Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or channel B data. 38 D3A/B Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or channel B data. 39 D4A/B Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or channel B data. 40 D5A/B Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or channel B data. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. _______________________________________________________________________________________ 9 MAX1185 Pin Description Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185 Pin Description (continued) PIN NAME FUNCTION 41 D6A/B Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or channel B data. 42 D7A/B Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A or channel B data. 43 D8A/B Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A or channel B data. 44 D9A/B Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects channel A or channel B data. 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor. 47 REFP Positive Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 48 REFN Negative Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. — EP Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Exposed Paddle. Connect to analog ground. Detailed Description The MAX1185 uses a nine-stage, fully-differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. 1.5-bit (2-comparator) flash ADCs convert the held input voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. Both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. CHA data is updated on the rising edge (five clock cycles later) and CHB data is updated on the falling edge (5.5 clock cycles later) of the clock signal. The A/B indicator follows the clock signal with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated. 10 Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1185 to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA- as well as INB+ and INB- and set the common-mode voltage to midsupply (VDD / 2) for optimum performance. ______________________________________________________________________________________ Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Σ T/H FLASH ADC x2 VIN VOUT Σ T/H FLASH ADC DAC 1.5 BITS x2 MAX1185 VIN VOUT DAC 1.5 BITS 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 STAGE 1 DIGITAL CORRECTION LOGIC T/H STAGE 2 STAGE 8 STAGE 9 DIGITAL CORRECTION LOGIC T/H 10 10 VINB VINA OUTPUT MULTIPLEXER 10 D0A/B–D9A/B Figure 1. Pipelined Architecture—Stage Blocks COM INTERNAL BIAS S2a S5a S3a C1a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b S3b C1b S5b S2b INTERNAL BIAS COM INTERNAL BIAS COM HOLD CLK HOLD TRACK TRACK S5a S2a INTERNAL NONOVERLAPPING CLOCK SIGNALS S3a C1a S4a INB+ OUT C2a S4c MAX1185 S1 OUT INBS4b C2b S3b C1b S2b INTERNAL BIAS S5b COM Figure 2. MAX1185 T/H Amplifiers ______________________________________________________________________________________ 11 MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Analog Inputs and Reference Configurations The full-scale range of the MAX1185 is determined by the internally generated voltage difference between REFP (VDD / 2 + VREFIN / 4) and REFN (VDD / 2 - VREFIN / 4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD / 2), and REFN are internally buffered low-impedance outputs. The MAX1185 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a > 10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a > 10kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate, external reference sources. Clock Input (CLK) The MAX1185’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNRdB = 20 x log10 (1 / [2π x fIN x tAJ]) where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. 12 The MAX1185 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics. System Timing Requirements Figure 3 shows the relationship between clock and analog input, A/B indicator, and the resulting CHA/CHB data output. CHA and CHB data are sampled on the rising edge of the clock signal. Following the rising edge of the 5th clock cycles, the digitized value of the original CHA sample is presented at the output, followed one half-clock cycle later by the digitized value of the original CHB sample. A channel selection signal (A/B indicator) allows the user to determine which output data represents which input channel. With A/B = 1, digitized data from CHA is present at the output and with A/B = 0 digitized data from CHB is present. Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE), Channel Selection (A/B) All digital outputs, D0A/B–D9A/B (CHA or CHB data) and A/B are TTL/CMOS logic-compatible. The output coding can be chosen to be either offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A/B–D9A/B should be kept as low as possible (< 15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1185, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1185, small-series resistors (e.g., 100Ω) may be added to the digital output paths close to the MAX1185. Figure 4 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid. Power-Down (PD) and Sleep (SLEEP) Modes The MAX1185 offers two power-save modes—sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power-down. Pulling OE high forces the digital outputs into a high-impedance state. ______________________________________________________________________________________ Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185 5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB) CHA CHB tCLK tCL tCH CLK tDOB A/B tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB D0B D1A D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B tDA/B D0A/B-D9A/B Figure 3. Timing Diagram for Multiplexed Outputs the amplifiers. The user may select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. OE tENABLE OUTPUT D0A/B–D9A/B HIGH IMPEDANCE tDISABLE VALID DATA HIGH IMPEDANCE Figure 4. Output Timing Diagram Applications Information Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD / 2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers that follows Using Transformer Coupling An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1185 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1185 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. ______________________________________________________________________________________ 13 MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Table 1. MAX1185 Output Codes For Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY T/B = 0 TWO’S COMPLEMENT T/B = 1 VREF x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111 VREF x 1/512 + 1 LSB 10 0000 0001 00 0000 0001 0 Bipolar Zero 10 0000 0000 00 0000 0000 - VREF x 1/512 - 1 LSB 01 1111 1111 11 1111 1111 -VREF x 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001 - FULL SCALE 00 0000 0000 10 0000 0000 -VREF x 512/512 *VREF = VREFP - VREFN Single-Ended AC-Coupled Input Signal Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Typical QAM Demodulation Application The most frequently used modulation technique for digital communications applications is probably the Quadrature Amplitude Modulation (QAM). Typically found in spreadspectrum based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 degree phaseshifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into it’s I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual matched 3.3V, 10-bit ADC MAX1185 and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1185, the mixed down-signal components may be filtered by matched analog filters, such as Nyquist or Pulse-Shaping filters. These remove any unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference. 14 Grounding, Bypassing, and Board Layout The MAX1185 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC’s package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channelto-channel crosstalk. Keep all signal lines short and free of 90 degree turns. ______________________________________________________________________________________ Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185 +5V 0.1µF LOWPASS FILTER INA+ MAX4108 RIS0 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V 600Ω 600Ω 300Ω COM 0.1µF +5V +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INA- MAX4108 RIS0 50Ω 300Ω CIN 22pF 0.1µF -5V 300Ω 300Ω +5V 600Ω MAX1185 0.1µF LOWPASS FILTER INB+ MAX4108 RIS0 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V 600Ω 600Ω 300Ω 0.1µF +5V +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INB- MAX4108 RIS0 50Ω 300Ω -5V CIN 22pF 0.1µF 300Ω 300Ω 600Ω Figure 5. Typical Application for Single-Ended-to-Differential Conversion ______________________________________________________________________________________ 15 MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs 25Ω INA+ 22pF 0.1µF 1 VIN T1 5 2 N.C. 6 3 4 COM 2.2µF 0.1µF MINICIRCUITS TT1–6 25Ω INA22pF MAX1185 25Ω INB+ 22pF 0.1µF 1 VIN N.C. T1 6 2 5 3 4 2.2µF 0.1µF MINICIRCUITS TT1–6 25Ω INB22pF Figure 6. Transformer-Coupled Input Drive Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1185 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. 16 Dynamic Parameter Definitions Aperture Jitter Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS ______________________________________________________________________________________ Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1185 REFP VIN 0.1µF 1kΩ RISO 50Ω INA+ MAX4108 100Ω CIN 22pF 1kΩ COM REFN 0.1µF RISO 50Ω INA- 100Ω CIN 22pF REFP VIN 0.1µF MAX1185 1kΩ RISO 50Ω INB+ MAX4108 100Ω CIN 22pF 1kΩ REFN 0.1µF RISO 50Ω INB- 100Ω CIN 22pF Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-Bits): SNRdB[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. ______________________________________________________________________________________ 17 MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX2451 INA+ INA- A/B 0° 90° MAX1185 INB+ INB- DOWNCONVERTER ÷8 DSP POST PROCESSING CHA AND CHB DATA ALTERNATINGLY AVAILABLE ON 10-BIT, MULTIPLEXED OUTPUT BUS Figure 8. Typical QAM Application, Using the MAX1185 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: CLK ⎛ ⎞ V2 2 + V3 2 + V4 2 + V5 2 ⎟ ⎜ THD = 20 × log10 ⎜ ⎟ V1 ⎝ ⎠ ANALOG INPUT tAD where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. tAJ SAMPLED DATA (T/H) Spurious-Free Dynamic Range (SFDR) T/H TRACK HOLD TRACK SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) Figure 9. T/H Aperture Timing 18 The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are backed off by 6.5dB from full scale. ______________________________________________________________________________________ Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs VDD OGND OVDD GND INA+ PIPELINE ADC T/H DEC A/B MUX INA- 10 CONTROL CLK INB+ PIPELINE ADC T/H OUTPUT DRIVERS DEC 10 D0A/B–D9A/B OE INB- REFERENCE MAX1185 T/B PD SLEEP REFOUT REFN COM REFP REFIN Pin-Compatible Versions PART RESOLUTION (Bits) SPEED GRADE (Msps) OUTPUT BUS MAX1190 10 120 Full duplex MAX1180 10 105 Full duplex MAX1181 10 80 Full duplex MAX1182 10 65 Full duplex MAX1183 10 40 Full duplex MAX1186 10 40 Half duplex MAX1184 10 20 Full duplex MAX1185 10 20 Half duplex MAX1198 8 100 Full duplex MAX1197 8 60 Full duplex MAX1196 8 40 Half duplex MAX1195 8 40 Full duplex ______________________________________________________________________________________ 19 MAX1185 Functional Diagram MAX1185 Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 20 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFP-EP C48E-7 21-0065 ______________________________________________________________________________________ Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs REVISION NUMBER REVISION DATE 2 4/10 DESCRIPTION Added automotive qualified part to Ordering Information PAGES CHANGED 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX1185 Revision History