ONSEMI NUD3048MT1

NUD3048
FET Switch
100 V, 800 mW, N−Channel, TSOP−6
The NUD3048 provides a single device solution for a number of
applications requiring a low power, high voltage, FET switch. The
package includes a gate resistor and gate to source zener clamp. This
switch can accommodate a wide range of input voltages, making it
compatible with most current logic levels. Its 100 V rating makes it
compatible with 48 V telecom applications.
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MARKING
DIAGRAM
6
Features
•
•
•
•
•
6
100 V Rating On Gate 2
Integrated 100 k Rg Option
Integrated ESD Diode Protection
Low Threshold Voltage
Pb−Free Package is Available
1
JW7 MG
G
1
JW7 = Specific Device Code
M = Month Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Typical Applications
•
•
•
•
•
TSOP−6
CASE 318G
STYLE 9
FET Switch
Inverter
Level Shifter
Inrush Limiter
Relay Driver
ORDERING INFORMATION
Device
NUD3048MT1
NUD3048MT1G
Drain
2, 4, 5
Package
Shipping†
TSOP−6
3000 / Tape & Reel
TSOP−6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
6
100 kW
Gate 2
1
Gate 1
3
Source
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 5
1
Publication Order Number:
NUD3048/D
NUD3048
MAXIMUM RATINGS
Symbol
Value
Unit
VDSS
Drain to Source Voltage – Continuous
Rating
100
V
VG1SS
Gate to Source Voltage – Continuous @ 1.0 mA
15
V
ID
Drain Current – Continuous (TA =25_C) (Note 1)
(Note 2)
0.7
1.2
A
PD
Power Dissipation (TA =25_C) (Note 1)
(Note 2)
0.66
1.56
W
VG2SS
Gate Resistor to Source Voltage – Continuous
100
V
TJmax
Maximum Junction Temperature
150
°C
RqJA
Thermal Impedance (Junction−to−Ambient) (Note 1)
Thermal Impedance (Junction−to−Ambient) (Note 2)
190
80
°C/W
ESD
Human Body Model (HBM) Class 2
Machine Model Class A
According to EIA/JESD22/A114 Specification
2000
160
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (TJ =25_C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
IDSS
−
20
100
mA
IGSS
IGSS
−
−
3.0
6.0
10
20
VGS
1.3
1.7
2.0
V
Drain to Source Resistance (VGS = 4.5 V, ID = 100 mA)
RDS(on)
−
0.65
0.82
W
Drain to Source Resistance (VGS = 10 V, ID = 100 mA)
RDS(on)
−
0.6
0.72
W
Input Capacitance (VDS = 5.0 V, VGS = 0 V, f = 10 kHz)
Ciss
−
135
−
pF
Output Capacitance (VDS = 5.0 V, VGS = 0 V, f = 10 kHz)
Coss
−
75
−
pF
Transfer Capacitance (VDS = 5.0 V, VGS = 0 V, f = 10 kHz)
Crss
−
26
−
pF
Gate Resistor
RG
75
100
125
kW
Gate Zener Breakdown Voltage (IZ = 1.0 mA) (Note 3)
Gate Zener Breakdown Voltage (IZ = 3.0 mA) (Note 4)
VZ
15
100
17
115
−
−
V
OFF CHARACTERISTICS
Drain to Source Leakage Current (VDS = 80 V, VGS = 0 V)
mA
Gate Body Leakage Current
(VGS =10 V, VDS = 0 V)
(VGS = 10 V, VDS = 0 V, TJ = 125°C)
ON CHARACTERISTICS
Gate Threshold Voltage (ID = 1.0 mA)
DYNAMIC CHARACTERISTICS
GATE BIAS CHARACTERISTICS
1.
2.
3.
4.
Min pad, 1 oz. Cu.
1 inch pad, 1 oz Cu.
Measured from gate 1 to source.
Measured from gate 2 to source.
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2
NUD3048
0.5
0.70
VGS = 2.0 V
VGS = 3.0 V
VGS = 5.0 V
0.3
0.2
RDS(on) (W)
VDS(on) (V)
0.4
VGS = 7.0 V
0.65
VGS = 4.5 V
0.60
VGS = 10 V
0.1
VGS = 10 V
0
0
0.1
0.2
0.3
0.4
0.55
0
0.5
0.05 0.1
IDS (A)
Figure 2. VDS(on) Variation with IDS and
Gate Voltage
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
ID (A)
Figure 3. On Resistance Variation with
Drain Current and Gate Voltage
1.4
2.0
1.8
1.2
1.6
1.4
IGS (mA)
VGS = 4.5 V
0.8
VGS = 10 V
0.6
1.2
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0
−50
0
50
100
0.0
−10
150
−8
−6
−4
−2
0
2
4
6
8
RDS(on) VARIATION WITH TEMPERATURE
VGS (V)
Figure 4. Variation of RDS(on) with
Temperature and Gate Voltage at ID = 100 mA
Figure 5. Gate Leakage Current Variation
with Gate Voltage
7.40E−05
LEAKAGE CURRENT IDSS
RDS(on)
1
7.20E−05
7.00E−05
IDSS
6.80E−05
6.60E−05
6.40E−05
6.20E−05
6.00E−05
−40.0 −20.0
0.0
20.0
40.0
60.0
80.0 100.0 120.0
JUNCTION TEMPERATURE
Figure 6. Variation of Leakage Current IDSS (A)
with VGS = 0 V and VDS = 100 V
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3
10
NUD3048
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
D
6
HE
1
5
4
2
3
E
b
DIM
A
A1
b
c
D
E
e
L
HE
q
e
q
c
A
0.05 (0.002)
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.014
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
SOLDERING FOOTPRINT*
2.4
0.094
1.9
0.075
0.95
0.037
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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NUD3048/D