White Electronic Designs WSF41632-22XX PRELIMINARY* 128KX32 SRAM & 512Kx32 FLASH MIXED MODULE FEATURES Access times of 25ns (SRAM) and 120ns (FLASH) Packaging • 66 pin, PGA Type, 1.385" square HIP, hermetic ceramic HIP (Package 402) Built-in decoupling caps and multiple ground pins for low noise operation Weight - 13 grams typical FLASH MEMORY FEATURES • 68 lead, hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2). Package to be developed. 100,000 erase/program cycles minimum Sector architecture • 8 equal size sectors of 64KBytes each • Any combination of sectors can be concurrently erased. Also supports full chip erase 128Kx32 SRAM 512Kx32 5V Flash 5V programming; 5V ± 10% supply Organized as 128Kx32 of SRAM and 512Kx32 of Flash Memory with common data bus Embedded erase and program algorithms Hardware write protection Low power CMOS Commercial, industrial and military temperature ranges Page program operation and internal program control time. TTL compatible inputs and outputs Note: For programming information refer to flash programming 4M5 application note. * This product is under development, is not qualified or characterized and is subject to change without notice. PIN CONFIGURATION FOR WSF41632-22H2X Pin Description D0-31 A0-18 SWE#1-4 SCS# OE# VCC GND NC FWE#1-4 FCS Top View 1 12 23 34 45 56 I/O8 FWE2# I/O15 I/O24 VCC I/O31 I/O9 SWE2# I/O14 I/O25 SWE4# I/O30 I/O10 GND I/O13 I/O26 FWE4# I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE# A12 A4 A1 A11 A9 A17 SWE1# A5 A2 A0 A15 FWE1# A13 A6 A3 A18 VCC I/O7 A8 FWE3# I/O23 I/O0 FCS# I/O6 I/O16 SWE3# I/O22 I/O1 SCS# I/O5 I/O17 GND I/O21 I/O4 I/O18 I/O3 I/O2 11 22 33 Block Diagram FWE 1 # SWE 1 # FWE 2 # SWE 2 # FWE 3 # SWE 3 # FWE 4 # SWE 4 # OE# A 0-18 SCS# FCS# 128K x 8 Flash 128K x 8 Flash 128K x 8 Flash 128K x 8 Flash 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 I/O20 I/O19 44 Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select 55 66 White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 2 – PIN CONFIGURATION FOR WSF41632-22G2TX Pin Description D0-31 A0-18 SWE#1-4 SCS# OE# VCC GND NC FWE#1-4 FCS VCC A10 A9 A8 A7 FWE1# A6 SWE4# GND SWE3# A5 A4 A3 A2 A1 A0 NC Top View 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 10 60 I/O16 I/O1 11 59 I/O17 I/O2 12 58 I/O18 I/O3 13 57 I/O19 I/O4 14 56 I/O20 I/O5 15 55 I/O21 I/O6 16 54 I/O22 I/O7 17 53 I/O23 GND 18 52 GND I/O8 19 51 I/O24 I/O9 20 50 I/O25 I/O10 21 49 I/O26 I/O11 22 48 I/O27 I/O12 23 47 I/O28 I/O13 24 46 I/O29 I/O14 25 45 I/O30 I/O15 26 44 I/O31 Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select SWE1# SCS# NC FWE4# FWE3# FWE2# NC SWE2# OE# FCS# A16 A15 A14 A13 A12 A11 VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Block Diagram FWE 1 # SWE 1 # FWE 2 # SWE 2 # FWE 3 # SWE 3 # FWE 4 # SWE 4 # OE# A 0-18 SCS# FCS# 128K x 8 Flash 128K x 8 Flash 128K x 8 Flash 128K x 8 Flash 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 0.940" The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC Min -55 -65 -0.5 -0.5 SRAM TRUTH TABLE Max +125 +150 7.0 150 7.0 Unit °C °C V °C V SCS# H L L L OE# X L H X SWE# X H H L Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active NOTE: 1. FCS# must remain high when SCS# is low. Parameter Flash Data Retention 20 years Flash Endurance (write/erase cycles) CAPACITANCE 100,000 min Ta = +25°C NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Parameter OE# capacitance F/S WE1-4# capacitance F/S CS# capacitance D0-31 capacitance A0-16 capacitance RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 -0.5 Max 5.5 VCC + 0.3 +0.8 Unit V V V Symbol COE CWE CCS CI/O CAD Conditions Max Unit VIN = 0 V, f = 1.0 MHz 80 pF VIN = 0 V, f = 1.0 MHz 30 pF VIN = 0 V, f = 1.0 MHz 50 pF VIN = 0 V, f = 1.0 MHz 30 pF VIN = 0 V, f = 1.0 MHz 80 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 32 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash VCC Active Current for Read (1) Flash VCC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low VCC Lock Out Voltage Symbol ILI ILO ICCx32 ISB VOL VOH ICC1 ICC2 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC SCS# = VIH, OE# = VIH, VOUT = GND to VCC SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5 FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 8mA, VCC = 4.5 IOH = -4.0mA, VCC = 4.5 FCS# = VIL, OE# = SCS# = VIH FCS# = VIL, OE# = SCS# = VIH IOL = 8.0mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 µA, VCC = 4.5 Min Max 10 10 620 80 0.4 2.4 260 300 0.45 0.85 x VCC VCC -0.4 3.2 4.2 Unit µA µA mA mA V V mA mA V V V V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY SRAM AC CHARACTERISTICS SRAM AC CHARACTERISTICS VCC = 5.0V, -55°C ≤ TA ≤ +125°C VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Read Cycle Symbol -25 Min Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 Units Parameter Write Cycle Max 25 25 0 25 15 3 0 12 12 ns ns ns ns ns ns ns ns ns Symbol Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time 1. This parameter is guaranteed by design but not tested. -25 Min tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH Units Max 25 20 20 15 20 3 0 3 ns ns ns ns ns ns ns ns ns ns 15 0 1. This parameter is guaranteed by design but not tested. FIGURE 2 – AC TEST CIRCUIT AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level I OL Current Source VZ ≈ 1.5V D.U.T. Unit V ns V V Notes: V Z is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. (Bipolar Supply) C eff = 50 pf Typ VIL = 0, VIH = 3.0 5 1.5 1.5 I OH Current Source White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 3 – SRAM TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA tRC SCS# ADDRESS tCLZ SOE# tOH DATA I/O tCHZ tACS tAA PREVIOUS DATA VALID tOE tOLZ DATA VALID DATA I/O tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH) READ CYCLE 2, (SWE# = FCS# = VIH) FIGURE 4 – SRAM WRITE CYCLE - SWE# CONTROLLED tWC ADDRESS tAW tAH tCW SCS# tAS tWP SWE# tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH) FIGURE 5 – SRAM WRITE CYCLE - SCS# CONTROLLED tWC ADDRESS tAS tAW tAH tCW SCS# tWP SWE# tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH) White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -120 Min Unit Max Write Cycle Time tAVAV tWC 120 ns Chip Select Setup Time tELWL tCS 0 ns ns Write Enable Pulse Width tWLWH tWP 50 Address Setup Time tAVWL tAS 0 ns Data Setup Time tDVWH tDS 50 ns Data Hold Time tWHDX tDH 0 ns Address Hold Time tWLAX tAH 50 ns Write Enable Pulse Width High tWHWL tWPH 20 Duration of Byte Programming Operation (1) tWHWH1 Chip and Sector Erase Time (2) tWHWH2 Read Recovery Time Before Write tGHWL ns 300 µs 15 sec 0 VCC Set-up Time tVCS µs 50 µs Chip Programming Time 11 sec Output Enable Setup Time tOES 0 ns Output Enable Hold Time (4) tOEH 10 ns Chip Erase Time (3) 64 sec NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 4. For Toggle and Data# Polling. FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -120 Min Unit Max Read Cycle Time tAVAV tRC 120 ns Address Access Time tAVQV tACC 120 ns Chip Select Access Time tELQV tCE 120 ns OE# to Output Valid tGLQV tOE 50 ns Chip Select to Output High Z (1) tEHQZ tDF 30 ns OE# High to Output High Z (1) tGHQZ tDF Output Hold from Address, FCS# or OE# Change, whichever is first tAXQX tOH 30 0 ns ns 1. Guaranteed by design, not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -120 Min Write Cycle Time tAVAV tWC FWE# Setup Time tWLEL FCS# Pulse Width tELEH Address Setup Time Unit Max 120 ns tWS 0 ns tCP 50 ns tAVEL tAS 0 ns Data Setup Time tDVEH tDS 50 ns Data Hold Time tEHDX tDH 0 ns Address Hold Time tELAX tAH 50 ns FCS# Pulse Width High tEHEL tCPH 20 ns 300 µs 15 sec Chip Programming Time 11 sec Chip Erase Time (3) 64 sec Duration of Programming Operation (1) tWHWH1 Sector Erase Time (2) tWHWH2 Read Recovery Time tGHEL 0 ns NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 6 – AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS tRC Addresses Addresses Stable tACC FCS# tDF tOE OE# FWE# Outputs tCE tOH High Z Output Valid High Z NOTE: SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 7 – WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED Data# Polling Addresses 5555H PA tWC tAS PA tAH tRC FCS# tGHWL OE# tWP FWE# tWHWH1 tWPH tCS tDH A0H Data tDF tOE D7# PD DOUT tDS tOH 5.0 V tCE NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 8 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY tAS Addresses 5555H tAH 2AAAH 5555H 5555H 2AAAH SA FCS# tGHWL OE# tWP FWE# tWPH tCS Data tDH AAH 55H 80H AAH 55H 10H/30H tDS VCC tVCS Notes: 1. SA is the sector address for Sector Erase. 2. SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 9 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY t CH FCS# t DF t OE OE# tOEH FWE# tCE t OH D7 = Valid Data D7# D7 High Z tWHWH 1 or 2 D0-D7 Valid Data D0-D6 = Invalid D0-D6 t OE D7 Valid Data D7 D7 High Z tWHWH 1 or 2 Note: SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 10 – WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED Data# Polling Addresses 5555H PA tWC PA tAH tAS FWE# tGHEL OE# tCP FCS# tWHWH1 tCPH tWS tDH A0H Data D7# PD DOUT tDS 5.0 V NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 6. SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) 25.15 (0.990) ± 0.26 (0.010) SQ 4.57 (0.180) MAX 22.36 (0.880) ± 0.26 (0.010) SQ 0.27 (0.011) ± 0.04 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.03 (0.946) ± 0.26 (0.010) 0.19 (0.007) ± 0.06 (0.002) 1° / 7° 1.0 (0.040) ± 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 0.38 (0.015) ± 0.05 (0.002) 20.3 (0.800) REF The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WSF41632-22XX PRELIMINARY PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.385) ± 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.81 (0.150) ± 0.1 (0.005) 1.27 (0.050) ± 0.1 (0.005) 0.76 (0.030) ± 0.1 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W S F 41632 - 22 X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509) ACCESS TIME (ns) 22 = 25ns SRAM and 120ns FLASH ORGANIZATION, 128K x 32 Flash PROM SRAM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October, 2002 Rev. 4 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com