88 CY7C188 32K x 9 Static RAM Features provided by an active-LOW chip enable (CE1), an active-HIGH chip enable (CE2), an active-LOW output enable (OE), and three-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. • High speed — 15 ns • Automatic power-down when deselected • Low active power — 660 mW • Low standby power — 140 mW • CMOS for optimum speed/power • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE features Writing to the device is accomplished by taking CE1 and write enable (WE) inputs LOW and CE2 input HIGH. Data on the nine I/O pins (I/Oo – I/O8) is then written into the location specified on the address pins (A0 – A14). Reading from the device is accomplished by taking CE1 and OE LOW while forcing WE and CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Functional Description The CY7C188 is a high-performance CMOS static RAM organized as 32,768 words by 9 bits. Easy memory expansion is The nine input/output pins (I/O0 – I/O8) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C188 is available in standard 300-mil-wide SOJs. Logic Block Diagram Pin Configuration DIP/SOJ Top View NC NC A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 INPUT BUFFER SENSE AMPS I/O2 ROW DECODER A0 A1 A2 A3 A4 A5 A6 I/O1 32K x 9 ARRAY I/O0 I/O1 I/O2 I/O3 GND I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A14 CE2 WE A13 A9 A10 A11 OE A12 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 I/O5 C188–2 I/O6 CE1 CE2 WE OE POWER DOWN COLUMN DECODER I/O7 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 I/O8 C188–1 Selection Guide 7C188–20 7C188–25 7C188–35 Maximum Access Time (ns) 7C188–15 15 20 25 35 Maximum Operating Current (mA) Commercial 120 170 165 160 Maximum Standby Current (mA) 35 35 35 30 Cypress Semiconductor Corporation Document #: 38-05053 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C188 DC Input Voltage[1] ................................. –0.5V to VCC +0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC Relative to GND (Pin 32 to Pin 16) .......................................... –0.5V to + 7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range[2] 7C188–15 Parameter Description Test Conditions Min. Max 2.4 7C188–20 Min. Max. 2.4 7C188–25 Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 2.2 VCC + 0.3 VIL Input LOW Voltage[1] –0.5 0.8 –0.5 0.8 –0.5 IIX Input Load Current GND ≤ VI ≤ VCC –5 +5 –5 +5 IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled –5 +5 –5 +5 IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 120 ISB1 Automatic CE Power-Down Current— TTL Inputs Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL, VIN ≥ VIH or VIN ≤ VIL, f = fMAX ISB2 Automatic CE Power-Down Current — CMOS Inputs Max. VCC, CE1 ≥ VCC –0.3V or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V, f = 0 0.4 2.4 0.4 7C188–35 Min. Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC + 0.3 V 0.8 –0.5 0.8 V –5 +5 –5 +5 µA –5 +5 –5 +5 µA –300 –300 mA 170 165 160 mA 35 35 35 30 mA 10 15 15 15 mA Capacitance[4] Parameter Description CIN: Addresses Input Capacitance CIN: Controls Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 8 pF 8 pF Notes: 1. Minimum voltage is equal to –2.0V for pulse durations less than 20 ns. 2. .See the last page of this specification for Group A subgroup testing information. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05053 Rev. ** Page 2 of 8 CY7C188 AC Test Loads and Waveforms[5, 6] R1 481Ω R1 481Ω 5V 5V OUTPUT ALLINPUTPULSES OUTPUT R2 255Ω 30 pF INCLUDING JIGAND SCOPE Equivalent to: 3.0V R2 255Ω 5 pF INCLUDING JIGAND SCOPE (a) (b) 90% 10% 90% 10% GND ≤ 3 ns ≤ 3 ns C188–3 C188–4 THÉ VENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[2, 5] 7C188–15 Parameter Description Min. Max. 7C188–20 Min. Max. 7C188–25 Min. Max. 7C188–35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW or CE2 HIGH to Data Valid 15 20 25 35 ns tDOE OE LOW to Data Valid 7 9 10 16 ns tLZOE OE LOW to Low Z 15 20 15 3 [7] tHZOE OE HIGH to High Z tLZCE CE1 LOW or CE2 HIGH to Low Z[7] 20 3 0 [6,7] 7 tHZCE CE1 HIGH or CE2 LOW to High Z tPU CE1 LOW or CE2 HIGH to Power-Up tPD CE1 HIGH or CE2 LOW to Power-Down 0 25 9 0 15 35 11 0 20 ns 15 3 11 ns ns 15 0 20 ns ns 3 3 9 ns 3 3 3 7 35 3 0 3 [6, 7] 25 ns ns 20 ns WRITE CYCLE[8, 9] tWC Write Cycle Time 15 20 25 35 ns tSCE CE1 LOW or CE2 HIGH to Write End 10 15 18 22 ns tAW Address Set-Up to Write End 10 15 20 30 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 10 15 18 22 ns tSD Data Set-Up to Write End 8 10 10 15 ns tHD Data Hold from Write End 0 0 0 0 ns tHZWE tLZWE WE LOW to High Z [6] 0 WE HIGH to Low Z [6, 7] 3 Document #: 38-05053 Rev. ** 7 0 3 7 0 3 11 0 3 15 ns ns Page 3 of 8 CY7C188 Switching Characteristics Over the Operating Range[2, 5] 7C188–15 Parameter Description Min. Max. 7C188–20 Min. Max. 7C188–25 Min. 7C188–35 Max. Min. Max. Unit Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1, LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Switching Waveforms Read Cycle No. 1[10,11] tRC ADDRESS tAA tOHA DATA OUT DATA VALID PREVIOUS DATA VALID C188–5 Read Cycle No. 2 (Chip-Enable Controlled) [11,12,13] tRC CE1 tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C188–6 Write Cycle No. 1 (WE Controlled)[8,13,14,15] Document #: 38-05053 Rev. ** Page 4 of 8 CY7C188 Switching Waveforms (Continued) tWC ADDRESS CE1 tAW tHA tSA tPWE WE OE tSD DATA I/O NOTE 16 tHD DATA IN VALID tHZOE C188–7 Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Timing parameters are the same for all chip enable signals (CE1 and CE2), so only the timing for CE1 is shown. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in the output state and input signals should not be applied. [8,13,14,15] Write Cycle No.2 (CE Controlled) tWC ADDRESS tSCE CE1 tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID C188–8 Write Cycle No. 3 (WE Controlled, OE LOW)[9,13,15] Document #: 38-05053 Rev. ** Page 5 of 8 CY7C188 Switching Waveforms (Continued) tWC ADDRESS CE tAW tHA tSA WE tHD tSD NOTE 16 DATA I/O DATA IN VALID tLZWE tHZWE C188–9 Truth Table CE WE OE Input/Output Mode Power H X X High Z Deselect/Power-Down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C188–15VC V32 32-Lead (300-Mil) Molded SOJ Commercial 20 CY7C188–20VC V32 32-Lead (300-Mil) Molded SOJ Commercial 25 CY7C188–25VC V32 32-Lead (300-Mil) Molded SOJ 35 CY7C188–35VC V32 32-Lead (300-Mil) Molded SOJ MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL Max. 1, 2, 3 Document #: 38-05053 Rev. ** Parameter Subgroups IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 ISB1 1, 2, 3 ISB2 1, 2, 3 Page 6 of 8 CY7C188 Switching Characteristics Parameter Subgroups READ CYCLE tRC 7, 8, 9, 10, 11 tAA 7, 8, 9, 10, 11 tOHA 7, 8, 9, 10, 11 tACE 7, 8, 9, 10, 11 tDOE 7, 8, 9, 10, 11 WRITE CYCLE tWC 7, 8, 9, 10, 11 tSCE 7, 8, 9, 10, 11 tAW 7, 8, 9, 10, 11 tHA 7, 8, 9, 10, 11 tSA 7, 8, 9, 10, 11 tPWE 7, 8, 9, 10, 11 tSD 7, 8, 9, 10, 11 tHD 7, 8, 9, 10, 11 Package Diagrams 32-Lead (300-Mil) Molded SOJ V32 Document #: 38-05053 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C188 Document Title: CY7C188 32K x 9 Static RAM Document Number: 38-05053 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107155 09/10/01 SZV Change from Spec number: 38-00220 to 38-05053 Document #: 38-05053 Rev. ** Page 8 of 8