PRELIMINARY CY24141-3 MediaClock™ Graphics Clock Generator Features Benefits • Integrated phase-locked loop (PLL) High-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy output Meets critical timing requirements in complex system designs • 3.3V operation with 2.5V/1.68V output Enables application compatibility • Ultra-linear crystal capacitors Ensures 0PPM Accuracy Part Number Outputs Input Frequency Range CY24141-3 2 18.432 MHz Output Frequencies 18.432 MHz, 53.94605395 MHz/54 MHz (selectable) Logic Block Diagram CLK_A 18.432 MHz XIN Q OSC XOUT OUTPUT DIVIDER Φ VCO CLK_B (selectable) P PLL FS AVDD VDDL AVSS VSSL VDD VSS Pin Configurations CY24141ZC-3 16-pin TSSOP CY24141 Frequency Select Table 16 XOUT 2 15 3 14 4 13 CLK_A N/C VSS AVSS 5 12 N/C VSSL 6 11 VDDL N/C N/C 7 10 8 9 N/C CLK_B XIN VDD 1 AVDD FS Cypress Semiconductor Corporation Document #: 38-07324 Rev. ** • Frequency Select PPM CLK_B Unit 1 –1.000073 53.94605395 MHz 0 0 54 MHz 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 4, 2002 PRELIMINARY CY24141-3 Pin Summary Pin Name Pin Number Pin Description XIN 1 Reference Input VDD 2 Voltage Supply AVDD 3 Analog Voltage Supply FS 4 Frequency Select Pin (Internal Pull-down Resistor) AVSS 5 Analog Ground VSSL 6 Output Ground N/C 7 No Connect N/C 8 No Connect CLK_B 9 53.94605395-MHz/54-MHz Clock Output (Frequency Selectable) @ VDDL level N/C 10 No Connect VDDL 11 Output Voltage Supply for CLK_B N/C 12 No Connect VSS 13 Ground N/C 14 No Connect CLK_A 15 18.432-MHz Clock Output XOUT[1] 16 Reference Output Absolute Maximum Conditions Parameter Description Min. Max. Unit AVDD Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C TJ Junction Temperature 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V 2000 V Electrostatic Discharge Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit AVDD Analog Voltage Supply 3.15 3.45 3.6 V VDD Voltage Supply 3.15 3.45 3.6 V VDDLH 2.5V Output Voltage Supply 2.25 2.5 2.75 V VDDLL 1.68V Output Voltage Supply 1.63 1.68 1.75 V TA Ambient Temperature CLOAD Max Load Capacitance fREF Reference Frequency 0 18.432 85 °C 15 pF MHz Note: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07324 Rev. ** Page 2 of 6 PRELIMINARY CY24141-3 DC Electrical Characteristics Parameter IOH3.3 IOL3.3 IOH2.5 IOL2.5 IOH1.68 IOL1.68 VIH VIL RI CIN XLDCAP IIZ IDD Description Output High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Resistor Input Capacitance Crystal Load Capacitance Input Leakage Current Supply Current Conditions VOH = VDD – 0.5, VDD = 3.3 V VOL = 0.5, VDD = 3.3 V VOH = VDDL – 0.5, VDDL = 2.5 V VOL = 0.5, VDDL = 2.5 V VOH = VDDL – 0.5, VDDL = 1.68 V VOL = 0.5, VDDL = 1.68 V FS Frequency Select Input FS Frequency Select Input FS Frequency Select Pull Down Resistor Min. 12 12 8 8 6 6 70% Typ. 24 24 20 20 12 12 80 100 Internal Load Caps Max. 30% 135 7 12.9 5 30 Sum of Core and Output Current 10 35 Unit mA mA mA mA mA mA VDD VDD kohm pF pF µA mA Cycle-Cycle Jitter Specifications (VDD = 3.15V–3.6V) Parameter t9 t9 Description Clock Jitter–peak-peak Clock Jitter–peak-peak t9 Clock Jitter–peak-peak t9 Clock Jitter–peak-peak t9 Clock Jitter–peak-peak Conditions Cycle-Cycle Jitter–18.432 MHz Cycle-Cycle Jitter–54 MHz VDDL = 1.63V–1.75V Cycle-Cycle Jitter–54 MHz VDDL = 2.25V–2.75V Cycle-Cycle Jitter–53.94605395 MHz VDDL = 1.63V–1.75V Cycle-Cycle Jitter–53.94605395 MHz VDDL = 2.25V–2.75V 1σ 12 32 Typ. 55 135 Max. 140 220 Unit ps ps 11 70 150 ps 31 160 220 ps 11 70 150 ps Conditions 1000-Cycle-Cycle Jitter–18.432 MHz 1000-Cycle-Cycle Jitter–54 MHz VDDL = 1.63V–1.75V 1000-Cycle-Cycle Jitter–54 MHz VDDL = 2.25V–2.75V 1000-Cycle-Cycle Jitter–53.94605395 MHz–VDDL = 1.63V–1.75V 1000-Cycle-Cycle Jitter–53.94605395 MHz–VDDL = 2.25V–2.75V 1σ 19 55 Typ. 95 275 Max. 140 400 Unit ps ps 50 275 400 ps 293 1025 1200 ps 290 1025 1200 ps Min. Typ. –119 –95 –92 Max. Unit dBc dBc dBc 1000-cycle Jitter (VDD = 3.15V–3.6V) Parameter Description Clock Jitter–peak-peak t10 Clock Jitter–peak-peak t10 t10 Clock Jitter–peak-peak t10 Clock Jitter–peak-peak t10 Clock Jitter–peak-peak Phase Noise Specifications Parameter Description Phase Noise Phase Noise Phase Noise Conditions 18.432 MHz @ 10-kHz offset 54 MHz @ 10-kHz offset 53.94605395 MHz @ 10-kHz offset AC Electrical Characteristics (VDD = 3.15V–3.6V) Description Parameter[3] Frequency Error Fppm Fppm Frequency Error Conditions Min. Typ. Max. Part to Part (three lots tested on same board, PCB board ±5 ±10 can vary more than ±5 ppm) Over temperature from 0 to 85°C (crystal should not be ±2 ±5 heated for this test, only IC) Unit ppm ppm Note: 3. Not 100% tested. Document #: 38-07324 Rev. ** Page 3 of 6 PRELIMINARY CY24141-3 AC Electrical Characteristics (VDD = 3.15V–3.6V) (continued) Parameter[3] DC t3 t4 t5 Description Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate PLL Lock Time Conditions Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20%–80% of VDD/ VDDL = 2.5V Output Clock Fall Time, 80%–20% of VDD/ VDDL = 2.5V Min. Typ. Max. 45 50 55 0.8 1.4 0.8 1.4 3 Unit % V/ns V/ns ms Test Circuit AVDD t1 CLK out 0.1 µF t2 CLOAD OUTPUTS CLK 50% VDD 0.1 µF Figure 1. Duty Cycle Definition; DC = t2/t1 t3 GND t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions VDD 80% t5 Stable @ ±0.1% frequency Figure 3. PLL Lock Time ... t10 t9B t9A ... t10 Figure 5. 1000-Cycle Jitter Figure 4. Cycle-Cycle Jitter Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24141ZC-3 Z16 16-TSSOP Commercial 3.3V Document #: 38-07324 Rev. ** Page 4 of 6 PRELIMINARY CY24141-3 16-lead Thin Shrunk Small Outline Package (4.40-MM Body) Z16 51-85091 MediaClock is a trademark of Cypress Semiconductor. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07324 Rev. ** Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY24141-3 Document Title: CY24141-3 MediaClock™ Graphics Clock Generator Document Number: 38-07324 REV. ECN NO. Issue Date Orig. of Change ** 111593 04/30/02 CKN Document #: 38-07324 Rev. ** Description of Change New Data Sheet Page 6 of 6