WINBOND W681512S

W681512
SINGLE-CHANNEL VOICEBAND CODEC
Data Sheet
-1-
Publication Release Date: September, 2007
Revision C14
W681512
1. GENERAL DESCRIPTION
The W681512 is a general-purpose single channel PCM CODEC with pin-selectable μ-Law or A-Law
companding. The device is compliant with the ITU G.712 specification. It operates from a single +5V
power supply and is available in 20-pin SOG (SOP), SSOP and TSSOP package. Functions
performed include digitization and reconstruction of voice signals, and band limiting and smoothing
filters required for PCM systems. The filters are compliant with ITU G.712 specification. W681512
performance is specified over the industrial temperature range of –40°C to +85°C.
The W681512 includes an on-chip precision voltage reference and an additional power amplifier,
capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is
fully differential, reducing noise and improving the power supply rejection ratio. The data transfer
protocol supports both long-frame and short-frame synchronous communications for PCM
applications, and IDL and GCI communications for ISDN applications. W681512 accepts seven
master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically
determines the division ratio for the required internal clock.
ApplIcations
2. FEATURES
•
VoIP, Voice over Networks equipment
•
Single +5V power supply
•
•
Typical power dissipation of 30 mW,
power-down mode of 0.5 μW
Digital telephone and communication
systems
•
Wireless Voice devices
•
Fully-differential analog circuit design and
output signals
•
DECT/Digital Cordless phones
•
Differential Analog Outputs
•
Broadband Access Equipment
•
On-chip precision reference of 1.575 V for
a 0 dBm TLP at 600 Ω (775mVRMS)
•
Bluetooth Headsets
•
Fiber-to-curb equipment
•
Push-pull power amplifiers with external
gain adjustment with 300 Ω load capability
•
Enterprise phones
•
Digital Voice Recorders
•
Seven master clock rates of 256 kHz to
4.096 MHz
•
Pin-selectable
μ-Law
and
A-Law
companding (compliant with ITU G.711)
•
CODEC A/D and D/A filtering compliant
with ITU G.712
•
Industrial temperature range (–40°C to
+85°C)
•
Packages: 20-pin SOG (SOP), SSOP and
TSSOP
•
Pb-Free package options available
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W681512
3. BLOCK DIAGRAM
Re
Int
PC
cei
erf
M
ve
ace
Receive
PCM
Interface
BCLKR
FSR
PCMR
G.712 CODEC
G.711 μ/A -Law
Tra Int
ns PC erf
mitM ace
Transmit
PCM
Interface
BCLKT
FST
PCMT
PAO+
PAOPAI
RORO+
RO
AO
AI+
AIμ/A-Law
512 kHz
256 kHz
Voltage reference
V AG
8 kHz
PUI
Power Conditioning
VDD
256 kHz,
512 kHz,
1536 kHz,
1544 kHz,
2048 kHz,
2560 kHz
& 4096 kHz
Pre -Scaler
scaler
VSS
MCLK
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Publication Release Date: April, 2007
Revision C14
W681512
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8
7.1. Transmit Path ................................................................................................................................ 8
7.2. Receive Path ................................................................................................................................. 9
7.3. Power Management..................................................................................................................... 10
7.3.1. Analog and Digital Supply ..................................................................................................... 10
7.3.2. Analog Ground Reference Voltage Output ...........................................................................10
7.4. PCM Interface .............................................................................................................................. 10
7.4.1. Long Frame Sync.................................................................................................................. 10
7.4.2. Short Frame Sync ................................................................................................................. 11
7.4.3. General Circuit Interface (GCI) ............................................................................................. 11
7.4.4. Interchip Digital Link (IDL)..................................................................................................... 12
7.4.5. System Timing ...................................................................................................................... 12
8. TIMING DIAGRAMS.......................................................................................................................... 13
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
9.1. Absolute Maximum Ratings ......................................................................................................... 20
9.2. Operating Conditions ................................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21
10.1. General Parameters .................................................................................................................. 21
10.2. Analog Signal Level and Gain Parameters ...............................................................................22
10.3. Analog Distortion and Noise Parameters ..................................................................................23
10.4. Analog Input and Output Amplifier Parameters.........................................................................24
10.5. Digital I/O ................................................................................................................................... 26
10.5.1. μ-Law Encode Decode Characteristics...............................................................................26
10.5.2. A-Law Encode Decode Characteristics ..............................................................................27
10.5.3. PCM Codes for Zero and Full Scale ...................................................................................28
10.5.4. PCM Codes for 0dBm0 Output ...........................................................................................28
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 29
12. PACKAGE SPECIFICATION .......................................................................................................... 31
12.1. 20L SOG (SOP)-300mil ............................................................................................................. 31
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W681512
12.2. 20L SSOP-209 mil ..................................................................................................................... 33
12.3. 20L TSSOP - 4.4X6.5mm .......................................................................................................... 35
13. ORDERING INFORMATION........................................................................................................... 36
14. VERSION HISTORY ....................................................................................................................... 37
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Publication Release Date: April, 2007
Revision C14
W681512
5. PIN CONFIGURATION
RO+
ROPAI
PAOPAO+
VDD
FSR
PCMR
BCLKR
PUI
1
20
2
19
3
18
4
17
5
6
7
SINGLE
CHANNEL
CODEC
16
15
14
8
13
9
12
10
11
SOG/SSOP/TSSOP
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VAG
AI+
AIAO
/A
μ/A-Law
VSS
FST
PCMT
BCLKT
MCLK
W681512
6. PIN DESCRIPTION
Pin
Name
Pin
No.
Functionality
RO+
1
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
RO-
2
Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 1.575
volt peak referenced to the analog ground level.
PAI
3
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
4
Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced
to the VAG voltage level.
PAO+
5
Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak
referenced to the VAG voltage level.
VDD
6
Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.
FSR
7
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR
8
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
9
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
MCLK
11
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have
the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the
case of 256 and 512 kHz frequency.
BCLKT
12
PCM transmit bit clock input pin.
PCMT
13
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST
14
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
VSS
15
This is the supply ground. This pin should be connected to 0V.
μ/A-Law
16
Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law
companding is selected when this pin is tied to VSS.
AO
17
Analog output of the first gain stage in the transmit path.
AI-
18
Inverting input of the first gain stage in the transmit path.
AI+
19
Non-inverting input of the first gain stage in the transmit path.
VAG
20
Mid-Supply analog ground pin, which supplies a 2.4 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to VSS with a 0.01μF to 0.1 μF capacitor. This pin
becomes high impedance when the chip is powered down.
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Publication Release Date: April, 2007
Revision C14
W681512
7. FUNCTIONAL DESCRIPTION
W681512 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a
complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply
with the specifications of the ITU-T G.711 recommendation.
The block diagram in section 3 shows the main components of the W681512. The chip consists of a
PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.
The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample
rate with the external frame sync frequency. The power conditioning block provides the internal
power supply for the digital and the analog section, while the voltage reference block provides a
precision analog ground voltage for the analog signal processing. The main CODEC block diagram
is shown in section 3.
VA
V AG
G
+
-
-
+
Receive Path
PAO+
PAO PAI
8
μ/A-Contr
Control
ol
D/A
+
RO +
Converter
w
-
RO -
fC= 3400Hz
Hz
Smoothi
Smoothing
n Filter
1
Smoothing
Smoothi
n Filter
2
Transmit Path
AO
8
A/D
Converter
μ μ/A- /A
Control
Contr
ffCC == 200Hz
200
Hz Pass
High
High
Filte
Filter
Pas
++
-
fC== 3400Hz
3400
Hz
AntAliasing
Ant
-Aliasi
i Filter
n
AI+
AI -
Ant-Aliasi
Ant-Aliasing
Filter
Figure 7.1 The W681512 Signal Path
7.1. Transmit Path
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain
setting (see application examples in section 11). The device has an input operational amplifier whose
output is the input to the encoder section. If the input amplifier is not required for operation it can be
powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or
the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The
input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected
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W681512
as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see
Table 7.1).
AI+
Input Amplifier
Input
VDD
Powered Down
AO
1.2 to VDD-1.2
Powered Up
AI+, AI-
VSS
Powered Down
AI-
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the
analog ground voltage VAG.
The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched
capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of
input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is
filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the
recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is
digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or ALaw format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression
format can be selected according to Table 7.2.
μ/A-Law Pin
Format
VSS
A-Law
VDD
μ-Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the
data rate supplied by the external BCLKT.
7.2. Receive Path
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the differential receive output signals RO+ and RO-. The RO+ or RO- outputs can
be externally connected to the PAI pin to provide a differential output with high driving capability at the
PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings
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Publication Release Date: April, 2007
Revision C14
W681512
of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered
down by connecting PAI to VDD.
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681512 must be 5V +/- 10%. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF
ceramic capacitor.
7.3.2. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 μF to a 0.1 μF ceramic capacitor.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
BCLKR
FSR
Interface Mode
64 kHz to 4.096 MHz
8 kHz
Long or Short Frame Sync
VSS
VSS
ISDN GCI with active channel B1
VSS
VDD
ISDN GCI with active channel B2
VDD
VSS
ISDN IDL with active channel B1
VDD
VDD
ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8
kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC
sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when
the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The
length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge
occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin
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W681512
PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data
word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame
Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted.
The internal decision logic will determine whether the next frame sync is a long or a short frame sync,
based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high
impedance for two frame sync cycles after every power down state. More detailed timing information
can be found in the interface timing section.
7.4.2. Short Frame Sync
The W681512 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681512 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681512 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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Publication Release Date: April, 2007
Revision C14
W681512
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channel. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz
master clock rates. The system clock is supplied through the master clock input MCLK and can be
derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8
kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW
for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the
W681512 will enter the low power standby mode. Another way to power down is to set the PUI pin to
LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
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W681512
8. TIMING DIAGRAMS
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFSL
FST
TFTRH
BCLKT
0
TFTRS
1
TFTFH
2
3
TFDTD
TBCKH
4
5
6
7
TBDTD
PCMT
D7
D6
8
0
D4
D3
D2
1
TBCK
THID
THID
D5
TBCKL
D1 D0
MSB
LSB
TFS
TFSL
FSR
TFRRH
BCLKR
0
TFRRS
1
TFRFH
2
3
TBCKH
4
5
6
7
8
TBCKL
0
1
TBCK
PCMR
D7
MSB
TDRS
D6
D5
D4
D3
D2
D1 D0
LSB
TDRH
Figure 8.1 Long Frame Sync PCM Timing
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Publication Release Date: April, 2007
Revision C14
W681512
SYMBOL
DESCRIPTION
1/TFS
FST, FSR Frequency
1
MIN
TYP
MAX
---
8
---
TBCK
UNIT
kHz
TFSL
FST / FSR Minimum LOW Width
sec
1/TBCK
BCLKT, BCLKR Frequency
64
---
4096
TBCKH
BCLKT, BCLKR HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT, BCLKR LOW Pulse Width
50
---
---
ns
TFTRH
BCLKT 0 Falling Edge to FST Rising
Edge Hold Time
20
---
---
ns
TFTRS
FST Rising Edge to BCLKT 1 Falling
edge Setup Time
80
---
---
ns
TFTFH
BCLKT 2 Falling Edge to FST Falling
Edge Hold Time
50
---
---
ns
TFDTD
FST Rising Edge to Valid PCMT Delay
Time
---
---
60
ns
TBDTD
BCLKT Rising Edge to Valid PCMT
Delay Time
---
---
60
ns
THID
Delay Time from the Later of FST
Falling Edge, or
10
---
60
ns
kHz
BCLKT 8 Falling Edge to PCMT Output
High Impedance
TFRRH
BCLKR 0 Falling Edge to FSR Rising
Edge Hold Time
20
---
---
ns
TFRRS
FSR Rising Edge to BCLKR 1 Falling
edge Setup Time
80
---
---
ns
TFRFH
BCLKR 2 Falling Edge to FSR Falling
Edge Hold Time
50
---
---
ns
TDRS
Valid PCMR to BCLKR Falling Edge
Setup Time
0
---
---
ns
TDRH
PCMR Hold Time from BCLKR Falling
Edge
50
---
---
ns
Table 8.1 Long Frame Sync PCM Timing Parameters
1
TFSL must be at least ≥ TBCK
- 14 -
W681512
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFTFH
TFTFS
FST
TFTRS
TFTRH
BCLKT
-1
0
TBCKH
1
2
3
TBDTD
D7
PCMT
4
5
6
7
0
8
TBDTD
D6
D5
TBCKL
TBCK
THID
D4
D3
D2
1
D1 D0
MSB
LSB
TFS
TFRFH
TFRFS
FSR
TFRRS
TFRRH
BCLKR
-1
0
TBCKH
1
2
3
4
5
6
7
TBCKL
0
8
1
TBCK
PCMR
D7
MSB
TDRS
D6
D5
D4
D3
D2
D1 D0
LSB
TDRH
Figure 8.2 Short Frame Sync PCM Timing
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Publication Release Date: April, 2007
Revision C14
W681512
SYMBOL
DESCRIPTION
MIN
TYP
MAX
1/TFS
FST, FSR Frequency
---
8
---
kHz
1/TBCK
BCLKT, BCLKR Frequency
64
---
4096
kHz
TBCKH
BCLKT, BCLKR HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT, BCLKR LOW Pulse Width
50
---
---
ns
TFTRH
BCLKT –1 Falling Edge to FST Rising Edge Hold
Time
20
---
---
ns
TFTRS
FST Rising Edge to BCLKT 0 Falling edge Setup
Time
80
---
---
ns
TFTFH
BCLKT 0 Falling Edge to FST Falling Edge Hold Time
50
---
---
ns
TFTFS
FST Falling Edge to BCLKT 1 Falling Edge Setup
Time
50
---
---
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay Time
10
---
60
ns
THID
Delay Time from BCLKT 8 Falling Edge to PCMT
Output High Impedance
10
---
60
ns
TFRRH
BCLKR –1 Falling Edge to FSR Rising Edge Hold
Time
20
---
---
ns
TFRRS
FSR Rising Edge to BCLKR 0 Falling edge Setup
Time
80
---
---
ns
TFRFH
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time
50
---
---
ns
TFRFS
FSR Falling Edge to BCLKR 1 Falling Edge Setup
Time
50
---
---
ns
TDRS
Valid PCMR to BCLKR Falling Edge Setup Time
0
---
---
ns
TDRH
PCMR Hold Time from BCLKR Falling Edge
50
---
---
ns
Table 8.2 Short Frame Sync PCM Timing Parameters
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UNIT
W681512
TFS
FST
TFSFH
TFSRS
TFSRH
BCLKT
-1
0
1
TBCKH
2
3
4
5
TBDTD
PCMT
6
8
9
THID
TBDTD
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
TDRS
PCMR
7
10
11 12
LSB
15 16
17
18
TBCK
THID
TBDTD
D7 D6 D5 D4 D3 D2
D1 D0
LSB
MSB
TDRS
D7 D6 D5 D4 D3 D2 D1 D0
14
TBDTD
TDRH
MSB
13
TBCKL
TDRH
D7 D6 D5 D4 D3 D2
MSB
BCH = 0
B1 Channel
D1 D0
LSB
BCH = 1
B2 Channel
Figure 8.3 IDL PCM Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFS
FST Frequency
---
8
---
kHz
1/TBCK
BCLKT Frequency
256
---
4096
kHz
TBCKH
BCLKT HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT LOW Pulse Width
50
---
---
ns
TFSRH
BCLKT –1 Falling Edge to FST Rising Edge
Hold Time
20
---
---
ns
TFSRS
FST Rising Edge to BCLKT 0 Falling edge
Setup Time
60
---
---
ns
TFSFH
BCLKT 0 Falling Edge to FST Falling Edge
Hold Time
20
---
---
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay
Time
10
---
60
ns
THID
Delay Time from the BCLKT 8 Falling Edge
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
10
---
50
ns
TDRS
Valid PCMR to BCLKT Falling Edge Setup
Time
20
---
---
ns
TDRH
PCMR Hold Time from BCLKT Falling Edge
75
---
---
ns
Table 8.3 IDL PCM Timing Parameters
- 17 -
Publication Release Date: April, 2007
Revision C14
W681512
TFS
FST
TFSFH
TFSRS
TFSRH
TBCKH
TBCKL
BCLKT
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TFDTD
PCMT
TBDTD
TBDTD
D7 D6 D5 D4 D3 D2 D1 D0
TDRS
D7 D6 D5 D4 D3 D2
D1 D0
LSB
TDRS
TDRH
TDRH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
MSB
THID
TBDTD TBCK
LSB MSB
MSB
PCMR
THID
D1 D0
LSB
LSB MSB
BCH = 0
B1 Channel
BCH = 1
B2 Channel
Figure 8.4 GCI PCM Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
1/TFST
FST Frequency
1/TBCK
---
8
---
kHz
BCLKT Frequency
512
---
6176
kHz
TBCKH
BCLKT HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT LOW Pulse Width
50
---
---
ns
TFSRH
BCLKT 0 Falling Edge to FST Rising Edge Hold Time
20
---
---
ns
TFSRS
FST Rising Edge to BCLKT 1 Falling edge Setup Time
60
---
---
ns
TFSFH
BCLKT 1 Falling Edge to FST Falling Edge Hold Time
20
---
---
ns
TFDTD
FST Rising Edge to Valid PCMT Delay Time
---
---
60
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay Time
---
---
60
ns
THID
Delay Time from the BCLKT 16 Falling Edge (B1
channel) or BCLKT 32 Falling Edge (B2 Channel) to
PCMT Output High Impedance
10
---
50
ns
TDRS
Valid PCMR to BCLKT Rising Edge Setup Time
20
---
---
ns
TDRH
PCMR Hold Time from BCLKT Rising Edge
---
---
60
ns
Table 8.4 GCI PCM Timing Parameters
- 18 -
UNIT
W681512
SYMBOL
DESCRIPTION
1/TMCK
Master Clock Frequency
TYP
MIN
---
256
MAX
---
UNIT
kHz
512
1536
1544
2048
2560
4096
TMCKH /
TMCK
MCLK Duty Cycle for 256 kHz
Operation
45%
TMCKH
Minimum Pulse Width HIGH for
MCLK(512 kHz or Higher)
50
---
---
ns
TMCKL
Minimum Pulse Width LOW for MCLK
(512 kHz or Higher)
50
---
---
ns
TFTRHM
MCLK falling Edge to FST Rising Edge
Hold Time
50
---
---
ns
TFTRSM
FST Rising Edge to MCLK Falling edge
Setup Time
50
---
---
ns
TRISE
Rise Time for All Digital Signals
---
---
50
ns
TFALL
Fall Time for
---
---
50
ns
All Digital Signals
55%
Table 8.5 General PCM Timing Parameters
- 19 -
Publication Release Date: April, 2007
Revision C14
W681512
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS
Condition
Value
Junction temperature
1500C
Storage temperature range
-650C to +1500C
Voltage Applied to any pin
(VSS - 0.3V) to (VDD + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VDD + 1.0V)
VDD - VSS
-0.5V to +6V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. OPERATING CONDITIONS
Condition
Value
0
0
Industrial operating temperature
-40 C to +85 C
Supply voltage (VDD)
+4.5V to +5.5V
Ground voltage (VSS)
0V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
- 20 -
W681512
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Conditions
Min (2)
Typ (1)
Max (2)
Units
0.6
V
Symbol
Parameters
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOL
PCMT Output LOW Voltage
IOL = 3 mA
VOH
PCMT Output HIGH Voltage
IOL = -3 mA
IDD
VDD Current (Operating) - ADC + DAC
No Load
6
8
mA
ISB
VDD Current (Standby)
FST & FSR =Vss ;
PUI=VDD
10
100
μA
Ipd
VDD Current (Power Down)
PUI= Vss
0.1
10
μA
IIL
Input Leakage Current
VSS<VIN<VDD
+/-10
μA
IOL
PCMT Output Leakage Current
VSS<PCMT<VDD
+/-10
μA
10
pF
15
pF
2.4
V
0.4
VDD –
0.4
V
V
High Z State
CIN
Digital Input Capacitance
COUT
PCMT Output Capacitance
PCMT High Z
1. Typical values: TA = 25°C , VDD = 5.0 V
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
- 21 -
Publication Release Date: April, 2007
Revision C14
W681512
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;
MCLK=BCLK= 2.048MHz; FST=FSR=8kHz synchronous operation
PARAMETER
SYM.
Absolute
Level
LABS
Max. Transmit
Level
TXMAX
Absolute Gain
(0 dBm0 @
1020 Hz;
TA=+25°C)
CONDITION
TYP.
0 dBm0 = 0dBm @ 600Ω
1.096
TRANSMIT
(A/D)
RECEIVE
(D/A)
MIN.
MAX.
MIN.
MAX.
---
---
---
---
0.775
UNIT
VPK
VRMS
3.17 dBm0 for μ-Law
1.579
---
---
---
---
VPK
3.14 dBm0 for A-Law
1.573
---
---
---
---
VPK
GABS
0 dBm0 @ 1020 Hz;
TA=+25°C
0
-0.25
+0.25
-0.25
+0.25
dB
Absolute Gain
variation with
Temperature
GABST
TA=0°C to TA=+70°C
0
-0.03
+0.03
-0.03
+0.03
dB
-0.05
+0.05
-0.05
+0.05
Frequency
Response,
GRTV
TA=-40°C to TA=+85°C
Relative to
0dBm0 @
1020 Hz
Gain Variation
vs. Level Tone
(1020 Hz
relative to –10
dBm0)
GLT
15 Hz
---
---
-40
-0.5
0
50 Hz
---
---
-30
-0.5
0
60 Hz
---
---
-26
-0.5
0
200 Hz
---
-1.0
-0.4
-0.5
0
300 to 3000 Hz
---
-0.20
+0.15
-0.20
+0.15
3300 Hz
---
-0.35
+0.15
-0.35
+0.15
3400 Hz
---
-0.8
0
-0.8
0
3600 Hz
---
---
0
---
0
4000 Hz
---
---
-14
---
-14
4600 Hz to 100 kHz
---
---
-32
---
-30
+3 to –40 dBm0
---
-0.3
+0.3
-0.2
+0.2
-40 to –50 dBm0
---
-0.6
+0.6
-0.4
+0.4
-50 to –55 dBm0
---
-1.6
+1.6
-1.6
+1.6
- 22 -
dB
dB
W681512
10.3. ANALOG DISTORTION AND NOISE PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;
MCLK=BCLK= 2.048MHz; FST=FSR=8kHz synchronous operation
PARAMETER
Total Distortion vs.
Level Tone (1020 Hz,
μ-Law, C-Message
Weighted)
Total Distortion vs.
Level Tone (1020 Hz,
A-Law, Psophometric
Weighted)
Spurious Out-Of-Band
at RO+ (300 Hz to
3400 Hz @ 0dBm0)
SYM.
DLTμ
CONDITION
TRANSMIT (A/D)
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
36
---
---
34
---
---
36
---
---
36
---
---
-40 dBm0
29
---
---
30
---
---
-45 dBm0
25
---
---
25
---
---
+3 dBm0
36
---
---
34
---
---
36
---
---
36
---
---
-40 dBm0
29
---
---
30
---
---
-45 dBm0
25
---
---
25
---
---
4600 Hz to 7600 Hz
---
---
---
---
---
-30
7600 Hz to 8400 Hz
---
---
---
---
---
-40
8400 Hz to 100000 Hz
---
---
---
---
---
-30
+3 dBm0
0 dBm0 to -30 dBm0
DLTA
0 dBm0 to -30 dBm0
DSPO
RECEIVE (D/A)
UNIT
dBC
dBp
dB
Spurious In-Band (700
Hz to 1100 Hz @
0dBm0)
DSPI
300 to 3000 Hz
---
---
-47
---
---
-47
dB
Intermodulation
Distortion (300 Hz to
3400 Hz –4 to –21
dBm0
DIM
Two tones
---
---
-41
---
---
-41
dB
Crosstalk (1020 Hz @
0dBm0)
DXT
---
---
-75
---
---
-75
dBm0
Absolute Group Delay
τABS
1200Hz
---
---
360
---
---
240
μsec
Group Delay
Distortion (relative to
group delay @ 1200
Hz)
τD
500 Hz
---
---
750
---
---
750
μsec
600 Hz
---
---
380
---
---
370
1000 Hz
---
---
130
---
---
120
2600 Hz
---
---
130
---
---
120
2800 Hz
---
---
750
---
---
750
μ-Law; C-message
---
---
18
---
---
13
dBrnc0
A-Law; Psophometric
---
---
-68
---
---
-78
dBm0p
Idle Channel Noise
NIDL
- 23 -
Publication Release Date: April, 2007
Revision C14
W681512
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;
PARAMETER
SYM.
CONDITION
MIN.
TYP.
MAX.
UNIT.
AI Input Offset Voltage
VOFF,AI
AI+, AI-
---
---
±25
mV
AI Input Current
IIN,AI
AI+, AI-
---
±0.1
±1.0
μA
AI Input Resistance
RIN,AI
AI+, AI- to VAG
10
---
---
MΩ
AI Input Capacitance
CIN,AI
AI+, AI-
---
---
10
pF
AI Common Mode Input Voltage
Range
VCM,AI
AI+, AI-
1.2
---
VDD-1.2
V
AI Common Mode Rejection Ratio
CMRRTI
AI+, AI-
---
60
---
dB
AI Amp Gain Bandwidth Product
GBWTI
AO, RLD≥10kΩ
---
2150
---
kHz
AI Amp DC Open Loop Gain
GTI
AO, RLD≥10kΩ
---
95
---
dB
AI Amp Equivalent Input Noise
NTI
C-Message Weighted
---
-24
---
dBrnC
AO Output Voltage Range
VTG
RLD=10kΩ to VAG
0.5
---
VDD-0.5
V
RLD=2kΩ to VAG
1.0
---
VDD-1.0
Load Resistance
RLDTGRO
AO, RO to VAG
2
---
---
kΩ
Load Capacitance
CLDTGAO
AO
---
---
100
pF
Load Capacitance
CLDTGRO
RO
---
---
500
pF
AO & RO Output Current
IOUT1
0.5 ≤AO,RO+, RO-≤ VDD0.5
±1.0
---
---
mA
RO+, RO- Output Resistance
RRO+, RO-
RO+, RO-, 0 to 3400 Hz
---
1
---
Ω
RO+, RO- Output Offset Voltage
VOFF,RO+,RO-
RO+ to VAG
---
---
±25
mV
Analog Ground Voltage
VAG
Relative to VSS
2.2
2.4
2.6
V
VAG Output Resistance
RVAG
Within ±25mV change
---
2.5
12.5
Ω
Power Supply Rejection Ratio (0 to
100 kHz to VDD, C-message)
PSRR
Transmit
30
80
---
dBC
Receive
30
75
---
PAI Input Offset Voltage
VOFF,PAI
PAI
---
---
±25
mV
PAI Input Current
IIN,PAI
PAI
---
±0.05
±1.0
μA
PAI Input Resistance
RIN,PAI
PAI to VAG
10
---
---
MΩ
PAI Amp Gain Bandwidth Product
GBWPI
PAO- no load
---
1000
---
kHz
Output Offset Voltage
VOFF,PO
PAO+ to PAO-
---
---
±50
mV
Load Resistance
RLDPO
PAO+, PAO- differentially
300
---
---
Ω
Load Capacitance
CLDPO
PAO+, PAO- differentially
---
---
1000
pF
PO Output Current
IOUTPO
VSS + 0.7 ≤PAO- or PAO+≤
VDD-0.7
±10.0
---
---
mA
PO Output Resistance
RPO
PAO+ to PAO-
---
1
---
Ω
- 24 -
W681512
PARAMETER
SYM.
CONDITION
MIN.
TYP.
MAX.
UNIT.
-0.2
0
+0.2
dB
dBC
PO Differential Gain
GPO
RLD=300Ω, +3dBm0, 1 kHz,
PAO+ to PAO-
PO Differential Signal to Distortion
C-Message weighted
DPO
ZLD=300Ω
45
60
---
ZLD=100nF + 100Ω
---
40
---
ZLD=100nF + 20Ω
---
40
---
0 to 4 kHz
40
55
---
4 to 25 kHz
---
40
---
PO Power Supply Rejection Ratio
(0 to 25 kHz to VDD, Differential
out)
PSRRPO
- 25 -
Publication Release Date: April, 2007
Revision C14
dB
W681512
10.5. DIGITAL I/O
10.5.1. μ-Law Encode Decode Characteristics
Normalized
Encode
Decision
Levels
8159
Normalized
Digital Code
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
1
0
0
0
0
0
0
0
7903
1
0
0
0
1
1
1
1
4063
1
0
0
1
1
1
1
1
2015
1
0
1
0
1
1
1
1
991
1
0
1
1
1
1
1
1
479
1
1
0
0
1
1
1
1
223
1
1
0
1
1
1
1
1
95
99
:
:
35
231
:
:
103
495
:
:
239
1023
:
:
511
2079
:
:
1055
4191
:
:
2143
8031
:
:
4319
Decode
Levels
1
1
1
0
1
1
1
1
31
33
:
:
3
1
1
1
1
1
1
1
1
0
2
1
1
1
1
1
1
1
1
0
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
- 26 -
W681512
10.5.2. A-Law Encode Decode Characteristics
Normalized
Encode
Decision
Levels
4096
Digital Code
Normalized
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
1
0
1
0
1
0
1
0
3968
1
0
1
0
0
1
0
1
2048
1
0
1
1
0
1
0
1
1024
1
0
0
0
0
1
0
1
512
1
0
0
1
0
1
0
1
256
1
1
1
0
0
1
0
1
128
1
1
1
0
0
1
0
1
64
66
:
:
2
132
:
:
68
264
:
:
136
528
:
:
272
1056
:
:
544
2112
:
:
1088
4032
:
:
2048
Decode
Levels
1
1
0
1
0
1
0
1
1
0
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
- 27 -
Publication Release Date: April, 2007
Revision C14
W681512
10.5.3. PCM Codes for Zero and Full Scale
μ-Law
Level
A-Law
Sign bit
Chord bits
Step bits
Sign bit
Chord bits
Step bits
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
+ Full Scale
1
000
0000
1
010
1010
+ Zero
1
111
1111
1
101
0101
- Zero
0
111
1111
0
101
0101
- Full Scale
0
000
0000
0
010
1010
10.5.4. PCM Codes for 0dBm0 Output
μ-Law
Sample
A-Law
Sign bit
Chord bits
Step bits
Sign bit
Chord bits
Step bits
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
1
0
001
1110
0
011
0100
2
0
000
1011
0
010
0001
3
0
000
1011
0
010
0001
4
0
001
1110
0
011
0100
5
1
001
1110
1
011
0100
6
1
000
1011
1
010
0001
7
1
000
1011
1
010
0001
8
1
001
1110
1
011
0100
- 28 -
W681512
11. TYPICAL APPLICATION CIRCUIT
VDD
17
AO
27K
18
19
AI+
27K
27K
MCLK
20
2
VAG
RO-
1
PCMR
BCLKR
FSR
RO+
0.01 uF
3
14
12
13
8 KHz Frame Sy nc
2.048 MHz
Bit Clock
11
PCM OUT
8
9
7
PCM IN
PAI
VDD
4
PAO-
5
PAO+
DIFFERENTIAL
AUDIO OUT
RL > 2K ohms
+
W681512
VSS
1.0 uF
FST
BCLKT
PCMT
AI-
u/A
PUI
16
10
MODE SELECT
POWER CONTROL
15
1.0 uF
DIFFERENTIAL
AUDIO IN
+
VDD
U2
27K
6
0.1 uF
Figure 11.1 Typical circuit for Differential Analog I/O’s
VDD
27K
18
AUDIO IN
19
27K
1.0 uF
27K
20
2
1
0.01 uF
AUDIO OUT
RL > 2K ohms
27K
3
27K
4
5
AUDIO OUT
RL > 150 ohms
100 uF
AO
FST
BCLKT
PCMT
AIAI+
MCLK
VAG
RO-
PCMR
BCLKR
FSR
RO+
14
12
13
8 KHz Frame Sy nc
2.048 MHz
Bit Clock
11
PCM OUT
8
9
7
PCM IN
PAI
PAOPAO+
W681512
VSS
1.0 uF
u/A
PUI
16
10
MODE SELECT
POWER CONTROL
15
17
VDD
U3
27K
6
0.1 uF
Figure 11.2 Typical circuit for Single Ended Analog I/O’s
- 29 -
Publication Release Date: April, 2007
Revision C14
W681512
VDD
1K
0.1 uF
6
22 uF
U4
+
1.0 uF
3.9K
100pF
18
1.0 uF
3.9K
19
100pF
ELECTRET
MICROPHONE
20
2
62K
0.01 uF
1
27K
27K
3
1.5K
27K
4
5
AO
FST
BCLKT
PCMT
AIAI+
MCLK
VAG
RO-
PCMR
BCLKR
FSR
RO+
14
12
13
8 KHz Frame Sy nc
2.048 MHz
Bit Clock
11
PCM OUT
8
9
7
PCM IN
PAI
PAOPAO+
W681512
u/A
PUI
VSS
17
VDD
62K
16
10
MODE SELECT
POWER CONTROL
15
1.5K
SPEAKER
Figure 11.3 Handset Interface
VDD
1.0 uF
19
20
2
600
27K
1
0.01 uF
TRANSFORMER
600 OHM 1:1
3
27K
4
5
AO
FST
BCLKT
PCMT
AIAI+
MCLK
VAG
RO-
PCMR
BCLKR
FSR
RO+
PAO+
8 KHz Frame Sy nc
2.048 MHz
Bit Clock
11
PCM OUT
8
9
7
PCM IN
B1/B2 SELECT
PAO-
W681512
u/A
PUI
Figure 11.4 Transformer Interface Circuit in GCI mode
- 30 -
14
12
13
PAI
VSS
18
15
17
27K
VDD
U5
27K
6
0.1 uF
16
10
MODE SELECT
POWER CONTROL
W681512
12. PACKAGE SPECIFICATION
12.1. 20L SOG (SOP)-300MIL
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS
11
20
c
E
H
E
L
10
1
O
D
0.25
A
Y
SEATING PLANE
e
GAUGE PLANE
A1
b
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Publication Release Date: September, 2005
Revision C13
W681512
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
MAX.
MIN.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
b
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.013
E
7.40
7.60
0.291
0.299
D
12.60
13.00
0.496
0.512
e
1.27 BSC
0.050 BSC
HE
10.00
10.65
0.394
0.419
Y
-
0.10
-
0.004
L
0.40
1.27
0.016
0.050
0
0º
8º
0º
8º
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W681512
12.2. 20L SSOP-209 MIL
SHRINK SMALL OUTLINE PACKAGE DIMENSIONS
D
11
20
DTEAIL A
H
E
E
1
10
A2
b
A
SEATING PLANE
SEATING PLANE
θ
L
Y
L1
e
b
A1
DETAIL A
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Publication Release Date: September, 2005
Revision C13
W681512
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
-
-
2.00
-
-
0.079
A1
0.05
-
-
0.002
-
-
A2
1.65
1.75
1.85
0.065
0.069
-
b
0.22
-
0.38
0.009
-
0.015
c
0.09
-
0.25
0.004
-
0.010
D
6.90
7.20
7.50
0.272
0.283
0.295
E
5.00
5.30
5.60
0.197
0.209
0.220
HE
7.40
7.80
8.20
0.291
0.307
0.323
e
-
0.65
-
-
0.0256
-
L
0.55
0.75
0.95
0.021
0.030
0.037
L1
-
1.25
-
-
0.050
-
Y
-
-
0.10
-
-
0.004
0
0º
-
8º
0
-
8º
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W681512
12.3. 20L TSSOP - 4.4X6.5MM
PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS
SYMBOL
A
MIN.
-
DIMENSION (MM)
NOM.
MAX.
1.20
MIN.
-
DIMENSION (INCH)
NOM.
MAX.
0.047
A1
0.05
-
0.15
0.002
-
0.006
A2
0.80
0.90
1.05
0.031
0.035
0.041
E
4.30
4.40
4.50
0.169
0.173
0.177
6.50
6.60
0.252
0.60
0.75
0.020
HE
6.40 BSC
D
6.40
L
0.50
L1
b
1.00 REF
0.19
e
c
0
Y
.252 BSC
-
0º
0.260
0.024
0.030
0.039 REF
0.30
0.007
0.65 BSC
0.09
0.256
-
0.012
0.026 BSC
-
0.20
0.004
-
8º
0º
0.10 BASIC
-
0.008
-
8º
0.004 BASIC
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Publication Release Date: September, 2005
Revision C13
W681512
13. ORDERING INFORMATION
Winbond Part Number Description
W681512_ _
Product Family
W681512 Product
Package Material:
Blank
=
Standard Package
G
=
Pb-free Package
Package Type:
S
=
20-Lead Plastic Small Outline Package (SOG/SOP)
R
=
20-Lead Plastic Shrink Small Outline Package (SSOP)
WG
=
20-Lead Free Plastic Thin Shrink Small Outline Package (TSSOP)
When ordering W681512 series devices, please refer to the following part numbers.
Part Number
W681512S*
W681512R*
W681512SG
W681512RG
W681512WG
*All Pb packages will be available for a limited time. Thus, Pb-free
packages are strongly recommended.
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W681512
14. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A10
March 25,
2003
A11
April 2,
2003
7
VAG: fixed the voltage value from 2.5V to 2.4V
B11
July, 2004
2
6
Added reference to SSOP package. Revised Applications
section.
32
Added reference to SSOP package.
33
Added description of SSOP package.
First revision
Added R package ordering code.
C11
November,
2004
2
Added reference to TSSOP package and Pb-free packaging.
6
Added reference to TSSOP package.
32
Added description of TSSOP package.
33
Added W and G package ordering code.
22
Extended conditions on Table 10.2.
23
Extended conditions on Table 10.3.
Corrected Idle Channel Noise min/max and units.
29
Improved Application Diagram.
30
Improved Application Diagram.
Add Important Notice
C12
April 2005
37
C13
September
, 2005
29, 30
Various
2, 22
C14
April, 2007
Improved Applications Diagram
Capilatized Logic HIGH/LOW
Added reference to VRMS
31
SOP Package diagram legible
33
SSOP Package diagram legible
35
TSSOP Package diagram legible
36
Removed Pb TSSOP Package
36
Footnote on Pb parts limited availability
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
- 37 -
Publication Release Date: September, 2005
Revision C13
W681512
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
The information contained in this datasheet may be subject to change without
notice. It is the responsibility of the customer to check the Winbond USA website
(www.winbond-usa.com) periodically for the latest version of this document, and
any Errata Sheets that may be generated between datasheet revisions.
- 38 -